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ND-100
Reference manual
Norsk Data ND-100 Reference Manual
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Contents
Table of Contents
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Table of Contents
Table of Contents
General Characteristics
General
ND- 700 Central Processing Unit (CPU) Module
CPU Characteristics
ND- 700 Architecture
General
ND-100 Configuration Examples
Multiprocessor Systems
Remote Operation
The Interrupt System
The Memory Management System
The Memory System
Main Memory
Cache Memory
The Input/Output System
Programmed Input/Output - PIO
Direct Memory Access - DMA
Nd- 700 Peripheral Equipment
Nd- 700 Software
The Operating System
Supporting Software
Distributed Data Processing
System Description
General
Central Processor
The Address Arithmetic
Instruction Fetch
Prefetch
Instruction Execution
Main Arithmetic
The Register File
Status Indicators
The Interrupt System
General
Functional Description
The External Interrupt System
The Internal Interrupt System
Internal Hardware Status Interrupts
Reset of the IIC Register
Programmming Control of the Interrupt System
Programmming the PID and PIE Registers
The WAIT, ION and IOF Instruction
The Previous Level Register, PVL
Vectored Interrupts and the IDENT Instructions
The Memory Management System
General
Memory Management Architecture
The Paging System
The Shadow Memory
The
Page Used and Written in Page
Page Table Selection
Memory Protection System
Page Protection System
Ring Protection System
Privileged Instructions
Memory Management Control and Status
The PON and POF Instructions
Paging Control Registers
Paging Status Register
The SEX and REX Instructions
Memorysystem
General
ND- 700 Memory Architecture
Local (Main) Memory
The Position Code
The Thumbwheel Setting
Memory Error Correction
Memory Control and Status
Error Correction Control Register (ECCR)
Memory Status Regsiters (PEA and PES)
Multiport Memory
Big Multiport Memory (BMPM)
Multiport Memory 4 (MPM4)
Cache Memory
Cache Memory Architecture
Cache Memory Organization
Cache Control and Status
Cache Control
2.4.6.3.2 Cache Status Register
Nd- 700 Input/ Output System
General
The ND-100 Bus
Programmed Input/Output - PIO
The Input/Output Instruction -- Lox
Interface Channels and Registers
Control and Status Register
Direct Memory Access (DMA)
General
DMA Controller Operation
Initialization
Transfer
Termination and Status Check
General Considerations
The I/O System and the Interrupt System
General
Interrupt Level Usage
Device Interrupt Identification
Programming Specifications for |/O Device on the CPU Board
The Real-Time Clock
The Current Loop Interface
General
Bus Extender Architecture
Nd-Ioo Instructions
General
Instruction and Data Formats
Single Bit
Bit Byte
16 Bit Word
32 Bit Double Word
48 Bit Floating Point Word
The Instruction Repertoire
Memory Reference Instructions
Addressing Structure
Store Instructions
Load Instructions
Arithmetical and Logical Instructions
Sequencing Instructions
Byte Instructions
Extended BYTE-Instructions
Register Instructions
Floating Point Conversion Instructions
Standard 48 Bit Floating Point Conversion
3.2.2.1.2 Optional 32 Bit Floating Point Conversion
Shift Instructions
Register Operations
ROP - Register Operation Instructions
Extended Register Operation Instructions
Skip Instructions
Argument Instructions
Bit Operation Instructions
Bit Skip Instructions
Bit Set Instructions
3.2.2.6.3 One Bit Accumulator Instructions
System Control Instructions
Monitor Call Instruction
Inter-Level Register Instructions
Input/Output Control Instructions
Extension of the Device Register Address
System Control Instructions
Interrupt Control Instructions
Wait or Give up Priority
Examine and Deposit
Load Writeable Control Store
Format of Instructions
Addressing
Instructions in the «Commercial Extended
Decimal Instructions
Data Formats for Decimal Instructions
Packed Decimal Number
ASCII Coded Decimal Number
The Decimal Instructions
Stack Handling Instructions
Data Structure Operated Upon by the Instructions
Operator's Interaction
Control Panel Push Buttons
The Panel Lock Key
Status Indicators
General Considerations
Control Functions
System Control
Master Clear
Stop
ALD Load
Continue Program
General Load
Leave MOPC
Program Execution
Start Program
Instruction Breakpoint
Manual Instruction
Single I/O Instruction Function
Singleinstruction
Miscellaneous Functions
Current Location Counter
Delete Entry
Internal Memory Test
Monitor Functions
Memory Functions
Physical Examine Mode
Virtual Examine Mode
Memory Examine
Memory Deposit
Deposit Rules
Memory Dump
Register Functions
Register Examine
Register Deposit
Register Dump Rd
Userregisteru
Operator Panel Switch Register - OPR
Internal Register Examine
Internal Register Functions
Internal Register Deposit
Display Functions
Displayed Format
Display Memory Bus
Display Activity
Bootstrap Loaders
Binary Format Load
Mass Storage Load
Automatic Load Descriptor
General
The Different Display Functions
Model 33 Asr/Ksr Teletype Code (Ascii) in Binary Form
Andident Codes
Internal Registers
Switch Settings for the Different Nd-100 Modules
Switches on the CPU Module (3002)
ALD - Automatic Load Descriptor
Console: Speed Setting for Console Terminal
Floppy Disk System
Terminal Group
Initial Baud Rate for Terminals
Survey
Control Functions (Does Not Affect DISPLAY
Display Functions (Affects Only DISPLAY
Nd-Ioo Technical Specifications
Specifications
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Quick Links
1
Nd-100 Configuration Examples
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Reference Manual
ND-06.014.02
NORSK DATA A.S
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