Micronas SDA 6000 Manuals

Manuals and User Guides for Micronas SDA 6000. We have 1 Micronas SDA 6000 manual available for free PDF download: User Manual

Micronas SDA 6000 User Manual

Micronas SDA 6000 User Manual (412 pages)

Teletext Decoder with Embedded 16-bit Controller M2

Brand: Micronas | Category: Media Converter | Size: 2 MB

Table of Contents

Table of Contents
4
D/A Converter

12
- Overview
  14
- Figure 1-1 M2 Tool Flow
  16
- Features
  18
  - Logic Symbol
    20
Pin Descriptions

21
C16X Microcontroller

38
- On-Chip Microcontroller RAM and SFR Area
  41
  - System Stack
    42
  - General Purpose Registers
    43
  - PEC Source and Destination Pointers
    44
    
    Special Function Registers
    45
    
    External Memory
    47
  - Sdram
    49
  - Figure 4-6 Interlocked Access Cycles to ROM and SDRAM
    50
  - Memory Mapping
    51
  - Figure 4-8 Memory Mapping
    52
  - External Static Memory Devices
    53
    
    Register Description
    54
    
    Figure 4-9 Four-Phase Handshake
    56
  - Crossing Memory Boundaries
    58
- Central Processing Unit
  60
Interrupt and Trap Functions

89
- Interrupt System Structure
  90
  - Hardware Traps
    92
  - Figure 5-1 Priority Levels and PEC Channels
    96
- Operation of the PEC Channels
  100
- Trap Functions
  114
  - System Reset
    118
  - External Interrupt Source Control
    120
    
    Behavior of I/Os During Reset
    125
    
    The Internal RAM after Reset
    126
  - System Start-Up Configuration
    127
  - Register Write Protection
    129
  - Power Reduction Modes
    133
  - Dedicated Pins
    137
  - XBUS Configuration
    139
  - Watchdog Timer
    140
  - Bootstrap Loader
    144
  - Identification Registers
    146
    
    CPU Identification
    149
- Parallel Ports
  150
- Peripherals
  
  162
- Sync System
  
  291
  - Figure 9-1 M2'S Display Timing
    292
  - Sync Interrupts
    293
  - Register Description
    294
    
    And Pixel Layer Area
    299
- Display Generator
  
  305
- Slicer and Acquisition
  
  357
  - Distortion Processing
    358
  - Data Separation
    359
  - H/V-Synchronization
    360
    
    FC-Check
    361
    
    Interrupts
    362
    
    Figure 12-2 VBI Buffer: General Structure
    363
    
    Register Description
    364
    
    RAM Registers
    366
    
    Recommended Parameter Settings
    380
- Register Overview
  
  385
  - Registers Ordered by Context
    386
  - Registers Ordered by Address
    395
    
    Registers in SFR Area
    396
    
    Registers in ESFR Area
    397
- Electrical Characteristics
  
  402
  - DC Characteristics
    403
  - Timings
    409
  - Package Outlines
    410

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