Micronas SDA 6000 User Manual

Teletext decoder with embedded 16-bit controller m2

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Edition March 1, 2001

6251-557-1

USER'S MANUAL

SDA 6000

Teletext Decoder

with Embedded

16-bit Controller

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Page 1 USER’S MANUAL SDA 6000 Teletext Decoder with Embedded 16-bit Controller Edition March 1, 2001 6251-557-1...
Page 2 ASC: Autobaud Detection Feature included IC: New Description GPT: New Description IIC changed to I For questions on technology, delivery and prices please contact the Micronas Offices in Germany or the Micronas GmbH Companies and Representatives worldwide: see our webpage at http://www.micronas.com...
Page 3 Contents Overview...
Page 4: Table Of Contents
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Overview ..........1 - 3 Features .
Page 5 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Reset ..........6 - 3 6.1.1...
Page 6 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 7.3.4.2 Baud Rate Selection and Calculation ..... 7 - 67 7.3.4.3 Overwriting Registers on Successful Autobaud Detection ..7 - 69 7.3.5...
Page 7 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 10.5.2 Transfer Areas ........10 - 20 10.5.3...
Page 8 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 14.1 Absolute Maximum Ratings ....... . . 14 - 3 14.2...
Page 9 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Figure 1-1 M2 Tool Flow ......... . 1 - 5 Figure 1-2 Logic Symbol .
Page 10 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Figure 7-13 Auxiliary Timer of Timer Block 1 in Capture Mode... . . 7 - 18 Figure 7-14 Structure of Timer Block 2 ....... 7 - 19 Figure 7-15 Block Diagram of Core Timer T6 in Timer Mode .
Page 11 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Figure 10-2 Behavior of Blank Pin for Consecutive Frames in ‘Meshed’ Regions........10 - 5 Figure 10-3 Priority of Layers in Overlapped Layer Mode.
Page 12: D/A Converter
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Preface M2 is a 16-bit controller based on Infineon’s C16x core with embedded teletext and graphic controller functions. M2 can be used for a wide range of TV and OSD applications. This document provides complete reference information on the hardware of M2.
Page 13 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Related Documentation For easier understanding of this specification it is recommended to read the documentation listed in the following table. Moreover it gives an overview of the software drivers which are available for M2.
Page 14: Overview
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Overview Overview M2 is designed to provide absolute top performance for a wide spectrum of teletext and graphic applications in standard and high end TV-sets and VCRs. M2 contains a data caption unit, a display unit and a high performance Infineon C16x based microcontroller (so that M2 becomes a one chip TV-controller) an up to level 3.5 teletext decoder and...
Page 15 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Overview supports SDRAMs as well as ROMs or FLASH ROMs. The organization of the memory is linear, so that it is easy to program the chip for graphic purposes. The SW development environment “MATE” is available to simplify and speed up the development of the software and displayed information.
Page 16: Figure 1-1 M2 Tool Flow
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Overview SIE-MATE Tool Concept: Fast Prototyping on the PC New Tool Generation User Interface User Interface Events and Object Editor Simulator Action Editor Converter Display data C Code info M2 formatted data, C Compiler...
Page 17 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Overview Standard Tool Chain For the M2 software development (documentation, coding, debugging and test) the Infineon C166 microcontroller family standard tools can be used: These are ASCII editor, structogram editor, compiler, assembler, linker. Debugging is supported by low-priced ROM-Monitor debuggers or the OCDS (On Chip Debug Support) debugger.
Page 18: Features
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Overview Teletext Decoder with Embedded 16-bit Controller Version 2.1 CMOS Features General • Level 1.5, 2.5, 3.5 WST Display Compatible • Fast External Bus Interface for SDRAM (Up to 8 MByte) and ROM or Flash-ROM (Up to 4 MByte) P-MQFP-128-2 •...
Page 19 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Overview • High-speed Synchronous Serial Interface (SSC). Full- and Half-duplex synchronous up to 16.5 Mbaud • 3 Independent, HW-supported Multi Master/Slave I C Channels at 400 Kbit/s • 16-Bit Watchdog Timer (WDT) • Real Time Clock (RTC) •...
Page 20: Logic Symbol
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Overview Logic Symbol DD(3.3 V) Address XTAL1 16 Bit XTAL2 RSTIN Data CVBS1A 16 Bit CVBS1B CVBS2 Port 2 8 Bit Port 3 15 Bit BLANK HSYNC Port 4 6 Bit VSYNC Port 5...
Page 21: Pin Descriptions
Pin Description...
Page 22 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Pin Descriptions Pin Descriptions 2 - 3 Micronas...
Page 23: Pin Diagram (Top View)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Pin Descriptions Pin Diagram (top view) P-MQFP-128-2 P6.2 P6.3 P6.4 P6.5 DD33-5 P6.6 SS33-5 VSYNC HSYNC COR/RSTOUT BLANK/CORBLA DD33-8 SS33-8 XTAL1 DD33-4 XTAL2 SS33-4 SSA-1 DDA-1 P-MQFP-128-2 LDQM UDQM CSROM SSA-2 CLKEN DDA-2...
Page 24: Pin Definitions And Functions
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Pin Descriptions Pin Definitions and Functions Table 2-1 Pin Definition and Functions Pin Name Second Dir. Function Function R0/C0 Address bit (All addresses are word addresses)/SDRAM Address bit R1/C1 Address bit/SDRAM address bit...
Page 25 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Pin Descriptions Table 2-1 Pin Definition and Functions (cont’d) Pin Name Second Dir. Function Function – Data bit – Data bit – Data bit – Data bit – Data bit – Data bit –...
Page 26 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Pin Descriptions Table 2-1 Pin Definition and Functions (cont’d) Pin Name Second Dir. Function Function – Analog output for green channel – Analog output for blue channel RSTOUT Output for contrast reduction/Reset output...
Page 27 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Pin Descriptions Table 2-1 Pin Definition and Functions (cont’d) Pin Name Second Dir. Function Function P3.9 MTSR General purpose I/O port/SSC master- transmit/slave-receiver O/I P3.10 TxD0 General purpose I/O port/ASC0 clock/data output P3.11...
Page 28 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Pin Descriptions Table 2-1 Pin Definition and Functions (cont’d) Pin Name Second Dir. Function Function – Data output for JTAG interface – Control signal for JTAG interface TMODE – Testmode pin – Analog ground SSA-1 –...
Page 29 Architectural Overview...
Page 30: Figure 3-1 M2 Top Level Block Diagram
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Architectural Overview Architectural Overview Figure 3-1 M2 Top Level Block Diagram 3 - 3 Micronas...
Page 31 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Architectural Overview The architecture of M2 comprises of a 16-bit microcontroller which is derived from the well known Infineon Technologies C16x controller family. Due to the core philosophy of M2, the architecture of the CPU core is the same as described in other Infineon Technologies C16x derivatives.
Page 32 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Architectural Overview The screen refresh unit is used to read the frame buffer pixel by pixel in real time and to process the transparency and RGB data. A color look up table (CLUT) can be used to get the RGB data of the current pixel.
Page 33 C16X Microcontroller...
Page 34 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller C16X Microcontroller 4 - 3 Micronas...
Page 35 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Overview M2’s microcontroller and its peripherals are based on a Cell-Based Core (CBC) which is compatible to the well known C166 architecture. In M2, the CPU and its peripherals are generally clocked with 33.33 MHz which results in an instruction cycle time of 60 ns.
Page 36 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller • Hardware support for multiply and divide instructions Internal RAM (IRAM) The internal dual-port RAM is the physical support for the General Purpose Registers, the system stack and the PEC pointers. Due to its close connections with the CPU, the internal RAM provides fast access to these resources.
Page 37 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller OCDS The On-Chip Debug System allows the detection of specific events during user program execution through software and hardware breakpoints. An additional communication module allows communication between the OCDS and an external debugger, through a standard JTAG port.
Page 38: C16X Microcontroller
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Memory Organization In normal operation mode the memory space of the CPU is configured in a “Von Neumann” architecture. This means that code and data are accessed within the same memory areas, i. e. external memory, internal controller memory (IRAM), the address...
Page 39 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller External Memory SDRAM Boot ROM PMBUS ICACHE ROM1 C16X XBUS DCACHE ROM2 UED11214 Figure 4-1 M2 Memory Path Block Diagram All memory locations are byte and word readable. The internal memories (IRAM, XRAM) and the external dynamic memory (SDRAM) are byte and word writable, but external static memory is only word writable.
Page 40 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Figure 4-2 Storage of Words, Byte and Bits in a Byte Organized Memory Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) memory area.
Page 41: On-Chip Microcontroller Ram And Sfr Area
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller On-Chip Microcontroller RAM and SFR Area The IRAM/SFR area is located within data page 3, and provides access to 2 KByte of dual ported IRAM and two 512 Byte blocks of Special Function Registers (SFRs).
Page 42: System Stack
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Code accesses are always made through even byte addresses. The highest possible code storage location in the IRAM is either 00’FDFE for single word instructions, or 00’FDFC for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossings from IRAM to the SFR area are not supported and cause erroneous results.
Page 43: General Purpose Registers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller 4.3.2 General Purpose Registers The General Purpose Registers (GPRs) use a block of 16 consecutive words within the IRAM. The Context Pointer (CP) register determines the base address of the currently active register bank.
Page 44: Pec Source And Destination Pointers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller context. The number of implemented register banks (arbitrary sizes) is only limited by the size of the available internal RAM. 4.3.3 PEC Source and Destination Pointers The 16 word locations in the IRAM from 00’FCE0 to 00’FCFE...
Page 45: Special Function Registers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller 4.3.4 Special Function Registers The so-called Special Function Registers (SFRs) are provided to control internal functions of M2 (CPU, bus interface, Interrupt Controller, OCDS) or peripherals connected to the Peripheral Bus. These SFRs are arranged within two areas of 512 Bytes each.
Page 46 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Note: The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions. 4 - 15...
Page 47: External Memory
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller External Memory M2 provides an external bus interface (EBI) to access an external SDRAM, together with an external static memory device (ROM or SRAM). To optimize the overall system performance, access to both memory types is interlocked. Because of high performance requirements M2 provides only one bus type (Demultiplexed 16-bit Bus).
Page 48 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller memory size is limited by the number of external address lines. Up to 21 external address lines are configurable, thus devices providing up to 4 MByte of static external memory can be connected to M2.
Page 49: Sdram
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller External Bus Interface (EBI). The EBI handles access channels to four SDRAM banks within one SDRAM device and up to two static memory devices at 100 MHz. (For lower requirements the clock frequency can be reduced to 66 MHz, refer to Chapter 8).
Page 50: Figure 4-6 Interlocked Access Cycles To Rom And Sdram
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller address locations are in different SDRAM banks. Detailed timings and the specification of setup and hold conditions can be found in Chapter 14. MEMCLK CSSDRAM Read Write A(21:0) ROM_Adr SDRAM Data...
Page 51: Memory Mapping
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller MEMCLK Read Read Read Read SDRAM: 16 MBit, 2 Banks A (9:0) Bank 1 Bank 0 SDRAM: 64 MBit, 4 Banks A (9:0) Bank Y Bank X bx by A(13:12) Precharge...
Page 52: Figure 4-8 Memory Mapping
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller C16X Address-Space Address-Space Address-Space FF’FFFF FF’FFFF XBUS 80’0000 80’0000 60’0000 41’0000 41’0000 41’0000 40’0000 40’0000 PMBUS 01’8000 00’8000 00’0000 00’0000 UED11212 Figure 4-8 Memory Mapping from C16x address-space to EBI address-space for 1 64MBit SDRAM (D) and 2 16MBit static memory devices (S1, S2) is shown on the left (XBUS/ PMBUS overlap).
Page 53: External Static Memory Devices
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Access to segments 65 to 255 selects the XBUS. This address range (41’0000 FF’FFFF ) is not remapped by the C16x. b) Mapping by caches: In normal operation mode the address requested by the controller is not altered by ICACHE and DCACHE.
Page 54: Register Description
When executing a direct mode command the EBI shifts the contents of register EBIDIR into the SDRAM control lines. The Micronas SDRAM driver (refer to document list) provides appropriate functions for executing operations in direct mode.
Page 55 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller REDIR1 Reset Value: 00FF REDIR1_SEG (7:0) Function REDIR1_SEG For access to segment 255, the segment part of the address is (7:0) replaced by REDIR1_SEG. The configuration of the “External Bus Interface” and its operation mode is defined with the EBICON register.
Page 56: Figure 4-9 Four-Phase Handshake
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Phase EDMR EDMA UET11123 Figure 4-9 Four-Phase Handshake • Phase I: The controller requests a direct mode command which has not yet been executed by the EBI. The controller must not reset the EDMR bit until the EBI acknowledges the EDMA bit (EDMA polling required).
Page 57 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller The setting required for initiating a certain command on the SDRAM has to be written to the EBIDIR register before the direct mode request, the EDMR bit in the EBICON register is asserted.
Page 58: Crossing Memory Boundaries
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Function CSENA Chip Select Enable ‘0’: CS3 is active for 2nd ROM device ‘1’: CS3 is inactive The allocation of address ranges for the SDRAM banks is controlled through the SDRSZE bit.
Page 59 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller blocks (code or data) or areas requires special attention to ensure that the controller executes the desired operations. Memory Areas are partitions of the address space that represent different kinds of memory (if provided at all).
Page 60: Central Processing Unit
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Central Processing Unit Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and to store the previously calculated results.
Page 61: Instruction Pipelining
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Peripheral units are connected to the CPU by the peripheral bus or the XBUS and can work practically independent of the CPU. Data and control information is interchanged between the CPU and these peripherals by Special Function Registers (SFRs) or external memory locations, depending on to which bus they are connected.
Page 62 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller 1st –>FETCH: In this stage the instruction selected by the Instruction Pointer (IP) and the Code Segment Pointer (CSP) is fetched from either the program memory, internal RAM, or external memory.
Page 63: Figure 4-11 Sequential Instruction Pipelining
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Instruction pipelining increases the average instruction throughput considered over a certain period of time. In the following, any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing.
Page 64: Figure 4-13 Cache Jump Instruction Pipelining
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Cache Jump Instruction Processing The CPU incorporates a jump cache to optimize conditional jumps, which are processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time to fetch the branch target instruction can be saved, therefore causing the corresponding cache jump instruction to need only one machine cycle.
Page 65 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller possible conflicts (e.g. multiple usage of buses) in a time optimized way and thus usually avoids the pipeline being noticed by the user. However, there are some very rare cases, where the CPU, being a pipelined machine, requires attention by the programmer. In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance.
Page 66 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller : POP ; pop word value from new top of stack into Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved internally by the CPU logic. Controlling Interrupts Software modifications (implicit or explicit) of the PSW are done in the execute phase of the respective instructions.
Page 67: Bit-Handling And Bit-Protection
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Timing Instruction pipelining reduces the average instruction processing time on a wide scale (usually from four to one machine cycles). However, there are some rare cases where a particular pipeline situation causes the processing time for a single instruction to be extended either by a half or by one machine cycle.
Page 68: Instruction State Times
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller realization through special programming (see “Particular Pipeline Effects” on page 33). Protected bits are not changed during the read-modify-write sequence, i.e. when hardware sets e.g. an interrupt request flag between the read and the write of the read- modify-write sequence.
Page 69: Cpu Special Function Registers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Execution from external memory strongly depends on the selected bus mode and the programming of the bus cycles (wait-states). The operand and instruction accesses listed below can extend the execution time of an instruction: •...
Page 70 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller SYSCON Reset Value: 0400 STKSZ(2..0) XPEN Function XPEN XBUS Peripheral Enable Bit ‘0’: Accesses to the on-chip X-Peripherals and their functions are disabled. ‘1’: The on-chip X-Peripherals are enabled and can be accessed.
Page 71 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Function ROMS1 Internal ROM Mapping ‘0’: External ROM area mapped to segment 0 (00’0000 … 00’7FFF ‘1’: External ROM area mapped to segment 1 (01’0000 … 01’7FFF Note: ROMS1 = ‘0’ is recommended.
Page 72 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 0000 ILVL(3..0) USR0 Function Negative Result Set, when the result of an ALU operation is negative. Carry Flag Set, when the result of an ALU operation produces a carry bit.
Page 73 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller • N-Flag: For most of the ALU operations, the N-flag is set to ‘1’ if the most significant bit of the result contains a ‘1’, otherwise it is cleared. In the case of integer operations the N-flag can be interpreted as the sign bit of the result (negative: N = ‘1’, positive:...
Page 74 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller V-flag, the C-flag allows the evaluation of the rounding error with a finer resolution (see Table 4-3). For Boolean bit operations with only one operand the V-flag is always cleared. For Boolean bit operations with two operands the V-flag represents the logical ORing of the two specified bits.
Page 75 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller case of a task scheduler that switches between independent tasks), the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered.
Page 76 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 0000 SEGNR(7..0) Function SEGNR Segment Number (7 … 0) Specifies the code segment, from where the current instruction is to be fetched. SEGNR is ignored when segmentation is disabled.
Page 77: Figure 4-14 Addressing Via The Code Segment Pointer
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller CSP Register IP Register Code Segment FF’FFFF H FE’0000 H 01’0000 H 24/20/18-Bit Physical Code Address 00’0000 H MCA02265 Figure 4-14 Addressing via the Code Segment Pointer Note: When segmentation is disabled, the IP value is used directly as the 16-bit address.
Page 78 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller DPP2 Reset Value: 0002 DPP2PN DPP3 Reset Value: 0003 DPP3PN Function DPPxPN Data Page Number of DPPx Specifies the data page selected via DPPx. Only the least significant two bits of DPPx are significant, when segmentation is disabled.
Page 79: Figure 4-15 Addressing Via The Data Page Pointers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Note: Due to the internal instruction pipeline, a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the updating of the DPP register by the instruction.
Page 80: Figure 4-16 Register Bank Selection Via Register Cp
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Note: It is the user's responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location. If this condition is not met, unexpected results may occur.
Page 81: Figure 4-17 Implicit Cp Use By Short Gpr Addressing Modes
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Short 4-Bit GPR Addresses (mnemonic: Rw or Rb) specify an address relative to the memory location specified by the contents of the CP register, i.e. the base of the current register bank.
Page 82 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller (usually bigger) can be realized via software. This mechanism is supported by the STKOV and STKUN registers (see respective descriptions below). The SP register can be updated via any instruction, which is capable of modifying an SFR.
Page 83 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller stack may have been overwritten by the status information stacked upon the stack overflow trap service. • Automatic system stack flushing allows the use of the system stack as a “Stack Cache”...
Page 84 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller SUB instructions or by PUSH or POP operations (explicit or implicit, i.e. CALL or RET instructions). This control mechanism is not triggered, i.e. no stack trap is generated, when • the stack pointer SP is directly updated via MOV instructions •...
Page 85 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 0000 Function Specifies the low order 16 bits of the 32-bit multiply and divide register Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to ‘1’. The MDRIU flag is cleared whenever the MDL register is read via software.
Page 86 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller registers (to be able to restart the interrupted operation later), and then it must be cleared to prepare it for the new calculation. After the completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored.
Page 87 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller IDCHIP CHIPID(7..0) CHIPREVNU(7..0) Function CHIPREVNU Device Revision Code (7 … 0) Identifies the device step where the first release is marked ‘01 ’. CHIPID Device Identification (7 … 0) Identifies the device name.
Page 88 Interrupt and Trap Function...
Page 89: Interrupt And Trap Functions
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Interrupt and Trap Functions The C166 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources either by the CPU itself or external, i.e.
Page 90: Interrupt System Structure
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Interrupt System Structure M2 provides up to 33 separate interrupt nodes that may be assigned to 16 priority levels. Each node is associated with an interrupt input line in the Interrupt System Interface of the CPU.
Page 91 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Table 5-1 Interrupt Allocation Table Source of Interrupt or PEC Interrupt Address of Interrupt Trap Service Request Control Control Vector Number Register Register Location External Interrupt 0 EX0IC 00’FF88 00’0060...
Page 92: Hardware Traps
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Table 5-1 Interrupt Allocation Table (cont’d) Source of Interrupt or PEC Interrupt Address of Interrupt Trap Service Request Control Control Vector Number Register Register Location ADC Wake Up ADWIC 00’F178...
Page 93 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Table 5-2 Exception Condition Trap Trap Vector Trap Trap Flag Vector Location Number Priority Reset Functions: Hardware Reset – RESET 00’0000 Software Reset RESET 00’0000 Watchdog Timer RESET 00’0000...
Page 94 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Interrupt System Register Description Interrupt processing is controlled globally by the PSW register through a general interrupt enable bit (IEN) and the CPU priority field (ILVL). Additionally the different interrupt sources are controlled individually by their specific interrupt control registers (…...
Page 95 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions xxIC Reset Value: - - 00 xxIR xxIE ILVL GLVL Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. Highest group priority Lowest group priority...
Page 96: Figure 5-1 Priority Levels And Pec Channels
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Note: All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities. Otherwise an incorrect interrupt vector will be generated.
Page 97 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions The table below shows a few examples of each action executed with each particular programming of an interrupt control register. Priority Level Type of Service COUNT  00 ILVL...
Page 98 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Reset Value: 0000 ILVL USR0 Function N, C, V, Z, E, CPU status flags (Described in Chapter 4.6) MULIP, Define the current status of the CPU (ALU, multiplication unit).
Page 99 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions accepted by the CPU. However requests that have already entered the pipeline at that time will be processed. When IEN is set to ‘1’, all interrupt sources, which have been individually enabled by the interrupt enable bits in their associated control registers, are globally enabled.
Page 100: Operation Of The Pec Channels
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Operation of the PEC Channels M2’s Peripheral Event Controller (PEC) provides 8 PEC service channels, which move a single byte or word between two locations in the entire memory space. Packet transfers are provided with channels 0 and 1.
Page 101 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Function INC(1 … 0) Increment Control (Modification of SRCPx or DSTPx) 0 0: Pointers are not modified. 0 1: Increment DSTPx by 1 or 2. 1 0: Increment SRCPx by 1 or 2.
Page 102 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Previous Modified IR after PEC Action of PEC Channel COUNT COUNT service and Comments ‘0’ Move a Byte / Word Continuous transfer mode, i.e. COUNT is not modified … 02 …...
Page 103 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions When a data block is completely transferred a channel link interrupt is generated and the PEC service request processing is automatically switched to the “other” PEC channel of the channel-pair. Thus, PEC service requests addressed to a linked PEC channel are either handled by linked PEC channel A or by linked PEC channel B.
Page 104 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions link interrupt condition of linked PEC channels (A and B channels) which requires support from the CPU. The following channel link interrupt conditions requesting CPU service are possible: • In single transfer mode a COUNT value change from 01...
Page 105: Figure 5-2 Mapping Of Pec Offset Pointers Into The Internal Ram
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions DSTP7 00’FCFE DSTP3 00’FCEE SRCP7 00’FCFC SRCP3 00’FCEC DSTP6 00’FCFA DSTP2 00’FCEA SRCP6 00’FCF8 SRCP2 00’FCE8 DSTP5 00’FCF6 DSTP1 00’FCE6 SRCP5 00’FCF4 SRCP1 00’FCE4 DSTP4 00’FCF2 DSTP0 00’FCE2 SRCP4 00’FCF0...
Page 106: Prioritization Of Interrupt And Pec Service Requests
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Table 5-4 PEC Segment Number Register Addresses Register Address Reg. Space Register Address Reg. Space PECSN0 FED0 / 68 PECSN4 FED8 / 6C PECSN1 FED2 / 69 PECSN5 FEDA...
Page 107 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Classes with up to 4 members can be established by using the same interrupt priority (ILVL) and assigning a dedicated group level (GLVL) to each member. This functionality is built-in and handled automatically by the interrupt controller.
Page 108: Saving The Status During Interrupt Service
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions 5.2.2 Saving the Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. The CPU status (PSW) is saved along with the location, where the execution of the interrupted task is resumed after returning from the service routine.
Page 109: Interrupt Response Times
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions When the interrupt service routine is left (RETI is executed), the status information is popped from the system stack in reverse order, taking into account the value of bit SGTDIS.
Page 110 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions All instructions in the pipeline, including instruction N (during which the interrupt request flag is set), are completed before entering the service routine. The actual execution time for these instructions (e.g. wait-states) therefore influences the interrupt response time.
Page 111: Pec Response Times
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions and N require external operand read accesses, instructions N-3 through N write back external operands, and the interrupt vector also points to an external location. In this case the interrupt response time is the time needed to perform 9 word bus accesses, because instruction I1 cannot be fetched via the external bus until all write, fetch and read requests from preceding instructions in the pipeline are terminated.
Page 112: Figure 5-5 Pipeline Diagram For Pec Response Time
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N + 1 N + 2 N + 2 DECODE N - 1 N + 1 EXECUTE N - 2...
Page 113: Fast Interrupts
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions • If instruction N reads the PSW and instruction N-1 effects the condition flags, the PEC response time may additionally be extended by 2 state times. The worst case PEC response time during internal code memory program execution adds to 9 state times (18 TCL).
Page 114: Trap Functions
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions The 8 lines can be programmed individually to this fast interrupt mode, where the trigger transition (rising, falling or both) can also be selected. The External Interrupt Control register EXICON controls this feature for all 8 signals.
Page 115 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Trap Functions Traps interrupt the current execution similar to standard interrupts. However, trap functions offer the possibility to bypass the interrupt system’s prioritization process in cases where immediate system reaction is required. Trap functions are not maskable and always have priority over interrupt requests on any priority level.
Page 116 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions 15), disabling all interrupts. The CSP is set to code segment zero, if segmentation is enabled. A trap service routine must be terminated with the RETI instruction. The nine hardware trap functions of M2 are divided into two classes: Class A traps are •...
Page 117 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Function UNDOPC Undefined Opcode Flag The currently decoded instruction has no valid M2 opcode. DEBUG Debug Trap Flag A debug event programmed to trigger a Debug Trap has been detected by the OCDS.
Page 118: System Reset
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions After returning from the NMI service routine, the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap. Debug Trap The OCDS may be programmed to trigger a Debug Trap when a debug event (match of data/address comparison, execution of DEBUG instruction, event on brk_in_n input) rises.
Page 119 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions add instruction, the pushed IP value represents the instruction address following the post add-instruction command. Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid M2 opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine.
Page 120: External Interrupt Source Control
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions 5.3.1 External Interrupt Source Control Fast external interrupts may also have interrupt sources selected from other peripherals. This function is very advantageous in Slow Down or in Sleep mode if, for example, the A/D converter input shall be used to wakeup the system.
Page 121 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions EXISEL Reset Value: 0000 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS Function EXIxSS External Interrupt x Source Selection Field (x = 7 … 0) 0 0: Input from default pin 0 1: Input from “alternate source”...
Page 122 System Control & Configuration...
Page 123 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration System Control & Configuration M2 has extended features for system level control and configuration. Most of these features are now handled by a new block inside the M2 which is the System Control Unit (SCU).
Page 124 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration System Reset The internal system reset function provides the initialization of the M2 into a defined default state and is invoked either by asserting a hardware reset signal on pin RSTIN (Hardware Reset Input), upon the execution of the SRST instruction (Software Reset) or by an overflow of the watchdog timer.
Page 125: Behavior Of I/Os During Reset
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration • Long Hardware Reset A long hardware reset requires an RSTIN active time longer than the duration of the internal reset sequence. The duration of the internal reset sequence is 2056 TCL.
Page 126: The Internal Ram After Reset
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration few exceptions to this rule provide a first pre-initialization, which is either fixed or controlled by input pins. DPP1: 0001 (points to data page 1) DPP2: 0002 (points to data page 2)
Page 127: System Start-Up Configuration
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration System Start-up Configuration Although most of the programmable features of the M2 are either selected during the initialization routine or repeatedly during program execution, there are some features that must be selected earlier, because they are used for the first access of the program execution.
Page 128 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration serial interface ASC0. The M2 will remain in bootstrap loader mode until a hardware reset with P4.0 high or a software reset. Default: The M2 starts fetching code from location 00’0000 , the bootstrap loader is off.
Page 129: Register Write Protection
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Register Write Protection The System Control Unit (SCU) provides two different protection types of configuration registers: • Unprotected Registers • Protectable Registers The unprotected registers allow the reading and writing (if not read-only) of register values without any restrictions.
Page 130 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration The new password is defined with command 3 and stored in the according 8-bit field in the SCUSLS register. The SCUSLC register is defined as follows SCUSLC Reset Value: 0000...
Page 131 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration SCUSLS Reset Value: 0000 STATE PASSWORD Function PASSWORD Current Password Current Security Level ‘00’: Unprotected Write Mode ‘01’: Low Protected Mode ‘10’: Reserved ‘11’: Write Protected Mode STATE Current State ‘000’: State 0 = Wait for Command 0.
Page 132 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration The following state diagram shows the state machine for security level switching and for unlock command execution in low protected mode: Command 3 or any other SCU Register Write Access...
Page 133: Power Reduction Modes
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Power Reduction Modes Three power reduction modes with different levels of power reduction, which may be entered under software control, have been implemented in M2: Idle Mode: The CPU is stopped, while the peripherals including watchdog timer continue their operation at low clock frequency.
Page 134 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration interrupt requests can be used. Power down mode can only be terminated with hardware reset. To prevent unintentional entry into Idle mode, the IDLE instruction has been implemented as a protected 32-bit instruction.
Page 135 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Denied CPU Interrupt Request Accepted IDLE Instruction Active Idle Mode Mode Denied PEC Request Executed PEC Request UED11132 Figure 6-2 Transitions between Idle Mode and Active Mode Any interrupt request, whose individual Interrupt Enable flag was set before Idle mode was entered, will terminate Idle mode regardless of the current CPU priority.
Page 136 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Status of Output Pins during Idle and Power Down Mode During Idle mode the CPU is stopped, while all peripherals continue their operation in the same way previously described. Therefore all ports pins, which are configured as general purpose output pins, output the last data value which was written to their port output latches.
Page 137: Dedicated Pins
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Dedicated Pins M2 has different dedicated Pins than other controllers of C16X family. The following dedicated pins are not available: ALE, READY, EA, NMI. The following table explains M2 specific dedicated pins.
Page 138 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Signals MEMCLK, CLKEN are used to provide a clock and an enable signal for an external SDRAM. During reset an internal pull-down ensures an inactive (low) level on these outputs.
Page 139: Xbus Configuration
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration XBUS Configuration Although the XBUS is not visible at the chip boundary, some registers have to be set to guarantee correct operation. The user has to program the XBUS-registers in the...
Page 140: Watchdog Timer
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Watchdog Timer The watchdog timer is a 16-bit up counter which can be clocked with the CPU clock ), either divided by 2 or divided by 128. This 16-bit timer is realized as two concatenated 8-bit timers (see Figure 6-3).
Page 141 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration To prevent the watchdog timer from overflowing, it must be serviced periodically by the user software. The watchdog timer is serviced with the instruction SRVWDT, which is a protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog time WDT register with the preset value in bit field WDTREL, which is the high byte of the WDTCON register.
Page 142 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration WDTCON Reset Value: 00XX WDTREL(7 .. 0) Function WDTIN Watchdog Timer Input Frequency Selection Input frequency is Input frequency is /128 WDTR Watchdog Timer Reset Indication Flag Cleared by a hardware reset or by the SRVWDT instruction.
Page 143 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Reset Source Indication The reset indication flags in register WDTCON provide information on the source of the last reset. As M2 starts executing from location 00’0000 after any possible reset event,...
Page 144: Bootstrap Loader
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Bootstrap Loader The bootstrap loader of M2 works in the same way as implemented in other C16x derivatives. It provides a mechanism to load the start-up program, which is executed after reset, via a serial interface (ASC).
Page 145 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Register BUSCON0: according to start-up config. Register S0BG: according to ‘00’ byte P3.10/TXD0: ‘1’ DP3.10: ‘1’ Other than after a normal reset the watchdog timer is disabled, therefore the bootstrap loading sequence is not time limited.
Page 146: Identification Registers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Identification Registers A set of 8 identification registers are provided to offer information on the chip as manufacturer, chip type and its memory (EEPROM, OTP, DRAM or Flash memory) properties, and information on the CSCU (type of module, redesign state).
Page 147 MANUF Manufacturer This is the JEDEC normalized manufacturer code. :Infineon Technologies : SGS-Thomson DEPT Department Indicates the department within Micronas and Infineon Technologies. : HL MC : HL CAD Macrocells : HL IT IDCHIP Reset Value: XXXX CHIPID Chip Revision Number...
Page 148 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Function Size Size of On-chip Program Memory The size of the implemented program memory in terms of 4 K blocks, i.e. Memory-size = <Size> ⌠ 4 KByte. Type Type of On-chip Program Memory Identifies the memory type on this silicon.
Page 149: Cpu Identification
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Function Redesign Index This device is the original “Revision”. else: This device has experienced minor changes that are not reflected to the customer by the “Revision” bit field. Redundancy Activation This device is as it was manufactured.
Page 150: Parallel Ports
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration 6.10 Parallel Ports M2 provides up to 30 input/outputs, 6 output and 6 input multiple purpose ports. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers.
Page 151 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Reset Value: 0000 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 Function P2.y Port data register P2 bit y. Reset Value: 0000 DP2. DP2. DP2. DP2. DP2. DP2. DP2.
Page 152 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Port 3 If this 15-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP3. All port lines can be switched into push/pull or open drain mode via the open drain control register ODP3.
Page 153 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Function ODP3.y Port 3 Open Drain control register bit y ODP3.y = 0: Port line P3.y output driver in push/pull mode. ODP3.y = 1: Port line P3.y output driver in open drain mode.
Page 154 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration P4L (during reset) Reset Value: XXXX P4L.5 P4L.4 P4L.3 P4L.2 P4L.1 P4L.0 Function P4L.0 BSLENA (Boot Strap Load Enable) P4L.0 = 1: Boot strap loader enabled P4L.0 = 0: Boot strap loader disabled P4L.1...
Page 155 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration The number of segment address lines is selected via P4 during reset. The selected value can be read from bit field SALSEL and CSENA of register RP0H e.g. in order to check the configuration during run time.
Page 156 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Port 5 Pin Alternate Function P5.0 ANA0Analog Input 0 (Wake Up Function) P5.1 ANA1Analog Input 1 P5.2 ANA2Analog Input 2 P5.3 ANA3 Analog Input 3 P5.14 T4EUDTimer 4 External Up/Down Input P5.15...
Page 157 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Reset Value: 0000 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0 Function DP6.y Port direction register DP6 bit y. DP6.y = 0: Port line P6.y is an input (high-impedance). DP6.y = 1: Port line P6.y is an output.
Page 158 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration ALTSEL0P6 Reset Value: 0000 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 Function SELP6.y Alternate Function Control Bit SELP6.y = 0: General Purpose Port Functionality enabled for Line P6.y. SELP6.y = 1: Alternate Function enabled for Line P6.y.
Page 159 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration 6 - 40 Micronas...
Page 160 Peripherals...
Page 161 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Peripherals All of the peripherals described in the following paragraphs are clocked with the same clock as the CPU ( ). Depending on the mode (normal or Idle), this frequency is hw_clk 33.33 MHz or 3 MHz.
Page 162: Peripherals
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals General Purpose Timer Unit The General Purpose Timer Unit (GPT) represents very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2.
Page 163: Figure 7-1 Structure Of Timer Block 1 Core Timer T3
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals as capture or reload registers for the core timer. Concatenation of T3 with other timers is provided through line T3OTL. The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2, T3, or T4, which are located in the non-bitaddressable SFR space.
Page 164 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals In gated timer mode, the timer will only run if T3R is set and the gate is active (high or low, as programmed). Note: When bit T2RC/T4RC in timer control register T2CON/T4CON is set, T3R will also control (start and stop) auxiliary timer T2/T4.
Page 165 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals In addition, T3OTL can be used in conjunction with the timer over/underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4. For this purpose, the state of T3OTL does not have to be available at any port pin, because an internal connection is provided for this option.
Page 166: Figure 7-2 Block Diagram Of Core Timer T3 In Timer Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals BPS1 Interrupt Core Timer Tx hw_clk Request Down TxUD EXOR TxEUD x = 3 TxUDE UEB11196 Figure 7-2 Block Diagram of Core Timer T3 in Timer Mode Timer 3 in Gated Timer Mode The gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to ‘010...
Page 167: Figure 7-4 Block Diagram Of Core Timer T3 In Counter Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals If T3M = ‘010 ’, the timer is enabled when T3IN shows a low level. A high level at this line stops the timer. If T3M = ‘011 ’, line T3IN must have a high level in order to enable the timer.
Page 168: Figure 7-5 Block Diagram Of Core Timer T3 In Incremental Interface Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals For counter operation, a port pin associated to line T3IN must be configured as input. The maximum input frequency which is allowed in counter mode is /8 (BPS1 = ‘01’). hw_clk To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized, its level should be held high or low for at least 4 cycles (BPS1 = ‘01’)
Page 169: Figure 7-6 Interfacing The Encoder To The Microcontroller
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals generated each time a count action for timer T3 occurs. Count direction, changes in the count direction and count requests are monitored through the status bits T3RDIR, T3CHDIR and T3EDGE in register T3CON. T3 is modified automatically according to the speed and the direction of the incremental encoder.
Page 170: Figure 7-7 Evaluation Of The Incremental Encoder Signals
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals The maximum input frequency which is allowed in incremental interface mode is hw_clk 8 (BPS = 01). To ensure that a transition of any input signal is correctly recognized, its level should be held high or low for at least 4 cycles (BPS = 01) before it changes.
Page 171: Figure 7-8 Evaluation Of The Incremental Encoder Signals
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Forward Jitter Backward Jitter Forward T3IN T3EUD Contents of T3 Down Note: This example shows the timer behavior assuming that T3 counts upon any transition on input T3IN, i.e. T3I = ’001 ’.
Page 172: Figure 7-9 Block Diagram Of An Auxiliary Timer In Counter Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode, their operation is the same as described for the core timer T3. The descriptions, figures and tables apply accordingly with two exceptions: •...
Page 173: Timer Concatenation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Table 7-6 Auxiliary Timer (Counter Mode) Input Edge Selection T2I/T4I Triggering Edge for Counter Increment/Decrement X 0 0 None. Counter Tx is disabled 0 0 1 Positive transition (rising edge) on TxIN...
Page 174: Figure 7-10 Concatenation Of Core Timer T3 And An Auxiliary Timer
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals BPS1 TyI TyOUT Core Timer Ty TyOTL hw_clk TyOE Up/Down Interrupt Request Edge Select Interrupt Auxiliary Timer Tx TxIR Request x = 2, 4 y = 3 UES11201 Note: Line ‘*’ is only affected by over/underflows of T3, but NOT by software modifications of T3OTL.
Page 175: Figure 7-11 Gpt1 Auxiliary Timer In Reload Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Source/Edge x = 2, 4 Select Reload Register Tx Interrupt TxIN Request Input Interrupt Core Timer T3 Clock Request Up/Down T3OUT T3OTL T3OE UES11202 Note: Line ‘*’ is only affected by over/underflows of T3, but NOT by software modifications of T3OTL.
Page 176: Figure 7-12 Gpt1 Timer Reload Configuration For Pwm Generation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Figure 7-12 shows an example of the generation of a PWM signal using the alternate reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative transitions).
Page 177: Figure 7-13 Auxiliary Timer Of Timer Block 1 In Capture Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to ‘101 ’. In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer’s external input line TxIN.
Page 178: Functional Description Of Timer Block 2
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.1.2 Functional Description of Timer Block 2 Timer block 2 includes the two timers T5 (referred to as the auxiliary timer) and T6 (referred to as the core timer), and the 16-bit capture/reload register CAPREL.
Page 179: Core Timer T6
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.1.2.1 Core Timer T6 The operation of the core timer T6 is controlled by its bit-addressable control register T6CON. Timer 6 Run Bit The timer can be started or stopped by software through bit T6R (Timer T6 Run Bit).
Page 180: Auxiliary Timer T5
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals BPS2 T6OFL Interrupt Core Timer T6 hw_clk Request Down T6OTL T6UD x = 6 UEB11206 Figure 7-15 Block Diagram of Core Timer T6 in Timer Mode 7.1.2.2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer mode using the same options for the timer frequencies and the count signal as the core timer T6.
Page 181: Timer Concatenation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.1.2.3 Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer. Depending on which transition of T6OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33- bit timer/counter.
Page 182: Figure 7-17 Timer Block 2 Register Caprel In Capture Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals T3EUD or both inputs T3IN and T3EUD. The active edge is controlled by bit field CI in register T5CON. The maximum input frequency for the capture trigger signal at CAPIN is hw_clk (BPS2 = ‘01’).
Page 183: Figure 7-18 Timer Block 2 Register Caprel In Reload Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Timer Block 2 Capture/Reload Register CAPREL in Reload Mode This 16-bit register can be used as a reload register for the core timer T6. This mode is selected by setting bit T6SR = ‘1’ in register T6CON. The operation causing a reload in this mode is an overflow or underflow of the core timer T6.
Page 184: Figure 7-19 Timer Block 2 Register Caprel In Capture-And-Reload Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Up/Down Input Interrupt Auxiliary Timer T5 Clock Request Edge Select T5CLR CAPIN T5CC T3IN/ T3EUD T5SC Interrupt Request CAPREL Register T6CLR T6SR Input Interrupt Core Timer T6 Clock Request T6OFL Up/Down UEB11210...
Page 185: Gpt Registers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals bit T6OTL will be toggled. This signal has 8 times more transitions than the signal which is applied to line CAPIN. A certain deviation of the output frequency is generated by the fact that timer T5 will count actual time units (e.g.
Page 186 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals T3CON Timer 3 Control Register BPS1 Field Bits Type Description [2:0] Timer 3 Input Parameter Selection Timer mode see Table 7-9 for encoding Gated Timer see Table 7-9 for encoding Counter mode see Table 7-10 for encoding...
Page 187 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Description T3OE Overflow/Underflow Output Enable T3 overflow/underflow can not be externally monitored T3 overflow/underflow may be externally monitored via T3OUT T3OTL [10] Timer 3 Output Toggle Latch Toggles on each overflow/underflow of T3. Can be set or reset by software.
Page 188 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Table 7-9 Timer 3 Input Parameter Selection for Timer Mode and Gated Mode Prescaler for Prescaler for Prescaler for Prescaler for hw_clk hw_clk hw_clk hw_clk (BPS1 = 00) (BPS1 = 01) (BPS1 = 10)
Page 189 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals T2CON T4CON Timer 2/4 Control Register RDIR Field Bits Type Description [2:0] Timer x Input Parameter Selection Timer mode see Table 7-12 for encoding Gated Timer see Table 7-12 for encoding Counter mode see Table 7-13 for encoding...
Page 190 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Description TxRC Timer x Remote Control Timer/Counter x is controlled by its own run bit Timer/Counter x is controlled by the run bit of core timer 3 TxIRDIS [12]...
Page 191 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Table 7-12 Timer x Input Parameter Selection for Timer Mode and Gated Mode Prescaler for Prescaler for Prescaler for Prescaler for hw_clk hw_clk hw_clk hw_clk (BPS1 = 00) (BPS1 = 01) (BPS1 = 10)
Page 192 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals T6CON Timer 6 Control Register BPS2 Field Bits Type Description [2:0] Timer 6 Input Parameter Selection Timer mode see Table 7-15 for encoding [5:3] Timer 6 Mode Control (Basic Operating Mode) Timer Mode Reserved.
Page 193 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Table 7-15 Timer 6 Input Parameter Selection for Timer Mode and Gated Mode Prescaler for Prescaler for Prescaler for Prescaler for (BPS2 = 00) (BPS2 = 01) (BPS2 = 10) (BPS2 = 11)
Page 194 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals T5CON Timer 5 Control Register Field Bits Type Description [2:0] Timer 5 Input Parameter Selection Timer mode see Table 7-17 for encoding Counter mode see Table 7-18 for encoding [5:3] Timer 5 Mode Control (Basic Operating Mode)
Page 195 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Description [13:12] rw Register CAPREL Capture Trigger Selection (depending in bit CT3) Capture disabled Positive transition (rising edge) on CAPIN or any transition on T3IN Negative transition (falling edge) on CAPIN or...
Page 196: Interrupts
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Table 7-18 Timer 5 Input Parameter Selection for Counter Mode Triggering Edge for Counter Update None. Counter T5 is disabled Reserved. Do not use this combination. Reserved. Do not use this combination.
Page 197 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Table 7-19 Peripheral Name Interrupt Sources (cont’d) Interrupt Interrupt Node Description Rotation T2IC Interrupt is requested on a change of the count Direction direction in the Incremental Interface Mode Change Timer 2 (T2I = 110).
Page 198: Real-Time Clock
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Real-time Clock 7.2.1 General Description The Real Time Clock (RTC) module of M2 is basically an independent timer chain and counts time ticks. The base frequency of the RTC can be programmed via a reload counter.
Page 199: Figure 7-21 Rtc Block Diagram
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals RTC_INT 3 MHz RTC_T14INT RTCR Interrupt Subnode RTC0INT RTC1INT RTC2INT RTC3INT RTCRELL0 RTCRELL1 RTCREL2 RTCREL3 T14REL(16 Bit) 10 Bit 6 Bit 6 Bit 10 Bit T14_IN 10 Bit 6 Bit 6 Bit...
Page 200: Register Description
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals RTCRELH = FA04 , counter T14 generates one overflow per millisecond, RTCL0 one per second, RTCL1 one per minute, RTCH2 one per hour and RTCH3 one per day. 48-bit Timer Operation The concatenation of the 16-bit reload timer T14 and the 32-bit RTC timer can be regarded as a 48-bit timer which counts with the RTC count input frequency (3 MHz).
Page 201 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Note: Bit RTCR is set on hardware reset. Reset Value: 0000 TIMER14(15 ..0 ) Function TIMER14 16 Bit Timer Register (15 … 0) Timer T14 generates the input clock for the RTC register and the periodic interrupt.
Page 202 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals RTCH Reset Value: 0000 RTCH3(9.. 0) RTCH2(5 .. 0) Function RTCH3 (9 … 0) High Word of 32 Bit Capture Register. RTCH2 (5 … 0) RTCRELL Reset Value: 0000 RTCRELL0(9 .. 0) RTCRELL1(5 ..
Page 203 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals RTC Interrupt Subnode Control RTCISNC Reset Value: 0000 3 IR 2 IR 1 IR 1 IE 0 IR Function T14IR T14 Overflow Interrupt Request Flag ‘0’: No request pending. ‘1’: This source has raised an interrupt request.
Page 204 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals ISNC Reset Value: 0000 INT2 INT2 Function RTCINTIR RTC Interrupt Request Flag ‘0’: No request pending. ‘1’: RTC has raised an interrupt request. RTCINTIE RTC Interrupt Enable Control Bit ‘0’: Interrupt request is disabled.
Page 205: Asynchronous/Synchronous Serial Interface
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Asynchronous/Synchronous Serial Interface The Asynchronous/Synchronous Serial Interface ASC0 provides serial communication between M2 and other microcontrollers, microprocessors or external peripherals. It provides the following features: • Full duplex asynchronous operating modes – 8- or 9-bit data frames, LSB first –...
Page 206: Figure 7-22 Block Diagram Of The Asc0
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Asynchronous Mode Prescaler/ Baud Rate 33 MHz Fractional Divider Timer Autobaud Detection Serial Port Control Receive/Transmit IrDA Buffers and Coding IrDA Shift Registers Decoding Synchronous Mode ÷ Baud Rate Timer ÷ 3...
Page 207: Figure 7-23 Asc Register Overview
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Ports & Direction Control Data Registers Control Registers Interrupt Control Alternate Functions ODP3 S0BG S0CON S0TIC S0TBUF S0FDV S0RIC S0RBUF S0PMW S0EIC ABCON S0TBIC RxD0/P3.11 ABSTAT TxD0/P3.10 ODP3 Port 3 Open Drain Control Register...
Page 208: Asynchronous Operation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Data reception is enabled by the receiver enable bit S0REN. After reception of a character has been completed, the received data and, if provided by the selected operating mode, the received parity bit can be read from the (read-only) receive buffer register S0RBUF.
Page 209: Figure 7-24 Asynchronous Mode Of Serial Channel Asc0
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 13-Bit Reload Register S0FDE Fractional Divider 33 MHz ÷ 13-Bit Baud Rate Timer ÷ ÷ S0BRS S0PE S0STR S0FE S0OE S0RIR S0REN Shift Clock Receive Int. Request S0TIR S0FEN Transmit Int. Request...
Page 210: Asynchronous Data Frames
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.3.1.1 Asynchronous Data Frames 8-Bit Data Frames 8-bit data frames either consist of 8 data bits D7 … D0 (S0M = ‘001 ’), or of 7 data bits D6 … D0 plus an automatically generated parity bit (S0M = ‘011 ’).
Page 211: Figure 7-26 Asynchronous 9-Bit Frames
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 11-/12-Bit UART Frame 9 Data Bits (1st) (2nd) Start Bit 9 Stop Stop SOM = 100 : Bit 9 = Data Bit D8 SOM = 101 : Bit 9 = Wake-up Bit...
Page 212: Asynchronous Transmission
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals UART Frame Start Stop 8 Data Bits IR Frame Start Stop 8 Data Bits Bit Time 1/2 BitTime Pulse Width = 3/16 Bit Time (or variable length) UED11146 Figure 7-27 IrDA Frame Encoding/Decoding 7.3.1.2...
Page 213: Asynchronous Reception
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.3.1.3 Asynchronous Reception Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin RXD0, provided that bits S0R and S0REN are set. The receive data input pin RXD0 is sampled at 16 times the rate of the selected baud rate.
Page 214: Figure 7-28 Fixed Irda Pulse Generation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals S0PWM Start Timer IrDA Pulse 33 MHz 8-Bit Timer UED11147 Figure 7-28 Fixed IrDA Pulse Generation The IrDA pulse width can be calculated according to the formulas given in the following table.
Page 215: Synchronous Operation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Depending on the asynchronous operating mode (controlled by bitfield CON_M), the ASC output signal or the RXD input signal in echo mode (controlled by bit ABCON_ABEM) is switched to the TXD output by an inverter (controlled by bit ABCON_TXINV).
Page 216: Synchronous Transmission
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 13-Bit Reload Register 33 MHz ÷ 13-Bit Baud Rate Timer ÷ ÷ S0BRS S0M = 000 S0OE S0RIR Shift Clock Receive Int. Request S0REN S0TIR Transmit Int. Request S0OEN Serial Port Control...
Page 217: Synchronous Reception
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals data, while transmission of the previous one is still going on. The data bits are transmitted synchronous to the shift clock. After the bit time for the 8th data bit, both pins TXD0 and RXD0 will go high, the transmit interrupt request line S0TIR is activated, and serial data transmission stops.
Page 218: Baud Rate Generation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Receive/Transmit Timing Shift Latch Shift Latch Shift Shift Clock Transmit Data Data Bit n Data Bit n+1 Data Bit n+2 Receive Data Valid Data n Valid Data n+1 Valid Data n+2 Continuous Transmit Timing...
Page 219: Baud Rates In Asynchronous Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Register S0BG is the dual-function Baud Rate Generator/Reload register. Reading S0BG returns the content of the timer (bits 15 … 13 return zero), while writing to S0BG always updates the reload register (bits 15 … 13 are insignificant).
Page 220: Figure 7-32 Asc0 Baud Rate Generator Circuitry In Asynchronous Modes
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 13-Bit Reload Register S0FDE Baud Rate Fractional ÷ Clock Divider Sample 33 MHz ÷ 13-Bit Baud Rate Timer Clock ÷ S0FDE S0BRS Selected Divider S0BRS ÷ 2 ÷ 3 Fractional Divider UES11151...
Page 221 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals below lists various commonly used baud rates, together with the required reload values and the deviation errors compared to the intended baud rate. Baud Rate S0BRS = ‘0’, = 33.33 MHz S0BRS = ‘1’, = 33.33 MHz...
Page 222: Baud Rates In Synchronous Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.3.3.2 Baud Rates in Synchronous Mode For synchronous operation, the baud rate generator provides a clock with 4 times the rate of the established baud rate (see Figure 7-33). 13-Bit Reload Register ÷...
Page 223: Serial Frames For Autobaud Detection
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Figure 7-34 shows how the autobaud detection unit of the ASC is integrated into its asynchronous mode configuration. The RXD data line is an input of the autobaud detection unit. The clock , which is generated by the fractional divider, is used by the autobaud detection unit as a time base.
Page 224: Figure 7-35 Two-Byte Serial Frames With Ascii 'At'
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Note: Some other two-byte combinations will also be defined. 7 Bit, Even Parity ’a’ = 61 ’t’ = 74 Start Parity Stop Start Parity Stop 7 Bit, Odd Parity ’a’ = 61 ’t’...
Page 225: Figure 7-36 Two-Byte Serial Frames With Ascii 'At'
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7 Bit, Even Parity ’A’ = 41 ’T’ = 54 Start Parity Stop Start Parity Stop 7 Bit, Odd Parity ’A’ = 41 ’T’ = 54 Start Parity Stop Start Parity Stop 8 Bit, No Parity ’A’...
Page 226: Baud Rate Selection And Calculation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.3.4.2 Baud Rate Selection and Calculation The autobaud detection requires some calculations concerning the programming of the baud rate generator and the baud rates to be detected. Two steps must be considered: •...
Page 227 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Table 7-20 Autobaud Detection using Standard Baud Rates ( = 11.0592 MHz) Baud Rate Detectable Standard Divide Factor d BG is Loaded after Numbering Baud Rate Detection with Value 230.400 kBaud = 002 115.200 kBaud...
Page 228: Overwriting Registers On Successful Autobaud Detection
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Non-Standard Baud Rates Due to the relationship between Br0 to Br8 in Table 7-20 concerning the divide factor d other baud rates than the standard ones can also be selected. For example, if a baud rate of 50 kBaud has to be detected, Br2 is e.g.
Page 229: Asc Hardware Error Detection Capabilities
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Table 7-23 Autobaud Detection Overwrite Values for the CON Register Detected Parameters CON_M CON_ODD BG_BR_VALUE Operating Mode 7 bit, even parity 0 1 1 – 7 bit, odd parity 0 1 1...
Page 230: Interrupts
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.3.6 Interrupts Six interrupt sources are provided for serial channel ASC0. Line S0TIC indicates a transmit interrupt, S0TBIC indicates a transmit buffer interrupt, S0RIC indicates a receive interrupt and S0EIC indicates an error interrupt of the serial channel. The autobaud detection unit provides two additional interrupts, the ABSTIR start of autobaud operation interrupt and the ABDETIR autobaud detected interrupt.
Page 231: Register Description
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Asynchronous Mode S0TIR S0TIR S0TIR S0TBIR S0TBIR S0TBIR Idle Idle S0RIR S0RIR S0RIR Synchronous Mode S0TIR S0TIR S0TIR S0TBIR S0TBIR S0TBIR Idle Idle S0RIR S0RIR S0RIR UED11156 Figure 7-37 ASC0 Interrupt Generation As shown in Figure 7-37, S0TBIR is an early trigger for the reload routine, while S0TIR indicates the completed transmission.
Page 232 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description Mode Selection 0 0 0 8-bit data sync. operation 0 0 1 8-bit data async. operation 0 1 0 IrDA mode, 8-bit data async. operation 0 1 1 7-bit data + parity async.
Page 233 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description – Parity Error Flag Set by hardware on a parity error (PEN = ‘1’). Must be reset by software. – Framing Error Flag Set by hardware on a framing error (FEN = ‘1’).
Page 234 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals The autobaud control register ABCON is used to control the autobaud detection operation. It contains its general enable bit, the interrupt enable control bits, and data path control bits S0ABCON Autobaud Control Register...
Page 235 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description FCDETEN First Character of Two-Byte Frame Detected Enable Autobaud detection interrupt ABDETIR becomes active after the two-byte frame recognition Autobaud detection interrupt ABDETIR becomes active after detection of the first and second byte of the two-byte frame.
Page 236 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals S0ABSTAT Autobaud Status Register Field Bits Type Value Description FCSDET First Character with Small Letter Detected no small ‘a’ character detected small ‘a’ character detected Bit is cleared by hardware when ABCON_ABEN is set or if FCCDET or SCSDET or SCCDET is set.
Page 237 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description SCCDET Second Character with Capital Letter Detected no capital ‘T’ character detected capital ‘T’ character detected Bit is cleared by hardware when ABCON_ABEN is set or if FCSDET or FCCDET or SCSDET is set.
Page 238 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals S0BG Baud Rate Timer/Reload Register BR_VALUE Field Bits Type Value Description BR_VALUE 12-0 Baud Rate Timer/Reload Register Value Reading BG returns the 13-bit content of the baud rate timer (bits 15 … 13 return 0);...
Page 239 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals S0PMW IrDA Pulse Mode/Width Register PW_VALUE Field Bits Type Value Description PW_VALUE IrDA Pulse Width Value PW_VALUE is the 8-bit value n, which defines the variable pulse width of an IrDA pulse. Depending on the ASC_P input...
Page 240 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals S0TBUF Transmitter Buffer Register TD_VALUE Field Bits Type Value Description TD_VALUE Transmit Data Register Value TBUF contains the data to be transmitted in asynchronous and synchronous operating mode of the ASC_P. Data transmission is...
Page 241: High Speed Synchronous Serial Interface
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals High Speed Synchronous Serial Interface • Master and slave mode operation – Full-duplex or half-duplex operation • Flexible data format – Programmable number of data bits: 2 to 16 bit – Programmable shift direction: LSB or MSB shift first –...
Page 242: Figure 7-38 Sfrs And Port Pins Associated With The Ssc0
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Ports & Direction Control Data Registers Control Registers Interrupt Control Alternate Functions ODP3 SSCBR SSCCON SSCTIC SSCTB SSCRIC SSCRB SSCEIC SLCK/P3.13 MTSR/P3.9 MRST/P3.8 ODP3 Port 3 Open Drain Control Register Port 3 Data Register...
Page 243: Figure 7-39 Synchronous Serial Channel Ssc0 Block Diagram
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Baud Rate Clock 33 MHz SCLKx Generator Control Shift Clock SSC0RIR Receive Int. Request SSC0TIR SSC Control Block Transmit Int. Request SSC0CON SSC0EIR Error Int. Request Status Control MTSRx Control MRSTx 16-Bit Shift Register...
Page 244 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals transferred, the contents of the shift register are moved to the Receive Buffer SSCRB and a receive interrupt request line (SSCRIR) will be activated. If no further transfer is to take place (SSCTB is empty), SSC0BSY will be cleared at the same time. Software should not modify SSC0BSY, as this flag is hardware controlled.
Page 245: Full-Duplex Operation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals SSC0 SSC0 Shift Clock SCLK Pins MTSR0/MRST0 Transmit Data First Bit Last Bit Latch Data Shift Data UED11159 Figure 7-40 Serial Clock Phase and Polarity Options 7.4.1 Full-Duplex Operation The different devices are connected by three lines. The definition of these lines is always determined by the master: the line connected to the master’s data output pin MTSR is...
Page 246: Figure 7-41 Ssc0 Full Duplex Configuration
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Device #1 Master Device #2 Slave Shift Register Shift Register MTSR MTSR Transmit MRST MRST Receive Clock Clock Clock Device #3 Slave Shift Register MTSR MRST Clock UED11160 Figure 7-41 SSC0 Full Duplex Configuration The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration.
Page 247 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. After performing all necessary initializations of the SSC0, the serial interfaces can be enabled.
Page 248: Half Duplex Operation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals The same mechanism as for selecting a slave for transmission (separate select lines or special commands) may also be used to move the role of the master to another device in the network. In this case the previous master and the future master (previous slave) will have to toggle their operating mode (SSC0MS) and the direction of their port pins.
Page 249: Continuous Transfers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Device #1 Master Transmit Device #2 Slave Shift Register Shift Register MTSR MTSR MRST MRST Clock Clock Clock Common Transmit/ Receive Device #3 Slave Line Shift Register MTSR MRST Clock UED11161 Figure 7-42 SSC Half Duplex Configuration 7.4.3...
Page 250: Port Control
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.4.4 Port Control The SSC0 uses three pins to communicate with the external world. Pin SCLK serves as the clock line, while pins MRST (Master Receive/Slave Transmit) and MTSR (Master Transmit/Slave Receive) serve as the serial data input/output lines.
Page 251: Error Detection Mechanisms
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals The formulas below calculate either the resulting baud rate for a given reload value, or the required reload value for a given baud rate: 33 MHz 33 MHz Baud rate <SSCBR> = (...
Page 252: Figure 7-44 Ssc0 Error Interrupt Control
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Bit in Register SSCCON SSC0TEN & Transmit SSC0TE Error SSC0REN & Receive SSC0RE Error < Error Interrupt SSCEIR SSC0PEN & Phase SSC0PE Error SSC0BEN & Baud Rate SSC0BE Error UES11163 Figure 7-44 SSC0 Error Interrupt Control...
Page 253 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Note: If this error condition occurs and bit SSC0REN = ‘1’, an automatic reset of the SSC0 will be performed in case of this error. This is done to re-initialize the SSC0, if too few or too many clock pulses have been detected.
Page 254: Register Description
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.4.7 Register Description The operating mode of the serial channel SSC0 is controlled by its control register SSCCON. This register contains control bits for mode and error check selection, and status flags for error identification. Depending on bit SSC0EN, either control functions or status flags and master/slave control is enabled.
Page 255 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Function SSC0PEN SSC0 Phase Error Enable Bit Ignore phase errors Check phase errors SSC0BEN SSC0 Baud Rate Error Enable Bit Ignore baud rate errors Check baud rate errors SSC0AREN SSC0 Automatic Reset Enable Bit...
Page 256 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals SSC0EN = 1: Operating Mode SSCCON Reset Value: 0000 SSC0 SSC0 SSC0 SSC0 SSC0 SSC0 SSC0 SSC0BC Function SSC0BC SSC0 Bit Count Field Shift counter is updated with every shifted bit. Do not write to!!!
Page 257 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals SSCBR Reset Value: 0000 SSC0RL(15 ..0) Function SSC0RL Baud Rate Timer/Reload Register Value (15 … 0) Reading SSCBR returns the 16-bit content of the baud rate timer. Writing SSC0BR loads the baud rate timer reload register.
Page 258 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals SSCRB Reset Value: 0000 SSC0RD(15..0) Function SSC0RD Receive Data Register Value (7 … 0) SSCRB contains the received data bits. Unselected bits of SSC0RB will be not valid and should be ignored...
Page 259: Operational Overview
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals C-Bus Interface The on-chip I C Bus module connects the M2 to other external controllers and/or peripherals via the two-line serial I C interface. The I C Bus module provides communication at data rates of up to 400 Kbit/s and features 7-bit as well as 10-bit addressing.
Page 260 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Stop Transfer: A rising edge on SDA ( ) while SCL is high indicates a stop condition. This stop condition terminates a data transfer. An arbitrary number of bytes may be transferred between a start condition and a stop condition.
Page 261 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals This mechanism allows a number of configurations of the physical I C Bus interface: Physical Channels Can be selected, so the I C module can use electrically separated channels or increase the addressing range by using more data lines.
Page 262: Figure 7-46 Physical Bus Configuration Example
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Ι C-Channel 0 Ι Ι SDA 6000 C-Bus Node C-Bus Node Ι C-Channel 1 UES11165 Figure 7-46 Physical Bus Configuration Example Output Pin Configuration The pin drivers that are assigned to the I C channel(s) provide open drain outputs (i.e.
Page 263: Functional Overview
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.5.3 Functional Overview Operation in Master Mode If the on-chip I C module controls the I C bus (i.e. bus master), master mode must be selected via bit field MOD in register ICCON. The physical channel is configured by a control word written to register ICCFG, defining the active interface pins and the used baud rate.
Page 264: Registers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals line active at a time when operating in slave mode. The address by which the slave module can be selected is written to register ICADR. The I C module is selected by another master when it receives (after a start condition), either its own device address (stored in ICADR) or the general call address (00 ).
Page 265 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7.5.4 Registers All available module registers are summarized in the overview table below. Register Register Description Address Reset Value Name ICCFG C Configuration Register 00’E810 0000 ICCON C Control Register 00’E812 0000...
Page 266 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals C Control Register ICCON Reset Value: 0000 Field Bits Type Value Description Address Mode 7-bit addressing using ICA7 … 1. 10-bit addressing using ICA9 … 0. Repeated Start Condition No operation. Generate a repeated start condition in (multi) master mode.
Page 267 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description ACKDIS Acknowledge Pulse Disable An acknowledge pulse is generated for each received frame. No acknowledge pulse is generated. Note: ACKDIS is automatically cleared by a stop condition.
Page 268 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description [10:9] rw Length of the Transmit Buffer 1 Byte 2 Bytes 3 Bytes 4 Bytes If RMEN is set, RM is mirrored here. WMEN Write Mirror Enable...
Page 269 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals C Status Register ICST Reset Value: 0000 Field Bits Type Value Description – Address Bit ADR is set after a start condition in slave mode until the address has been received (1 byte in 7-bit address mode, 2 bytes in 10- bit address mode).
Page 270 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description Bus Busy The I C bus is idle, i.e. a stop condition has occurred. The I C bus is active, i.e. a start condition has occurred. Note: Bit BB is always ‘0’ while the I module is disabled.
Page 271 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description IRQP C Interrupt Request Bit for Protocol Events No interrupt request pending. A protocol event interrupt request is pending. IRQP is set when bit SLA or bit AL is set ( ), and must be cleared via software.
Page 272 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Field Bits Type Value Description 10..8 rw Counter of Transmitted Bytes Since Last Data Interrupt. If a multi byte transmission could not be finished because of a missing acknowledge, the number of correctly transferred bytes can be read from CO.
Page 273 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals C Address Register ICADR Reset Value: 0000 PREDIV ICA7..1 Field Bits Type Value Description ICA0 – Node Address Bit 0 in 10-Bit Mode (See ICCON bit M10) Access is only possible in 10-bit mode.
Page 274 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals implemented. It uses two different modes and an additional pre divider. Low baud rates may be configured at high precision in mode 0 which is compatible with older versions. High baud rates may be configured precisely in mode 1.
Page 275 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals C Receive/Transmit Buffer ICRTBH/L Reset Value: 0000 ICRTB3 ICRTB2 ICRTB1 ICRTB0 Field Bits Type Value Description 1) 2) ICRTBx 15..0 rwh – Receive/Transmit Buffer x = 3 … 0 The buffers contain the data to be sent/ received.
Page 276 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Interrupts Table 7-25 Interrupt Sources Interrupt SRC Register Description Data CTIC Interrupt is requested after the acknowledge bit of the last byte has been received or transmitted. Data Error CTIC Interrupt is requested if a multi byte...
Page 277 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Synchronization In Mastermode, the SCL line is controlled by the I C Module. Sent and received data is only valid if SCL is high. With SCL going down, all modules are starting to count down their low period.
Page 278 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals bit field CO must be read in case the buffer size (defined in CI) is greater than one byte, to decide which bytes in the receive buffer were received in the last transmission cycle.
Page 279: Analog Digital Converter
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals Analog Digital Converter M2 includes a four channel 8-bit ADC for control purposes. By means of these four input signals the controller is able to supervise the status of several analog signals and to take action if necessary.
Page 280: Register Description
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals of generating an interrupt signal (ADWIC) as soon as the CADC (ANA0) input voltage falls below a predefined level. Two different levels are available. The first one corresponds to (fullscale-4 LSB) the second one to (fullscale-16 LSB). The actual level can be selected by a control bit (ADWULE).
Page 281 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals ADDAT2 Reset Value: 0000 ADRES3 ADRES2 Function ADRES A/D Conversion Result (8-bit) of Channel 0 … 3 (ANA 0 … 3) (7 … 0) For each A/D channel two successive 7-bit samples (@33.3 MHZ) are processed, averaged and scaled to 0 - 254.
Page 282 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Peripherals 7 - 124 Micronas...
Page 283 Clock System...
Page 284 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Clock System Clock System 8 - 3 Micronas...
Page 285: Clock System
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Clock System General Function The on-chip clock generator provides M2 with its basic clock signals. Its oscillator can either run with an external crystal and appropriate oscillator circuitry (refer to “Application Diagram”) or it can be driven by an external digital clock signal. For applications with low accuracy requirements (RTC is not used) the external oscillator circuit can also be a ceramic resonator.
Page 286 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Clock System One, the 33 MHz system clock ( ) supplies the processor, all processor related peripherals, the sync timing logic, the A/D converters and the slicer. The second clock system (100/66 MHZ) ( ) is used to clock the external bus interface, the display generator, the CLUTs and the input part of the display FIFO.
Page 287: Register Description
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Clock System Register Description SYSCON2 Reset Value: 0000 Function CLKCON Bus Clock Frequency = 66 MHz = 100 MHz Note: Register SYSCON2 cannot be changed after execution of the EINIT instruction. Reset Value: 0148 PF(10..0)
Page 288 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Clock System 8 - 8 Micronas...
Page 289 Sync System...
Page 290 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System Sync System 9 - 3 Micronas...
Page 291: Sync System
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System General Description The display sync system is completely independent of the acquisition sync system (CVBS timing) and can either work as a sync master or as a sync slave system. Any mention of “H/V-Syncs”...
Page 292: Figure 9-1 M2'S Display Timing
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System V-Sync Vertical Blacklevel Clamping Delay (SDV) Screen Background Area H-Sync Delay (SDH) Pixel Layer 1 Variable Height Pixel Layer 2 Variable Width H_clmp_b (BHCR) H_clmp_e (EHCR) H_period (HPR) H-Sync UET11168 Figure 9-1 M2’s Display Timing...
Page 293: Sync Interrupts
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System Pixel Layer Area Pixels of this area are freely programmable according to the specifications of the display generator. The information is stored in the frame buffer in the external memory, that means the bigger that area is defined, the more bus performance is needed for SRU.
Page 294: Register Description
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System Register Description Reset Value: 0000 COR- VSU(3..0) BLAN MAST Function MAST Master / Slave Mode This bit defines the configuration of the sync system (master or slave mode) and also the direction (input/output) of the V, H pins.
Page 295 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System Function H-Pin Polarity This bit defines the polarity of the H pin. (Master and slave mode). Normal polarity (active high). Negative polarity. CORP COR-Pin Polarity This bit defines the polarity of the COR pin. (Master and slave mode).
Page 296 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System Reset Value: 0271 VL(9..0) Function VLR (9 … 0) Amount of Vertical Lines in a Frame. (Master mode only). M2 generates vertical sync impulses in sync master mode. If, for example, a normal PAL timing should be generated, set the register to ‘625d’...
Page 297 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System Reset Value: 0020 SDV(9..0) Function SDV (9 … 0) Vertical Sync Delay. (Master and slave mode). This register defines the delay (in lines) from the vertical sync to the first line of pixel layer 1 on the screen.
Page 298 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System Reset Value: 0A00 EHCR(7..0) EHCR(7..0) Function BHCR Beginning of Horizontal Clamp Phase. (Master and slave mode). (7 … 0) This register defines the delay of the horizontal clamp phase from the positive edge of the horizontal sync impulse (normal polarity is assumed).
Page 299: And Pixel Layer Area
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System Clamp Phase Area Screen Background Area Pixel Layer Area Video H Period - Frame n H Pulse UED11169 Figure 9-2 Priority of Clamp Phase, Screen Background and Pixel Layer Area BVCR...
Page 300 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Sync System EVCR Reset Value: 000A EVCR1 EVCR0 EVCR(9..0) Function EVCR End of Vertical Clamp Phase. (Master and slave mode). (9 … 0) This register defines the end of the vertical clamp phase from the positive edge of the vertical sync impulse (at normal polarity) in line count.
Page 301 Display Generator...
Page 302 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Display Generator 10 - 3 Micronas...
Page 303 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.1 General Description M2’s display concept is based on frame buffer technology, which means that for each pixel displayed on a screen appropriate information is stored in the memory of the so called frame buffer.
Page 304 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.2 Screen Alignments Two HW-layers are supported: layer 1 and layer 2. Layer 2 can be positioned relative to layer 1 (also in negative direction). If layer 2 exceeds the dimensions of layer 2 these exceeding parts are not visible on the screen.
Page 305: Display Generator
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator To adapt M2 to a wide range of displays in the market the sync-processing can be flexibly configured. Vertical Blacklevel Clamping Screen Background Area Layer 2 Area Layer 1 Variable Non-Visible Part...
Page 306: Layer Concept
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.3 Layer Concept M2 supports two HW-layers. Frame buffers of layer 1 and layer 2 can be placed at any word aligned position in external memory. Two different layer modes can be chosen: •...
Page 307 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.3.1 Overlapped Layers In overlapped layer mode the pixel information of both layers (layer 1, layer 2) is read in parallel to the RAM. This means that for each pixel the individual decision can be made which pixel source (layer 1, layer 2, screen background or video) has the highest priority.
Page 308: Overlapped Layers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-1 Behavior of M2’s Outputs in Overlapped Layer Mode Layer 1 Layer 2 Screen BLANK Background Pins Tube SBTL n.a. n.a. Layer 1 Layer 1 n.a. n.a. Meshed Layer 1...
Page 309 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-1 Behavior of M2’s Outputs in Overlapped Layer Mode (cont’d) Layer 1 Layer 2 Screen BLANK Background Pins Tube SBTL Back- Video ground Back- Contrast ground red. Video n.a. = not available X = don’t care...
Page 310: Embedded Layers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Layer 2 Layer 1 Background Color Video UEA11173 Figure 10-4 Priority of Layers in Embedded Layer Mode Depending on the transparency bits of both layers, the following signals are switched to the RGB, COR and BLANK (normal polarity assumed) outputs of M2.
Page 311 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-2 Behavior of M2’s Outputs in Embedded Layer Mode Layer 1 Layer 2 Screen BLANK Back- Pins Tube ground SBTL n.a. n.a. Layer 1 Layer 1 n.a. n.a. Meshed Layer 1...
Page 312 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-3 Behavior of M2’s Outputs in Background Area Screen BLANK RGB Pins RGB Tube Background STR1 STR0 RGB values RGB values defined defined in SAR in SAR Meshed RGB values...
Page 313: Input And Output Formats
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.4 Input and Output Formats The transfer of one memory area to another is executed by the graphic accelerator (GA). Transfer means reading data from a source memory area in a given input format, modifying the data and writing it in a defined output format to the destination memory area.
Page 314: Input Formats
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.4.1 Input Formats The following figures describe how bitmaps for different input bit map formats are stored in the source memory area . The 16-bit format is described in Figure 10-12.
Page 315: Output Formats
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 Byte Address n+1 Byte Address n Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel...
Page 316: Figure 10-10 2-Bit Pixel Format For Use In Frame Buffer
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator The different formats of pixels stored in a frame buffer which are used by the SRU are described in the following paragraphs: Frame Buffer in 2-bit Pixel Format Using this format, the frame buffer contains colour vectors. These 2-bitplane colour vectors will be converted into 4:4:4:2 format (R:G:B: transparency value) by addressing vector 252 …...
Page 317: Figure 10-12 16-Bit Pixel Format (4:4:4:2/Ttx) For Use In Frame Buffer
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator M TR(1..0) Pixel(12..0) 1 Hz Flash 2 Hz Flash, Phase 1 16-Bit TTX (2..0) FlashC(4..0) Pixel(4..0) Format 2 Hz Flash, Phase 2 2 Hz Flash, Phase 3 Transparency Level 1 Transparency Level 2 16-Bit 4:4:4:2 Red(3..0)
Page 318: Figure 10-13 Internally Generated Flash Signals In Different Flash Phases
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Slow Rate Flash. Normal Flash Fast Rate Flash. Phase 1. Normal Flash Fast Rate Flash. Phase 2. Normal Flash Fast Rate Flash. Phase 3. Normal Flash UED11182 Figure 10-13 Internally Generated Flash Signals in Different Flash Phases 5-bit colour look up vectors are converted into a 12-bit RGB value and a 2-bit transparency level by CLUT2 during display.
Page 319: Initialization Of Memory Transfers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.5 Initialization of Memory Transfers Transferring an input format of the source area to an output format in the destination area is supported by different transfer modes. For this, a pixel modification unit and CLUT1 of the GA is used.
Page 320 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-5 Supported Transfer Modes TMOD Input Output Transparency Modification (4 … 0) Format Format Available 00000 1-bit 16-bit OUT(15) = ‘0’ bitmap (TTX) OUT(14 … 13) = FLA(1 … 0) OUT(12 …...
Page 321 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-5 Supported Transfer Modes (cont’d) TMOD Input Output Transparency Modification (4 … 0) Format Format Available 01001 4-bit 16-bit OUT(15) = ‘1’ bitmap (4:4:4:2) OUT(14 … 13) = CLUT1(‘0000000’ &...
Page 322: Transfer Areas
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-5 Supported Transfer Modes (cont’d) TMOD Input Output Transparency Modification (4 … 0) Format Format Available 10100 8-bit 8-bit data No OUT(7 … 0) = IN(7 … 0) data Others...
Page 323 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator As described before, there are seven different formats on the input side of the transfer: • 1-bit bitmap • 2-bit bitmap • 4-bit bitmap • 8-bit bitmap • 8-bit data (used for direct data transfer) •...
Page 324: Figure 10-16 Use Of Register Settings To Specify Source Area
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator MEMORY S_ADDR WIDTH_IN (TSR) S_OFFSET (TOR) Source Area UED11185 Figure 10-16 Use of Register Settings to Specify Source Area Destination Area There are additional settings necessary to define the destination area. The table below...
Page 325 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator As described before, there are five different formats on the output side of the transfer: (Also please refer to Chapter 10.4.2) • 8-bit format CLUT2 vector • 16-bit format (4:4:4:2) RGB •...
Page 326 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Meaning of Double Width and Double Height during Transfer The destination area can be stretched horizontally and vertically by using GA instruction TAR. If double width (TDW) is set to ‘1’, the graphic accelerator writes each pixel twice horizontally to the destination area.
Page 327: Italic Mode
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Figure 10-17 gives a graphical overview of how to specify the different areas. Frame Buffer FB_ADDR WIDTH_L1(2) (FSR) D_ADDR WIDTH_OUT (TDR) D_OFFSET (TOR) C_ADDR Destination Area HEIGHT_OUT (TDR) HEIGHT_L1(2) (FSR) Clipping Area...
Page 328: Figure 10-19 Result For A Italic Transferred Memory Area In Frame Buffer
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator If this transfer is executed with the same register settings but in italic mode instead of non italic mode, the subsequent destination area is used inside the frame buffer: D_ADDR D_OFFSET...
Page 329: Register Description
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.6 Register Description 10.6.1 Special Function Registers The display generator is controlled by 3 special function registers and a list of accelerator instructions. Two of the registers define the position and the length of the instruction list, and one register is used for general control of the DG.
Page 330 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator DGCON Reset Value: 0000 Function EADG Enables access from DG to SDRAM. All requests from DG (SRU and GA) to the memory are disabled. The DG has normal access to the memory.
Page 331 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator The register PXDEL controls an individual delay of 0 … 2 clock cycles of the SRU outputs. Each output (R, G, B, Italic, blank, cor) is contolled by 2 bits in the PXDEL register.
Page 332: Description Of Graphic Accelerator Instructions
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7 Description of Graphic Accelerator Instructions GAIs are 32-bit instructions which are used as an interface from ← C to DG. They are written sequentially to the SDRAM by the controller in form of an instruction list.
Page 333: Figure 10-22 Gai Instruction Format
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator In the following GAI description, ‘–’ means that these bits are reserved for future use and have to be set to ‘0’. The meaning of an instruction is not given by the physical location (address) of the instruction but by its opcode which is represented by bits 31 …...
Page 334: Screen Attributes (Sar)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Transfer Parameters These instructions are immediately executed by the GA. • CUR (opcode = 0000) - set clipping coordinates • CBR (opcode = 0001) - set clipping coordinates • SDR (opcode = 0010) - set source descriptor for data transfer •...
Page 335 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Function Double Width Display Normal width Double width. The contents of the screen are stretched in horizontal direction. The SRU repeats the same pixel information twice in horizontal direction. Note: DDW = ‘1’ the frame buffer width (WIDTH_L1(L2) has to be divided by two to get the same area displayed on the screen.
Page 336 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-6 Display Modes DMODE Layer Formats Layer Mode (3 … 0) Layer 1 Layer 2 0000 16-bit (4:4:4:2 or TTX) – Layer 2 switched off 0001 8-bit – Layer 2 switched off...
Page 337: Startaddress Of Layer 1 (Fbr)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.2 Startaddress of Layer 1 (FBR) The start address of frame buffer 1 in the memory must be set by the controller. FB_ADDR(23..16) FB_ADDR(15..0) Function FB_ADDR Startaddress of frame buffer 1 (23 …...
Page 338: Startaddress Of Layer 2 (Dbr)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.4 Startaddress of Layer 2 (DBR) The start address of frame buffer 2 in the memory must be set by the controller. DB_ADDR(23..16) DB_ADDR(15..0) Function DB_ADDR Startaddress of Frame Buffer 2 (23 …...
Page 339: Display Coordinates Of Layer 2 (Dcr)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.6 Display Coordinates of Layer 2 (DCR) This instruction is used to place layer 2 in layer 1. By these coordinates the left top corner of layer 2 is placed in relation to the top left corner of layer 1. In this sense the coordinate ULY = 0/ULX = 0 is identical to the top left corner of layer 1.
Page 340: Contents Of Clut (Clr)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.7 Contents of CLUT (CLR) CLR instruction allows the contents of the CLUT1 and CLUT2 to be set. CLUT_ADDR(8..0) CLUT_CONTENT(15..0) Function CLUT_ CLUT address ADDR Bits 7 … 0 are CLUT vectors of either CLUT1 or CLUT2. Bit 8 selects the (8 …...
Page 341 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator C_OFFSET(3..0) CLIPPING_ADDR(23..16) CLIPPING_ADDR(15..0) Function C_OFFSET Clipping Offset (Bit3 … 0) (3 … 0) The MSBs of C_OFFSET are defined by instruction CBR CLIPPING Beginning of the clipping area _ADDR Bit 23 … 0 of a byte address.
Page 342: Source Descriptor For Data Transfer (Sdr)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.9 Source Descriptor for Data Transfer (SDR) This instruction defines the beginning of the memory area to be read and transferred. S_ADDR(23..16) S_ADDR(15..0) Function Must be set to ‘1’ if GA is to start memory transfer after executing this GA-instruction.
Page 343: Source Size Of Transferred Memory Area (Tsr)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.10 Source Size of Transferred Memory Area (TSR) This register contains different information depending on transfer mode. The size of transferred memory is described by width and height of the source of the transfer area.
Page 344: Destination Size Of Transferred Memory Area (Tdr)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.11 Destination Size of Transferred Memory Area (TDR) HEIGHT_OUT(9..0) WIDTH_OUT(10..0) Function Must be set to ‘1’ if GA is to start memory transfer after executing this GA-instruction. Otherwise this bit must be set to ‘0’.
Page 345: Offset Of Transferred Memory Area (Tor)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.12 Offset of Transferred Memory Area (TOR) This instruction defines the offset value for rectangle memory transfers. D_OFFSET(10..0) S_OFFSET(10..0) Function Must be set to ‘1’ if GA is to start memory transfer after executing this GA-instruction.
Page 346: Attributes Of Transfer (Tar)
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10.7.13 Attributes of Transfer (TAR) This instruction defines the transfer mode. CL(1..0) TMODE(4..0) FLA(1..0) Table 10-7 Function Must be set to ‘1’ if GA is to start memory transfer after executing this GA-instruction.
Page 347 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator Table 10-7 (cont’d) Function TMODE Transfer Mode (4 … 0) This mode is used to decide which transfer mode should be used. With this bit it is decided which input and which output format is used for transformation.
Page 348 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Display Generator 10 - 50 Micronas...
Page 349 D/A Converter...
Page 350 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 D/A Converter D/A Converter M2 uses a 3 ⌠ 6-bit voltage D/A converter to generate analog RGB output signals with a nominal amplitude of 0.7 V (also available: 0.5 V, 1.0 V and 1.2 V) peak to peak. Two different modes are available in order to allow the reduction of power consumption for applications which require a lower RGB bandwidth.
Page 351 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 D/A Converter 11.1 Register Description DACCON Reset Value: 0005 RGBGAIN (1..0) Function RGBGAIN Gain Adjustment of RGB Converter. (1 … 0) The user can change the output gain of the DAC. 0.5 V 0.7 V...
Page 352 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 D/A Converter 11 - 6 Micronas...
Page 353 Slicer and Acquisition...
Page 354 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Slicer and Acquisition 12 - 3 Micronas...
Page 355 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition 12.1 General Function M2 provides a full digital slicer including digital H- and V-sync separation and digital sync processing. The acquisition interface is capable to process on all known data services starting from line 6 to line 23 for TV (Teletext, VPS, CC, G+, WSS) as well as any full channel services.
Page 356 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition 12.2 Slicer Architecture The slicer is composed of five main blocks: • The full service slicer (Slicer 1) • The WSS only slicer (Slicer 2) • The H/V synchronization for full service slicer (Sync 1) •...
Page 357: Slicer And Acquisition
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Slicer 2 Sync 2 (WSS only Slicer) HS2_IR Sync Sep. H-PLL VS2_IR CVBS2 Data D-PLL Separation Timing Slicer 1 Sync 1 (Full Service Slicer) HS1_IR VS1_IR Sync Sep. H-PLL L23_IR...
Page 358: Distortion Processing
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition 12.2.1 Distortion Processing For the full service slicer the digital bit stream is applied to a circuitry which corrects transmission distortion. In order to apply the correct counter-measures, a signal evaluation is done in parallel.
Page 359: Data Separation
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition 12.2.2 Data Separation Parallel to the signal analyses and distortion compensation a filter is used to calculate the slicing level. The slicing level is the mean-value of the CRI. As the teletext is coded using the NRZ format, the slicing level can not be calculated outside the CRI and is therefore frozen after CRI.
Page 360: H/V-Synchronization
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition 12.3 H/V-Synchronization Slicer and acquisition interface need many signals synchronized to the incoming CVBS (e.g. line number, field or line start). Therefore a sync slicing level is calculated and the sync signal is sliced from the filtered digital CVBS signal.
Page 361: Fc-Check
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition 12.4 Acquisition Interface The acquisition interface manages the data transfer between both slicers and memory. First of all a byte synchronization is performed (FC-check). Following this, the data is paralleled and shifted into memory as 16 bit words. In the other direction parameters are loaded from memory to the slicer.
Page 362: Interrupts
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition FCWSS This FC is fixed to that of WSS. A special algorithm makes sure that the WSS-FC is detected even if the CVBS signal is coming from a video tape.
Page 363: Figure 12-2 Vbi Buffer: General Structure
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition register STRVBI) of the VBI buffer should only be changed if the acquisition is switched off. Byte 1 Byte 0 STRVBI ACQFP0 Field Parameters ACQFP1 Field Parameters Send to slicer...
Page 364: Register Description
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition 12.5 Register Description The acquisition interface has only two SFR Registers. The line and field parameters are stored in the RAM (RAM Registers). They have to be initialized by software before starting the acquisition.
Page 365 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Function VS1_IR VS interrupt. The vertical sync impulse can be used to have field synchronization for the software. (VS of slicer 1 is used). No request pending. This source has raised an interrupt request.
Page 366: Ram Registers
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Function CC_IR Channel Change Indicator The H-PLL has lost the synchronization. (Slicer 1 is used). No request pending. This source has raised an interrupt request. Note: Also refer to status bits STAB1 or VDOK1...
Page 367 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition FC3MASK(15..0) Function FC3MASK Mask for Framing code 3 (15 … 0) Bit 15:Mask for first received bit of FC. Bit 0: Mask for last received bit of FC. 12 - 16...
Page 368 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition ACQFP2 Reset Value: XXXX FC1(7..0) FULL Function Framing code 1 (7 … 0) Bit 7: First received bit of FC Bit 0: Last received bit of FC AGDON Automatic group delay compensation...
Page 369 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition ACQFP3 Reset Value: XXXX WSS2 WSS2 WSS2_DATA(83..80) _ACK Function WSS2OK No new WSS data from slicer 2 is available New WSS data from slicer 2 is available (written to memory by ACQ-interface)
Page 370 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition ACQFP5 Reset Value: XXXX WSS2_DATA(63..48) Function WSS2_ 16 bits of sliced data of slicer 2 DATA (written to memory by ACQ-interface). (63 … 48) Note: See also ACQFP3, ACQFP4, ACQFP6 to ACQFP8...
Page 371 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition ACQFP8 Reset Value: XXXX WSS2_DATA(15..0) Function WSS2_ 16 bits of sliced data of slicer 2 (WWS2_DATA(0) = last received bit) DATA (written to memory by ACQ-interface). (15 … 0) Note: See also ACQFP3 to ACQFP7...
Page 372 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Function NOISE Noise and co-channel detector of slicer 1 (1 … 0) No noise and no co-channel-distortion has been detected. (status bit) No noise but co-channel-distortion has been detected. Noise but no co-channel-distortion has been detected.
Page 373 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Line Parameters Note: Line parameters only work on slicer 1 and have no influence on slicer 2. ACQLP0 Reset Value: XXXX DINCR(15..0) Function DINCR Specifies the frequency of the D-PLL of slicer 1. This parameter is used (15 …...
Page 374 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Function ACCUON Accumulator on Improves slicing level calculation under noisy conditions. If noise has been detected during automatic mode or if the bit NOION has been set the internal slicing level calculation can be improved by setting this bit.
Page 375 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition ACQLP2 Reset Value: XXXX MLENGTH(2..0) FCSEL(1..0) ALENGTH CLKDIV(2..0) NORM(2..0) (1..0) Function FC1ER Error tolerance of FC1 check No error allowed One error allowed MLENGTH For noise suppression reasons a median filter has been introduced after (2 …...
Page 376 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Function CLKDIV The slicing level filter needs to find the DC value of the CVBS during CRI. In order to do this it should suppress at least the CRI frequency. As different services use different data frequencies the CRI frequency will be different as well.
Page 377 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition Function FCSEL There are three different framing codes which can be used for each field. The framing code used for the actual line is selected with FCSEL (corresponds to slicer 1).
Page 378 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition ACQLP4 Reset Value: XXXX FREA MSL(6..0) PERRP(5..0) TLDE FCOK Function FREATTL Frequency Depending Attenuation Measurement (Line indicator) High frequency-CVBS1-components (around 3.5 MHz) are strongly damped (6 to 9 dB) compared to lower frequency-CVBS1-components...
Page 379 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition ACQLP5 Reset Value: XXXX PERR(5..0) Function PERR Phase Error Watch Dog (5 … 0) (detection of test line CCIR331a or b) This is the exact phase error watch dog output for the current line. The value shows how often in a line the internal PLL found strong phase deviations between PLL and sliced data.
Page 380: Recommended Parameter Settings
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Slicer and Acquisition 12.5.2 Recommended Parameter Settings AGDON AFRON ANOON GDPON GDNON FREON PFILON LOWPON PLLTON ACCUON NOION FULL DINCR 54559 45041 39321 7864 7920 FC1ER MLENGTH ALENGTH CLKDIV NORM FCSEL don’t care don’t care...
Page 381 Register Overview...
Page 382 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Register Overview This section summarizes all SFR and ESFR registers, which are implemented in M2 and explains the description format which is used in the previous chapters to describe the functionality of the SFRs. Display generators and slicers are mainly programmed via RAM registers which are not mentioned in this chapter, due to their variable position in the RAM.
Page 383 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview 13.1 Register Description Format In the respective chapters the function and the layout of the SFRs is described in a specific format which provides a number of details about the described special function register.
Page 384 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview 13.2 CPU General Purpose Registers (GPRs) The GPRs form the register bank with which the CPU works. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks can only reside within the internal RAM.
Page 385: Register Overview
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Name Physical 8-Bit Description Reset Address Address Value (CP) + 0 CPU General Purpose (Byte) Register RL0 (CP) + 1 CPU General Purpose (Byte) Register RH0 (CP) + 2 CPU General Purpose (Byte) Register RL1...
Page 386: Registers Ordered By Context
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview 13.3 Registers Ordered by Context The following table lists all SFRs which are implemented in the M2 grouped by their context. Their actual address can be seen in the next chapter.
Page 387 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Table 13-1 (cont’d) Name Description Physical 8-Bit Reset Address Address Value RTCCON Control Register F1CC 0003 T14REL Prescaler Timer Reload F0D0 0000 Prescaler Timer T14 F0D2 0000 RTCL Count Register Low Word...
Page 388 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Table 13-1 (cont’d) Name Description Physical 8-Bit Reset Address Address Value General Purpose Timer Registers (GPT1/2) T2CON GPT1 Timer 2 Control Register FF40 0000 T3CON GPT1 Timer 3 Control Register FF42...
Page 389 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Table 13-1 (cont’d) Name Description Physical 8-Bit Reset Address Address Value EX7IC External Interrupt Control Register 7 FF96 0000 ADC1IC A/D Conversion Interrupt Control FF98 0000 (Channel 1 + 2) ADC2IC...
Page 390 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Table 13-1 (cont’d) Name Description Physical 8-Bit Reset Address Address Value PECC5 PEC Channel 5 Control Register FECA 0000 PECC6 PEC Channel 6 Control Register FECC 0000 PECC7 PEC Channel 7 Control Register...
Page 391 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Table 13-1 (cont’d) Name Description Physical 8-Bit Reset Address Address Value PXDEL Pixel Delay Register F198 0000 ACQISN Acquisition Interrupt Subnode Register F1A2 0000 GPRGCRL GAI Instruction Start Register (Low Word) F1A4...
Page 392 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Table 13-1 (cont’d) Name Description Physical 8-Bit Reset Address Address Value DCMP0L Hardware Trigger Equal Comparison F0E4 0000 Register 0 DCMP0H Extension of Register DCMP0L F0E6 0000 DCMP1L Hardware Trigger Equal Comparison...
Page 393 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Table 13-1 (cont’d) Name Description Physical 8-Bit Reset Address Address Value XADRS4 External Address Select Register 4 F01A 0000 XADRS5 External Address Select Register 5 F01C 0000 XADRS6 External Address Select Register 6...
Page 394 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview Table 13-1 (cont’d) Name Description Physical 8-Bit Reset Address Address Value EXICON External Interrupt Control F1C0 0000 OSCCON Oscillator Pad Control Register F1C4 0001 IDMANUF Manufacture ID F07E XXXX IDCHIP Chip ID...
Page 395: Registers Ordered By Address
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview 13.4 Registers Ordered by Address The following tables summarize the register symbols and their “short addresses”. The physical address can be calculated by multiplying the short address by 2 and adding that...
Page 396: Registers In Sfr Area
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview 13.4.1 Registers in SFR Area Address + 00 + 01 + 02 + 03 + 04 + 05 + 06 + 07 DPP0 DPP1 DPP2 DPP3 reserved STKOV STKUN ADDRSEL1 ADDRSEL2...
Page 397: Registers In Esfr Area
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview 13.4.2 Registers in ESFR Area Address + 00 + 01 + 02 + 03 + 04 + 05 + 06 + 07 CPUID XADRS1 XADRS2 XADRS3 XADRS4 XADRS5 XADRS6 XPERCON reserved...
Page 398 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Register Overview 13 - 20 Micronas...
Page 399 Elelctrical Characteristics...
Page 400 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics Electrical Characteristics 14 - 3 Micronas...
Page 401 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics 14.1 Absolute Maximum Ratings Note: The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Ambient Temperature Table 14-1 = 0 ...
Page 402: Electrical Characteristics
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics 14.2 Operating Range Table 14-2 Operating Range Parameter Symbol Limit Values Unit Test Condition min. max.  C Ambient temperature – Supply voltage 3.3 V – DD33 1-7 Supply voltage 2.5 V 2.25...
Page 403: Dc Characteristics
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics 14.3 DC Characteristics DC Characteristics Table 14-3 Parameter Symbol Limit Values Unit Test Condition min. max. Supply Currents Digital supply current for – all ports as inputs, 3.3 V 3.3 V domain...
Page 404 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics DC Characteristics Table 14-3 (cont’d) Parameter Symbol Limit Values Unit Test Condition min. max. Duty Cycle – – High time – – Pin capacitance (XTAL1) – – CVBS-Input: CVBS1A (ADC_DIFF = 0; differential CVBS Input) Pin capacitance –...
Page 405 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics DC Characteristics Table 14-3 (cont’d) Parameter Symbol Limit Values Unit Test Condition min. max. TXT data amplitude – DATA De-coupling Capacitors to – – – Dec_CPL at Pins CVBSi RGB-Outputs Load capacitance –...
Page 406 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics DC Characteristics Table 14-3 (cont’d) Parameter Symbol Limit Values Unit Test Condition min. max. Data Bits: D0 to D15 Output Rise Time – (10% - 90%) Output Fall Time – (10% - 90%) Load Capacitance –...
Page 407 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics DC Characteristics Table 14-3 (cont’d) Parameter Symbol Limit Values Unit Test Condition min. max. Output voltage for data – – insertion HSYNC Input Rise Time – (10% - 90%) Input Fall Time –...
Page 408 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics DC Characteristics Table 14-3 (cont’d) Parameter Symbol Limit Values Unit Test Condition min. max. ← s Horizontal Period – Depends on Register P2.x, P3.x, P5.x, P6.x Output Rise Time – (10% - 90%) Output Fall Time –...
Page 409: Timings
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics 14.4 Timings VSYNC OPWV OPWH HSYNC Line i Line i+1 Line i+2 UET11193 Figure 14-1 H/V - Sync-Timing (Sync-master mode) Equalizing Pulses Equalizing Pulses Field Sync Pulses Horizontal Pulses Horizontal Pulse...
Page 410: Package Outlines
SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics 14.5 Package Outlines P-MQFP-128-2 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm SMD = Surface Mounted Device...
Page 411 SDA 6000 PRELIMINARY DATA SHEET Version 2.1 Electrical Characteristics 14 - 14 Micronas...
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Micronas SDA 6000 User Manual

D/A Converter

Pin Descriptions

C16X Microcontroller

Interrupt and Trap Functions

Peripherals

Sync System

Display Generator

Slicer and Acquisition

Register Overview

Electrical Characteristics

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Summary of Contents for Micronas SDA 6000