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Infineon Technologies TriCore Compiler Manuals
Manuals and User Guides for Infineon Technologies TriCore Compiler. We have
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Infineon Technologies TriCore Compiler manual available for free PDF download: User Manual
Infineon Technologies TriCore Compiler User Manual (64 pages)
Brand:
Infineon Technologies
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
5
Preface
7
1 Optimization Strategies
8
Using 16-Bit Instructions
8
Register Allocation and Code Scheduling for Short Instructions
8
16-Bit Loads and Stores
10
Loads and Stores with Implicit Base and Implicit Destination
10
Other Implicit D15 Instructions
11
2.5 Address" Alternatives for Dyadic Instructions
11
Instructions with 8-Bit Constants
12
Compare Instructions
12
Compare and Jump
12
Using Complex Instructions
12
Auto-Adjust Addressing
13
Circular Addressing
14
Compare and Jump
14
Multiply-Add
14
Absolute Value
14
Min and Max
15
Count Leading (CL)
15
Conditional Instructions
16
Extending the Use of Conditional Instructions
17
Accumulating Compare Instructions
18
Using Bit Instructions
19
Template Matching for Extract
20
Template Matching for Insert
21
Bit-Logical Instructions
22
Call Related Optimizations
23
FCALL (Fast Call) Instruction
23
Tail Call Conversion
24
QSEED FPU (Floating Point Unit) Instruction
25
Miscellaneous Considerations
26
LOOP Instructions
26
Literals
26
Shift Instructions
27
Switch Statements
27
2 Implementation Information
30
Pipeline Model and Instruction Scheduling
30
First Approximation
30
Simple Pipeline Model for Tricore 1.2/1.3 and Tricore 2.0
31
Simple Scheduling Strategy
32
Latency Considerations
33
Floating Point Unit (FPU) Pipeline
33
Tricore 1.2/1.3 Regular Integer Versus MAC Pipelines
34
Tricore 1.2/1.3 Regular Integer Versus MAC Pipelines
35
Tricore 1.2/1.3 Load-To-Use Latencies
35
Tricore 1.2/1.3 Definition-To-Store Latencies
36
Tricore 2.0 Load-To-Use Latencies
37
Tricore 2.0 Definition-To-Use Latencies
37
Multi-Cycle Instructions
38
Scheduling Around CALL and RET
38
Block Ordering and Alignment
39
Tricore 1.2/1.3 & 2.0 Instruction Fetch Unit
39
Tricore 1.2/1.3 Branch Timings
39
Tricore 2.0 Branch Timings
40
Block Ordering for Tricore 1.2/1.3
40
Pipeline Balancing
42
3 Advanced Optimizations
44
SIMD Optimization - an Introduction
44
Data Dependence Analysis
45
FORALL Loops
46
Strip-Mining
47
Scalar Expansion & Loop Peeling
48
Loop Interchange
50
Loop Reversal
51
Loop Fusion and Loop Fission
51
Reductions
52
Miscellaneous Transformations
54
4 DSP Support
56
The Requirement of DSP-C Language
56
Data Types
56
Keywords
57
Other Topics
57
Appendix A Instruction Pairs for Packed Arithmetic
58
Appendix B Coding Examples
60
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