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iHome SDIO Card manual available for free PDF download: Specification Sheet
IHome SDIO Card Specification Sheet (73 pages)
SDI Technologies Memory Card Specification Sheet
Brand:
IHome
| Category:
Computer Hardware
| Size: 0.44 MB
Table of Contents
Revision History
2
Conventions Used in this Document
4
Table of Contents
5
1 General Description
10
SDIO Features
10
Primary Reference Document
10
Standard SDIO Functions
10
2 SDIO Signaling Definition
11
SDIO Card Types
11
SDIO Card Modes
11
SPI (Card Mandatory Support)
11
1-Bit SD Data Transfer Mode (Card Mandatory Support)
11
4-Bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for Low-Speed)
11
SDIO Host Modes
11
Signal Pins
12
Figure 2-1 Signal Connection to Two 4-Bit SDIO Cards
12
3 SDIO Card Initialization
13
Differences in I/O Card Initialization
13
Figure 3-1 SDIO Response to Non-I/O Aware Initialization
13
Figure 3-2 Card Initialization Flow in SD Mode (SDIO Aware Host)
16
Figure 3-3 Card Initialization Flow in SPI Mode (SDIO Aware Host)
18
The IO_SEND_OP_COND Command (CMD5)
19
Table 3-1 OCR Values for CMD5
19
Figure 3-4 IO_SEND_OP_COND Command (CMD5)
19
The IO_SEND_OP_COND Response (R4)
20
Figure 3-5 Response R4 in SD Mode
20
Figure 3-6 Response R4 in SPI Mode
20
Figure 3-7 Modified R1 Response
20
Special Initialization Considerations for Combo Cards
21
Re-Initialize both I/O and Memory
21
Using a Combo Card as SDIO Only or SD Memory Only after Combo Initialization
21
Acceptable Commands after Initialization
21
Recommendations for RCA after Reset
21
Figure 3-8 Re-Initialization Flow for I/O Controller
22
Figure 3-9 Re-Initialization Flow for Memory Controller
22
Enabling CRC in SPI Combo Card
23
4 Differences with SD Memory Specification
24
SDIO Command List
24
Unsupported SD Memory Commands
24
Modified R6 Response
25
Reset for SDIO
25
Bus Width
25
Table 4-1 Unsupported SD Memory Commands
25
Table 4-2 R6 Response to CMD3
25
Table 4-3 SDIO R6 Status Bits
25
Card Detect Resistor
26
Timings
26
Table 4-4 Combo Card 4-Bit Control
26
Table 4-5 Card Detect Resistor States
26
Table 4-6 Is Blanked
26
Data Transfer Block Sizes
27
Data Transfer Abort
27
Read Abort
27
Write Abort
27
Changes to SD Memory Fixed Registers
27
OCR Register
28
CID Register
28
CSD Register
28
RCA Register
28
DSR Register
28
SCR Register
28
SD Status
28
Card Status Register
28
Table 4-7 SDIO Status Register Structure
29
5 New I/O Read/Write Commands
30
IO_RW_DIRECT Command (CMD52)
30
Figure 5-1 IO_RW_DIRECT Command
30
IO_RW_DIRECT Response (R5)
31
CMD52 Response (SD Modes)
31
Figure 5-2 R5 IO_RW_DIRECT Response (SD Modes)
31
R5, IO_RW_DIRECT Response (SPI Mode)
32
Table 5-1 Flag Data for IO_RW_DIRECT SD Response
32
Figure 5-3 IO_RW_DIRECT Response in SPI Mode
32
IO_RW_EXTENDED Command (CMD53)
33
Figure 5-4 IO_RW_EXTENDED Command
33
Table 5-2 IO_RW_ EXTENDED Command Op Code Definition
33
CMD53 Data Transfer Format
34
Special Timing for CMD53 Multi-Block Read
34
Table 5-3 Byte Count Values
34
6 SDIO Card Internal Operation
35
Overview
35
Register Access Time
35
Interrupts
35
Suspend/Resume
36
Read Wait
36
CMD52 During Data Transfer
36
SDIO Fixed Internal Map
36
Common I/O Area (CIA)
37
Card Common Control Registers (CCCR)
37
Figure 6-1 SDIO Internal Map
37
Table 6-1 Card Common Control Registers (CCCR)
38
Table 6-2 CCCR Bit Definitions
43
Function Basic Registers (FBR)
44
Table 6-3 Function Basic Information Registers (FBR)
44
Table 6-4 FBR Bit and Field Definitions
45
Card Information Structure (CIS)
46
Multiple Function SDIO Cards
46
Setting Block Size with CMD53
46
Table 6-5 Card Information Structure (CIS) and Reserved Area of CIA
46
Bus State Diagram
47
Figure 6-2 State Diagram for Bus State Machine
47
7 Embedded I/O Code Storage Area (CSA)
48
CSA Access
48
CSA Data Format
48
8 SDIO Interrupts
49
Interrupt Timing
49
SPI and SD 1-Bit Mode Interrupts
49
SD 4-Bit Mode
49
Interrupt Period Definition
49
Interrupt Period at the Data Block Gap in 4-Bit SD Mode (Optional)
49
Inhibited Interrupts (Removed Section)
49
End of Interrupt Cycles
49
Terminated Data Transfer Interrupt Cycle
50
Interrupt Clear Timing
50
9 SDIO Suspend/Resume Operation
51
10 SDIO Read Wait Operation
52
11 Power Control
53
Power Control Overview
53
Power Control Support for SDIO Cards
53
Master Power Control
53
Power Selection
54
High-Power Tuples
54
Power Control Support for the SDIO Host
54
Version 1.10 Host
54
Table 11-1 Reference Tuples by Master Power Control and Power Select
54
Power Control Operation
55
12 High-Speed Mode
56
SDIO High-Speed Mode
56
Switching Bus Speed Mode in a Combo Card
56
13 SDIO Physical Properties
57
SDIO Form Factors
57
Full-Size SDIO
57
Minisdio
57
14 SDIO Power
57
SDIO Card Initialization Voltages
57
SDIO Power Consumption
57
15 Inrush Current Limiting
59
16 CIS Formats
60
CIS Reference Document
60
Basic Tuple Format and Tuple Chain Structure
60
Byte Order Within Tuples
60
Table 16-1 Basic Tuple Format
60
Tuple Version
61
SDIO Card Metaformat
61
Table 16-2 Tuples Supported by SDIO Cards
61
CISTPL_MANFID: Manufacturer Identification String Tuple
62
SDIO Specific Extensions
62
CISTPL_FUNCID: Function Identification Tuple
62
Table 16-3 CISTPL_MANFID: Manufacturer Identification Tuple
62
Table 16-4 CISTPL_FUNCID Tuple
62
CISTPL_FUNCE: Function Extension Tuple
63
CISTPL_FUNCE Tuple for Function 0 (Common)
63
Table 16-5 CISTPL_FUNCE Tuple General Structure
63
Table 16-6 TPLFID_FUNCTION Tuple for Function 0 (Common)
63
Table 16-7 TPLFID_FUNCTION Field Descriptions for Function 0 (Common)
63
CISTPL_FUNCE Tuple for Function 1-7
64
Table 16-8 TPLFID_FUNCTION Tuple for Function 1-7
64
Table 16-9 TPLFID_FUNCTION Field Descriptions for Functions 1-7
66
Table 16-10 TPLFE_FUNCTION_INFO Definition
66
Table 16-11 TPLFE_CSA_PROPERTY Definition
66
CISTPL_SDIO_STD: Function Is a Standard SDIO Function
67
CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards
67
Table 16-12 CISTPL_SDIO_STD: Tuple Reserved for SDIO Cards
67
Table 16-13 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards
67
Appendix A
68
A.1 SD and SPI Command List
68
Table A-14 SD Mode Command List
68
Table A-15 SPI Mode Command List
69
Appendix B
70
B.1 Normative References
70
Appendix C C.1 Abbreviations and Terms
71
Appendix D
73
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