User Manuals: hyperstone E1-32XS RISC/DSP Processor

Manuals and User Guides for hyperstone E1-32XS RISC/DSP Processor. We have 1 hyperstone E1-32XS RISC/DSP Processor manual available for free PDF download: User Manual

hyperstone E1-32XS User Manual

hyperstone E1-32XS User Manual (168 pages)

32-Bit-RISC/DSP

Brand: hyperstone | Category: Computer Hardware | Size: 3 MB

Table of Contents

Table of Contents
3
1 Architecture

9
- Introduction
  9
  - Compatibility
    10
  - Phased Locked Loop
    10
  - Registers
    10
  - Flags
    10
  - Register Data Types
    11
  - External Memory
    11
  - On-Chip Memory (IRAM)
    11
  - Memory Data Types
    11
  - Runtime Stack
    11
  - Instruction Cache
    11
  - Instructions General
    11
  - Instruction Summary
    12
  - Exceptions
    13
  - Timer
    14
  - Bus Interface
    14
  - Power Management
    14
- Block Diagram
  15
- Global Register Set
  16
  - Program Counter PC
    17
  - Status Register SR
    18
  - Floating-Point Exception Register FER
    21
  - Stack Pointer SP
    21
  - Upper Stack Bound UB
    21
  - Bus Control Register BCR
    21
  - Timer Prescaler Register TPR
    22
  - Timer Compare Register TCR
    22
  - Timer Register TR
    22
  - Watchdog Compare Register WCR
    22
  - Input Status Register ISR
    22
  - Function Control Register FCR
    22
  - Memory Control Register MCR
    22
- Local Register Set
  23
- Privilege States
  24
- Register Data Types
  25
- Memory Organization
  26
- Stack
  28
- Instruction Cache
  33
- On-Chip Memory (IRAM)
  35
2 Instructions General

37
- Instruction Notation
  37
- Instruction Execution
  38
- Instruction Formats
  39
- Entry Tables
  44
- Instruction Timing
  48
3 Instruction Set

51
- Memory Instructions
  51
  - Address Modes
    52
    
    Register Address Mode
    52
    
    Postincrement Address Mode
    52
    
    Displacement Address Mode
    52
    
    Absolute Address Mode
    52
    
    I/O Displacement Address Mode
    53
    
    I/O Absolute Address Mode
    53
    
    Next Address Mode
    54
    
    Stack Address Mode
    54
    
    Address Mode Encoding
    55
  - Load Instructions
    56
  - Store Instructions
    58
- Move Word Instructions
  60
- Move Double-Word Instruction
  60
- Logical Instructions
  61
- Invert Instruction
  62
- Mask Instruction
  62
- Add Instructions
  63
- S Ubtract
  64
- Sum Instructions
  65
- Subtract Instructions
  66
- Negate Instructions
  67
- Multiply Word Instruction
  68
- Multiply Double-Word Instructions
  68
- Divide Instructions
  69
- Shift Left Instructions
  70
- Shift Right Instructions
  71
- Rotate Left Instruction
  72
- Index Move Instructions
  73
- Check Instructions
  74
- N Ooperation Instruction
  74
- Compare Instructions
  75
- Compare Bit Instructions
  76
- Test Leading Zeros Instruction
  76
- Set Stack Address Instruction
  77
- Set Conditional Instructions
  77
- Branch Instructions
  79
- Delayed Branch Instructions
  80
- Call Instruction
  82
- Trap Instructions
  83
- Frame Instruction
  85
- Return
  86
- Return Instruction
  87
- Fetch Instruction
  89
- Extended Dsp Instructions
  90
- Software Instructions
  92
  - Do Instruction
    93
  - Floating-Point Instructions
    94
4 Exceptions

99
- Exception Processing
  99
- Exception Types
  100
  - Reset
    100
  - Range, Pointer, Frame and Privilege Error
    100
  - Extended Overflow
    101
  - Parity Error
    101
  - Interrupt
    101
  - Trace Exception
    102
- Exception Backtracking
  102
5 Timer and Cpu Clock Modes

105
- Overview
  105
  - Timer Prescaler Register TPR
    105
  - Timer Register TR
    106
  - Timer Compare Register TCR
    107
  - Power-Down Mode
    107
  - Additional Power Saving
    108
  - Sleep Mode
    109
6 Bus Interface

111
- Bus Control General
  111
  - Boot Width Selection
    112
  - SRAM and ROM Bus Access
    112
  - DRAM Bus Access, Fast Page Mode or EDO DRAM
    112
    
    DRAM Row Address Bits Multiplexing
    113
  - SDRAM Bus Access
    114
    
    SDRAM Row Address Bits Multiplexing
    114
    
    SDRAM Mode Register Setting
    115
    
    SDRAM Connection
    115
- I/O Bus Access
  116
- I/O Bu Acces
  116
- Bus Control Register Bcr
  118
- Memory Control Register Mcr
  122
  - Memx Parity Disable
    124
  - MEM2 Wait Disable
    124
  - Dramtype and Dramtype2
    125
  - Entry Table Map
    125
  - Memx Bus Hold Break
    125
  - Memx Bus Size
    125
- Sdram Control Register Sdcr
  126
  - Bankaddrenable
    126
  - Cs1Enable
    126
  - Cs1Select
    127
  - Caslatency
    127
  - Sdclkselect
    127
  - SDRAM Connection Example
    127
- Input Status Register Isr
  128
- Function Control Register Fcr
  129
  - Clkoutcontrol and Clkoutcontrol2
    131
- Watchdog Compare Register Wcr
  131
- Io3 Control Modes
  131
  - Io3Standard Mode
    131
  - Watchdog Mode
    131
  - Io3Timing Mode
    131
    
    On Io3Direction = Input
    132
    
    Io3Direction = Output
    132
  - Io3Timerinterrupt Mode
    132
- Bus Signals
  133
- Bus Cycles
  140
  - SRAM and ROM Accesses
    140
    
    SRAM and ROM Single-Cycle Read Access
    140
    
    SRAM Single-Cycle Write Access
    140
    
    Bu Cycle
    140
    
    SRAM and ROM Multi-Cycle Read Access
    141
    
    SRAM Multi-Cycle Write Access
    141
  - MEM2 Read Access with WAIT Pin
    142
  - I/O Read Access
    143
  - I/O Read Access with WAIT Pin
    144
  - I/O Write Access
    145
  - Dram
    146
    
    Fast Page Mode DRAM Access
    146
    
    EDO DRAM Single-Cycle Access
    147
    
    EDO DRAM Multi-Cycle Access
    148
    
    Fast Page Mode or EDO DRAM Refresh
    149
    
    SDRAM Access
    150
- DC Characteristics
  151
  - Absolute Maximum Ratings
    151
  - Parameters
    151
- Ac Characteristics
  152
  - Processor Clock and CLKIN
    152
  - GRANT# Response Time
    152
7 Mechanical Data

153

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