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hyperstone E1-16XS User Manual

32-bit-risc/dsp
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E1-32XS / E1-16XS
32-Bit-RISC/DSP Microprocessor
User's Manual

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  • Page 1 E1-32XS / E1-16XS 32-Bit-RISC/DSP Microprocessor User's Manual...
  • Page 2 Specifications and information in this document are subject to change without notice and do not represent a commitment on the part of Hyperstone AG. Hyperstone AG reserves the right to make changes to improve functioning. Although the information in this document has been carefully reviewed, Hyperstone AG does not assume any liability arising out of the use of the product or circuit described herein.

  • Page 3: Table Of Contents

    Table of Contents Table of Contents 1. ARCHITECTURE...................... 1-1 1.1. I ....................... 1-1 NTRODUCTION 1.1.1. Compatibility:....................1-2 1.1.2. Phased Locked Loop: ..................1-2 1.1.3. Registers:......................1-2 1.1.4. Flags:......................1-2 1.1.5. Register Data Types: ..................1-3 1.1.6. External Memory:................... 1-3 1.1.7. On-Chip Memory (IRAM): ................1-3 1.1.8.
  • Page 4 Table of Contents 2.4. E ....................... 2-8 NTRY ABLES 2.5. I ................... 2-12 NSTRUCTION IMING 3. INSTRUCTION SET ....................3-1 3.1. M ..................3-1 EMORY NSTRUCTIONS 3.1.1. Address Modes ....................3-2 3.1.1.1. Register Address Mode: ................3-2 3.1.1.2. Postincrement Address Mode: ..............3-2 3.1.1.3.
  • Page 5 Table of Contents 4. EXCEPTIONS ......................4-1 4.1. E ..................4-1 XCEPTION ROCESSING 4.2. E ....................4-2 XCEPTION YPES 4.2.1. Reset ....................... 4-2 4.2.2. Range, Pointer, Frame and Privilege Error ..........4-2 4.2.3. Extended Overflow ..................4-3 4.2.4. Parity Error ....................4-3 4.2.5.
  • Page 6 6.9.4. IO3TimerInterrupt Mode ................6-22 6.10. B ...................... 6-23 IGNALS 6.10.1. Bus Signals for the E1-32XS Processor ............. 6-23 6.10.2. Bus Signals for the E1-16XS Processor ............. 6-24 6.10.3. Bus Signal Description................6-25 6.11. B ....................... 6-30 YCLES 6.11.1. SRAM and ROM Accesses................6-30 6.11.1.1.
  • Page 7 Table of Contents 7.5.1. Package Dimensions LQFP ................. 7-13 7.5.2. Package Dimensions TFBGA ............... 7-15...

  • Page 9: Architecture

    E1-32XS User’s Manual Page 1-1 1. Architecture 1.1. Introduction microprocessors represent a further hyperstone E1-32XS hyperstone E1-16XS development of the processors. Using a hyperstone E1-32X hyperstone E1-16X sophisticated 0.25 µm CMOS process, the maximum clock rate of the processor could be further improved.

  • Page 10: Compatibility

    Most of the transistors are used for the on-chip memory, the instruction cache, the register stack and the multiplier, whereas only a small number is required for the control logic. Due to their low manufacturing costs, the hyperstone E1-32XS E1-16XS microprocessors are very well suited for embedded systems applications requiring high performance and lowest cost.

  • Page 11: Register Data Types

    E1-32XS User’s Manual Page 1-3 1.1.5. Register Data Types: Unsigned integer, signed integer, single or double signed short, signed complex short, single or double 16-bit fixed-point, bit string, IEEE-754 floating-point, each either 32 or 64 bits 1.1.6. External Memory: Address space of 4 Gbytes, divided into five areas Separate I/O address space Load/Store architecture Pipelined memory and I/O accesses...

  • Page 12: Instruction Summary

    Page 1-4 Architecture "source operator immediate ⇒ destination" All register bits participate in an operation Immediate operands of 5, 16 and 32 bits, zero- or sign-expanded Large address displacement of up to 28 bits Two sets of signed arithmetical instructions: instructions set or clear either only the overflow flag or trap additionally to a Range Error routine on overflow DSP instructions operate on 16-bit integer, real and complex fixed-point data and 32-bit integer data into 32-bit and 64-bit hardware accumulators...

  • Page 13: Exceptions

    E1-32XS User’s Manual Page 1-5 Compare bits, Compare bits immediate, Compare any byte zero Test number of leading zeros Set Conditional, save conditions in a register Branch unconditional and conditional (12 conditions) Delayed Branch unconditional and conditional (12 conditions) Call subprogram, unconditional and on overflow Trap to supervisor subprogram, unconditional and conditional (11 conditions) Frame, structure a new stack frame, include parameters in frame addressing, set frame length, restore reserve frame length and check for upper stack bound...

  • Page 14: Timer

    Separate address bus of 26 ( ) or 22 ( ) bits and data bus of up to 32 ( E1-32XS E1-16XS ) or 16 bits ( ) provide a throughput of up to four or two bytes at each clock 32XS E1-16XS cycle, respectively.

  • Page 15: Block Diagram

    E1-32XS User’s Manual Page 1-7 1.2. Block Diagram Register Set X Decode Y Decode 64 Local Instruction 26 Global Load Cache Decode Instruction Cache Control Instruction Decode Instruction Execution Control Barrel Shifter Execution Unit Instruction Bus Interface Prefetch Control Control Bus Pipeline Control Store Data...

  • Page 16: Global Register Set

    Page 1-8 Architecture 1.3. Global Register Set The architecture provides 32 global registers of 32 bits each. These are: Program Counter PC Status Register SR Floating-Point Exception Register FER G3..G15 General purpose registers G16..G17 Reserved Stack Pointer SP Upper Stack Bound UB Bus Control Register BCR (see section 6.

  • Page 17: Program Counter Pc

    E1-32XS User’s Manual Page 1-9 Program Counter PC Status Register SR Floating-Point Exception Register FER General Purpose Registers G3..G15 Reserved Reserved Stack Pointer SP Upper Stack Bound UB Bus Control Register BCR Timer Prescaler Register TPR Timer Compare Register TCR Timer Register TR Watchdog Compare Register WCR Input Status Register ISR...

  • Page 18: Status Register Sr

    Page 1-10 Architecture 1.3.2. Status Register SR G1 is the status register SR. Its content is updated by instruction execution. Besides this implicit updating, the SR can also be addressed like a regular register. When addressed as source or destination operand, all 32 bits are used as an operand. However, only bits 15..0 of a result can be placed in bits 15..0 of the SR, bits 31..16 of the result are discarded and bits 31..16 of the SR remain unchanged.
  • Page 19 E1-32XS User’s Manual Page 1-11 The status register SR contains the following status information: Bit zero is the carry condition flag C. In general, when set it indicates that the unsigned integer range has been exceeded. At add operations, it indicates a carry out of bit 31 of the result.
  • Page 20 Page 1-12 Architecture Bit 15 is the interrupt-lock flag L. When the L flag is one, all Interrupt, Parity Error and Extended Overflow exceptions regardless of individual mode bits are inhibited. The state of the L flag is effective immediately after any instruction which changed it.

  • Page 21: Floating-Point Exception Register Fer

    E1-32XS User’s Manual Page 1-13 1.3.3. Floating-Point Exception Register FER G2 is the floating-point exception register. Only bits 12..8 and 4..0 may be changed by a user program, all other bits must remain unchanged. Reserved Reserved for Operating System Floating-Point Actual Exceptions Floating-Point Accrued Exceptions Figure 1.5: Floating-Point Exception Register 1.3.4.

  • Page 22: Timer Prescaler Register Tpr

    Page 1-14 Architecture 1.3.7. Timer Prescaler Register TPR G21 is the write-only timer prescaler register TPR. It adapts the timer clock to different processor clock frequencies and controls the processor clock generation by the PLL circuit. The TPR can be addressed only via the high global flag H being set. Copying an operand to the TPR is a privileged operation.

  • Page 23: Local Register Set

    E1-32XS User’s Manual Page 1-15 1.4. Local Register Set The architecture provides a set of 64 local registers of 32 bits each. The local registers 0..63 represent the register part of the stack, containing the most recent stack frame(s). Local Register L0 Local Register L15 Figure 1.6: Local Register Set 0..63 The local registers can be addressed by the register code (0..15) of an instruction as...

  • Page 24: Privilege States

    Page 1-16 Architecture 1.5. Privilege States The architecture provides two privilege states, determined by the supervisor state flag S: user state (S = 0) and supervisor state (S = 1). The runtime kernel hyRTK is executed in the higher privileged supervisor state, thereby restricting access to all sensitive data to a highly reliable system program.

  • Page 25: Register Data Types

    E1-32XS User’s Manual Page 1-17 1.6. Register Data Types Register: 32 Bits Bitstring High-Order 32-Bits Low-Order 32-Bits Double-Word Bitstring 32-Bit Magnitude Unsigned Integer High-Order 32-Bit Magnitude Low-Order 32-Bit Magnitude Unsigned Double-Word Integer 31-Bit Magnitude Signed Integer, Two's Complement High-Order 31-Bit Magnitude Low-Order 32-Bit Magnitude Signed Double-Word Integer, Two's Complement S MSB...

  • Page 26: Memory Organization

    Page 1-18 Architecture 1.7. Memory Organization The architecture provides a memory address space in the range of 0..2 (0..4 294 967 295) 8-bit bytes. Memory is implied to be organized as 32-bit words. The following memory data types are available (see figure 1.8) Byte unsigned (unsigned 8-bit integer, bit string or character) Byte signed (signed 8-bit integer, two's complement) Half-word unsigned (unsigned 16-bit integer or bit string)
  • Page 27 E1-32XS User’s Manual Page 1-19 Figure 1.8 shows the location of data and instructions in memory relative to a binary address n = ...xxx00 (x = 0 or 1). The memory organization is big-endian. Byte n Byte n + 1 Byte n + 2 Byte n + 3 Halfword n...

  • Page 28: Stack

    Page 1-20 Architecture 1.8. Stack A runtime stack, called stack here, holds generations of local variables in last-in-first-out order. A generation of local variables, called stack frame or activation record, is created upon subprogram entry and released upon subprogram return. The runtime stack provided by the architecture is divided into a memory part and a register part.
  • Page 29 E1-32XS User’s Manual Page 1-21 Because the complete stack management is accomplished automatically by the hardware, programming the stack handling instructions is easy and does not require any knowledge of the internal working of the stack. The following example demonstrates how the Call, Frame and Return instructions are applied to achieve the stack behavior of the register part of the stack shown in the figures 1.9 and 1.10.
  • Page 30 Page 1-22 Architecture Program Example: FRAME L13, L3 ; set frame length FL = 13, decrement FP by 3 ; parameters passed to A can be addressed ; in L0, L1, L2 code of function A L7, L5 ; copy L5 to L7 for use as parameter1 MOVI L8, 4 ;...
  • Page 31 E1-32XS User’s Manual Page 1-23 Figure 1.9 shows the creation and release of stack frames in the register part of the stack. Return from B Call B Frame in B PC := ret. PC for B; PC := branch address; FP := FP - code of source reg.;...
  • Page 32 Page 1-24 Architecture before Frame Instruction for frame X after Frame Instruction for frame X register part memory part register part memory part of the stack of the stack of the stack of the stack A and X overlap modulo 64 words stack stack...

  • Page 33: Instruction Cache

    E1-32XS User’s Manual Page 1-25 1.9. Instruction Cache The instruction cache is transparent to programs. A program executes correctly even if it ignores the cache, whereby it is assumed that a program does not modify the instruction code in the local range contained in the cache. The instruction cache holds a total of up to 128 bytes (32 unstructured 32-bit words of instructions).
  • Page 34 Page 1-26 Architecture The cache is read in the decode cycle by using bits 6..1 of the PC as an address to the first half-word of the instruction presently being decoded. The instruction decode needs and uses only the number (1, 2 or 3) of instruction half-words defined by the instruction format.

  • Page 35: On-Chip Memory (Iram)

    E1-32XS User’s Manual Page 1-27 Enabling the cache-mode flag M is only required when a program loop to be contained in the cache contains a forward branch to a branch target in the program loop and more than three (or four, see above) instruction half-words are to be skipped. In this case, the enabled M flag in combination with a Delayed Branch instruction with an instruction length of one half-word inhibits flushing the cache when the branch target is not yet prefetched.

  • Page 37: Instructions General

    E1-32XS User’s manual Page 2-1 2. Instructions General 2.1. Instruction Notation In the following instruction-set presentation, an informal description of an instruction is followed by a formal description in the form: Format Notation Operation Format denotes the instruction format. Notation gives the assembler notation of the instruction. Operation describes the operation with the following symbols: denotes any of the local registers L0..L15 used as source register or as source operand.

  • Page 38: Instruction Execution

    Page 2-2 Instructions General 2.2. Instruction Execution On instruction execution, all bits of the operands participate in the operations, except on the Shift and Rotate instructions (whereat only the 5 least significant bits of the source operand are used) and except on the byte and half-word Store instructions. Instructions are executed by a two-stage pipeline.

  • Page 39: Instruction Formats

    E1-32XS User’s manual Page 2-3 2.3. Instruction Formats Instructions have a length of one, two or three half-words and must be located on half- word boundaries. The following formats are provided: Format Configuration Ls-code encodes L0..L15 for Ls OP-code Ld-code Ls-code Ld-code encodes L0..L15 for Ld Ls-code encodes L0..L15 for Ls...
  • Page 40 Page 2-4 Instructions General Format Configuration s = 0: Rs-code encodes G0..G15 for Rs s = 1: Rs-code encodes L0..L15 for Rs LRconst OP-code Ld-code Rs-code Ld-code encodes L0..L15 for Ld Sign bit of const const1 e = 0: const = 18 S//const1 const2 range -16 384..16 383 e = 1:...

  • Page 41: Table Of Immediate Values

    E1-32XS User’s manual Page 2-5 2.3.1. Table of Immediate Values immediate value imm Comment 0..16 0..16 at CMPBI, n = 0 encodes ANYBZ at ADDI and ADDSI n = 0 encodes CZ imm1//imm2 range = 0..2 -1 or -2 16 zeros//imm1 range = 0..65 535 16 ones//imm1 range = -65 536..-1...

  • Page 42: Table Of Instruction Codes

    Page 2-6 Instructions General 2.3.2. Table of Instruction Codes Table 2.4: Table of Instruction Codes...

  • Page 43: Table Of Extended Dsp Instruction Codes

    E1-32XS User’s manual Page 2-7 2.3.3. Table of Extended DSP Instruction Codes The Extended DSP instructions are specified by a 16-bit OP-code extension succeeding the instruction op-code for the EXTEND instruction. See section 3.32. Extended DSP Instructions. Instruction OP-code extension (hex) EMUL 0102 EMULU...

  • Page 44: Entry Tables

    Page 2-8 Instructions General 2.4. Entry Tables Spacing of the entries for the Trap instructions and exceptions is four bytes. These entries are intended to each contain an instruction branching to the associated function. The entries for the TRAPxx instructions are the same as for TRAP. Table 2.6 shows the trap entries when the entry table is mapped to the end of memory area MEM3 (default after Reset): Address (Hex)
  • Page 45 E1-32XS User’s manual Page 2-9 Table 2.7 shows the trap entries when the entry table is mapped to the beginning of memory areas MEM0, MEM1, MEM2 or IRAM. x is 0, 4, 8 or C corresponding to the mapping to MEM0, MEM1, MEM2 or IRAM respectively. Address (Hex) Entry Description...
  • Page 46 Page 2-10 Instructions General Table 2.8 below shows the addresses of the first instruction of the emulator code associated with the floating-point instructions when the trap entry tables are mapped to the end of memory area MEM3. Spacing of the entries for the Software instructions FADD..DO is 16 bytes.
  • Page 47 E1-32XS User’s manual Page 2-11 Table 2.9 below shows the addresses of the first instruction of the emulator code associated with the floating-point instructions when the trap entry tables are mapped to the beginning of memory areas MEM0, MEM1, MEM2 or IRAM. x is 0, 4, 8 or C corresponding to the mapping to MEM0, MEM1, MEM2 or IRAM respectively.

  • Page 48: Instruction Timing

    Page 2-12 Instructions General 2.5. Instruction Timing The following execution times are given in number of processor clock cycles. All instructions not shown below: 1 cycle Move double-word: 2 cycles Shift double-word: 2 cycles Test Leading Zeros: 2 cycles Multiply word: when both operands are in the range of -2 -1: 3 cycles all other cases: 5 cycles...
  • Page 49 E1-32XS User’s manual Page 2-13 Fetch instruction: when the required number of instruction half-words are already prefetched in the instruction cache: 1 cycle otherwise 1 + (required number of half-words - number of half-words already prefetched)/2 * bus cycles per access Memory word instructions, non-stack address mode: 1 cycle Memory word instructions, stack address mode:...
  • Page 50 Page 2-14 Instructions General Latency cycles are defined as the time that the multiply-accumulate execution unit is busy executing the Extended DSP instruction. In the last latency cycle of an Extended DSP instruction that is currently executed, the issue cycle of the next Extended DSP instruction may take place.

  • Page 51: Instruction Set

    E1-32XS User’s manual Page 3-1 3. Instruction Set 3.1. Memory Instructions The memory instructions load data from memory in a register Rs (or a register pair Rs//Rsf) or store data from Rs (or Rs//Rsf) to memory using the data types byte unsigned/signed, half-word unsigned/signed, word or double-word.

  • Page 52: Address Modes

    Page 3-2 Instruction Set 3.1.1. Address Modes 3.1.1.1. Register Address Mode: Notation: LDxx.R, STxx.R -- xx: word or double-word data type The content of the destination register Ld is used as an address into memory address space. 3.1.1.2. Postincrement Address Mode: Notation: LDxx.P, STxx.P...

  • Page 53: I/O Displacement Address Mode

    E1-32XS User’s manual Page 3-3 3.1.1.5. I/O Displacement Address Mode: Notation: LDxx.IOD, STxx.IOD -- xx: word or double-word data type The sum of the contents of the destination register Rd plus a signed displacement dis is used as an address into I/O address space. Rd may denote any register except the SR;...

  • Page 54: Next Address Mode

    Page 3-4 Instruction Set 3.1.1.7. Next Address Mode: Notation: LDxx.N, STxx.N -- xx: any data type The content of the destination register Rd is used as an address into memory address space, then Rd is incremented by the signed displacement dis regardless of any exception occurring.

  • Page 55: Address Mode Encoding

    E1-32XS User’s manual Page 3-5 3.1.1.9. Address Mode Encoding: The encoding of the displacement and absolute address mode types of memory instructions is shown in table 3.1: LDxx.D/A/IOD/IOA STxx.D/A/IOD/IOA D-code dis(1) dis(0) Rd does not Rd denotes SR Rd does not Rd denotes SR denote SR denote SR...

  • Page 56: Load Instructions

    Page 3-6 Instruction Set 3.1.2. Load Instructions The Load instructions transfer data from the addressed memory location into a register Rs or a register pair Rs//Rsf. In the case of data types word and double-word, one or two words are read from memory and transferred unchanged into Rs or Rs//Rsf respectively.
  • Page 57 E1-32XS User’s manual Page 3-7 Format Notation Operation Data Type xx LDxx.R Ld, Rs Rs := Ld^; [Rsf := (Ld + 4)^;] -- register address mode LDxx.P Ld, Rs Rs := Ld^; Ld := Ld + size; -- size = 4 or 8 [Rsf := (old Ld + 4)^;] -- post-increment address mode RRdis...

  • Page 58: Store Instructions

    Page 3-8 Instruction Set 3.1.3. Store Instructions The Store instructions transfer data from the register Rs or the register pair Rs//Rsf to the addressed memory location. In the case of data types word or double-word, one or two words are placed unchanged from Rs or Rs//Rsf respectively onto the data bus to be stored in the memory.
  • Page 59 E1-32XS User’s manual Page 3-9 Format Notation Operation Data Type xx STxx.R Ld, Rs Ld^ := Rs; [(Ld + 4)^ := Rsf;] -- register address mode STxx.P Ld, Rs Ld^ := Rs; Ld := Ld + size; -- size = 4 or 8 [(old Ld + 4)^ := Rsf;] -- post-increment address mode RRdis...

  • Page 60: Move Word Instructions

    Page 3-10 Instruction Set 3.2. Move Word Instructions The source operand or the immediate operand is copied to the destination register and the condition flags are set or cleared accordingly. Format Notation Operation MOV Rd, Rs Rd := Rs; Z := Rd = 0; N := Rd(31);...

  • Page 61: Logical Instructions

    E1-32XS User’s manual Page 3-11 3.4. Logical Instructions The result of a bitwise logical AND, AND not (ANDN), OR or exclusive OR (XOR) of the source or immediate operand and the destination operand is placed in the destination register and the Z flag is set or cleared accordingly. At ANDN, the source operand is used inverted (itself remaining unchanged).

  • Page 62: Invert Instruction

    Page 3-12 Instruction Set 3.5. Invert Instruction The source operand is placed bitwise inverted in the destination register and the Z flag is set or cleared accordingly. The source operand and the result are interpreted as bit strings of 32 bits each. Format Notation Operation...

  • Page 63: Add Instructions

    E1-32XS User’s manual Page 3-13 3.7. Add Instructions The source operand, the source operand + C or the immediate operand is added to the destination operand, the result is placed in the destination register and the condition flags are set or cleared accordingly. At ADD, ADDC and ADDI, both operands and the result are interpreted as either all signed or all unsigned integers.

  • Page 64: S Ubtract

    Page 3-14 Instruction Set Format Notation Operation Rimm ADDI Rd, imm Rd := Rd + imm; -- signed or unsigned Add Z := Rd = 0; N := Rd(31); -- sign V := overflow; C := carry; Rimm ADDSI Rd, imm Rd := Rd + imm;...

  • Page 65: Sum Instructions

    E1-32XS User’s manual Page 3-15 3.8. Sum Instructions The sum of the source operand and the immediate operand is placed in the destination register and the condition flags are set or cleared accordingly. At SUM, both operands and the result are interpreted as either all signed or all unsigned integers. At SUMS, both operands and the result are signed integers and a trap to Range Error occurs at overflow.

  • Page 66: Subtract Instructions

    Page 3-16 Instruction Set 3.9. Subtract Instructions The source operand or the source operand + C is subtracted from the destination operand, the result is placed in the destination register and the condition flags are set or cleared accordingly. At SUB and SUBC, both operands and the result are interpreted as either all signed or all unsigned integers.

  • Page 67: Negate Instructions

    E1-32XS User’s manual Page 3-17 3.10. Negate Instructions The source operand is subtracted from zero, the result is placed in the destination register and the condition flags are set or cleared accordingly. At NEG and NEGS, the source operand and the result are interpreted as either both signed or both unsigned integers.

  • Page 68: Multiply Word Instruction

    Page 3-18 Instruction Set 3.11. Multiply Word Instruction The source operand and the destination operand are multiplied, the low-order word of the product is placed in the destination register (the high-order product word is not evaluated) and the condition flags are set or cleared according to the single-word product. Both operands are either signed or unsigned integers, the product is a single-word integer.

  • Page 69: Divide Instructions

    E1-32XS User’s manual Page 3-19 3.13. Divide Instructions The double-word destination operand (dividend) is divided by the single-word source operand (divisor), the quotient is placed in the low-order destination register (Rdf), the remainder is placed in the high-order destination register (Rd) and the condition flags are set or cleared according to the quotient.

  • Page 70: Shift Left Instructions

    Page 3-20 Instruction Set 3.14. Shift Left Instructions The destination operand is shifted left by a number of bit positions specified at SHLI, SHLDI by n = 0..31 as a shift by 0..31; at SHL, SHLD by bits 4..0 of the source operand as a shift by 0..31. The higher-order bits of the source operand are ignored.

  • Page 71: Shift Right Instructions

    E1-32XS User’s manual Page 3-21 3.15. Shift Right Instructions The destination operand is shifted right by a number of bit positions specified at SARI, SARDI, SHRI, SHRDI by n = 0..31 as a shift by 0..31. at SAR, SARD, SHR, SHRD by bits 4..0 of the source operand as a shift by 0..31. The higher-order bits of the source operand are ignored.

  • Page 72: Rotate Left Instruction

    Page 3-22 Instruction Set 3.16. Rotate Left Instruction The destination operand is shifted left by a number of bit positions and the bits shifted out are inserted in the vacated bit positions; thus, the destination operand is rotated. The condition flags are set or cleared accordingly. Bits 4..0 of the source operand specify a rotation by 0..31 bit positions;...

  • Page 73: Index Move Instructions

    E1-32XS User’s manual Page 3-23 3.17. Index Move Instructions The source operand is placed shifted left by 0, 1, 2 or 3 bit positions in the destination register, corresponding to a multiplication by 1, 2, 4 or 8. At XM1..XM8, a trap to Range Error occurs if the source operand is higher than the immediate operand lim (upper bound).

  • Page 74: Check Instructions

    Page 3-24 Instruction Set 3.18. Check Instructions The destination operand is checked and a trap to Range Error occurs at CHK if the destination operand is higher than the source operand, at CHKZ if the destination operand is zero. All registers and all condition flags remain unchanged. All operands are interpreted as unsigned integers.

  • Page 75: Compare Instructions

    E1-32XS User’s manual Page 3-25 3.20. Compare Instructions Two operands are compared by subtracting the source operand or the immediate operand from the destination operand. The condition flags are set or cleared according to the result; the result itself is not retained. Note that the N flag indicates the correct compare result even in the case of an overflow.

  • Page 76: Compare Bit Instructions

    Page 3-26 Instruction Set 3.21. Compare Bit Instructions The result of a bitwise logical AND of the source or immediate operand and the destination operand is used to set or clear the Z flag accordingly; the result itself is not retained. All operands and the result are interpreted as bit strings of 32 bits each.

  • Page 77: Set Stack Address Instruction

    E1-32XS User’s manual Page 3-27 3.23. Set Stack Address Instruction The frame pointer FP is placed, expanded to the stack address, in the destination register. The FP itself and all condition flags remain unchanged. The expanded FP address is the address at which the content of L0 would be stored if pushed onto the memory part of the stack.
  • Page 78 Page 3-28 Instruction Set Format is Rn Notation Alternative Operation Reserved SET1 Rd Rd := 1; SET0 Rd Rd := 0; SETLE Rd if N = 1 or Z = 1 then Rd := 1 else Rd := 0; SETGT Rd if N = 0 and Z = 0 then Rd := 1 else Rd := 0;...

  • Page 79: Branch Instructions

    E1-32XS User’s manual Page 3-29 3.25. Branch Instructions The Branch instruction BR, and any of the conditional Branch instructions when the branch condition is met, place the branch address PC + rel (relative to the address of the first byte after the Branch instruction) in the program counter PC and clear the cache-mode flag M;...

  • Page 80: Delayed Branch Instructions

    Page 3-30 Instruction Set 3.26. Delayed Branch Instructions The Delayed Branch instruction DBR, and any of the conditional Delayed Branch in- structions when the branch condition is met, place the branch address PC + rel (relative to the address of the first byte after the Delayed Branch instruction) in the program counter PC.
  • Page 81 E1-32XS User’s manual Page 3-31 Format is PCrel Notation or alternative Operation Comment DBLE rel if N = 1 or Z = 1 then DBR; -- Less or Equal signed DBGT rel if N = 0 and Z = 0 then DBR; -- Greater Than signed DBLT rel DBN rel...

  • Page 82: Call Instruction

    Page 3-32 Instruction Set 3.27. Call Instruction The Call instruction causes a branch to a subprogram. The branch address Rs + const, or const alone if Rs denotes the SR, is placed in the program counter PC. The old PC containing the return address is saved in Ld; the old supervisor-state flag S is also saved in bit zero of Ld.

  • Page 83: Trap Instructions

    E1-32XS User’s manual Page 3-33 3.28. Trap Instructions The Trap instructions TRAP and any of the conditional Trap instructions when the trap condition is met, cause a branch to one out of 64 supervisor subprogram entries (see section 2.4. Entry Tables). When the trap condition is not met, instruction execution proceeds sequentially.
  • Page 84 Page 3-34 Instruction Set Format is PCadr Code Notation Operation TRAPLE trapno if N = 1 or Z = 1 then execute TRAP else execute next instruction; TRAPGT trapno if N = 0 and Z = 0 then execute TRAP else execute next instruction;...

  • Page 85: Frame Instruction

    E1-32XS User’s manual Page 3-35 3.29. Frame Instruction A Frame instruction restructures the current stack frame by decrementing the frame pointer FP to include (optionally) passed parameters in the local register addressing range; the first parameter passed is then addressable as L0; resetting the frame length FL to the actual number of registers needed for the current stack frame.

  • Page 86: Return

    Page 3-36 Instruction Set Format Notation Operation FRAME Ld, Ls FP := FP - Ls code; FL := Ld code; M := 0; difference(6..0) := SP(8..2) + (64 - 10) - (FP + FL); -- FL = 0 is treated as FL = 16 -- difference is signed, difference(6) = sign bit -- 64 = number of local registers -- 10 = number of reserve registers...

  • Page 87: Return Instruction

    E1-32XS User’s manual Page 3-37 3.30. Return Instruction The Return instruction returns control from a subprogram entered through a Call, Trap or Software instruction or an exception to the instruction located at the return address and restores the status from the saved return status. The source operand pair Rs//Rsf is placed in the register pair PC//SR.
  • Page 88 Page 3-38 Instruction Set Format Notation Operation RET PC, Rs old S := S; old L := L; PC := Rs(31..1)//0; SR := Rsf(31..21)//00//Rs(0)//Rsf(17..0); -- ILC := 0; -- S := Rs(0); if old S = 0 and S = 1 or S = 0 and old L = 0 and L = 1 then trap ⇒...

  • Page 89: Fetch Instruction

    E1-32XS User’s manual Page 3-39 3.31. Fetch Instruction The instruction execution is halted until a number of at least n/2 + 1 (n = 0, 2, 4..30) instruction half-words succeeding the Fetch instruction are prefetched in the instruction cache. Since instruction words are fetched, one more half-word may be fetched. The number n/2 is derived by using bits 4..1 of n, bit 0 of n must be zero.

  • Page 90: Extended Dsp Instructions

    Page 3-40 Instruction Set 3.32. Extended DSP Instructions The Extended DSP instructions use the on-chip multiply-accumulate unit. Single word results always use register G15 as destination register, while double-word results are always placed in G14 and G15. The condition flags remain unchanged. Format Notation Operation...
  • Page 91 E1-32XS User’s manual Page 3-41 Format Notation Operation LLext EHCFFTSD Ld, Ls G14(31..16) := (Ld(31..16) + (G14 >> 15)) >> 1; G14(15..0) := (Ld(15..0) + (G15 >> 15)) >> 1; G15(31..16) := (Ld(31..16) - (G14 >> 15)) >> 1; G15(15..0) := (Ld(15..0) - (G15 >> 15)) >> 1; -- half-word (complex) add/subtract with fixed-point adjustment and shift -- Ls is not used and should denote the same register as Ld...

  • Page 92: Software Instructions

    Page 3-42 Instruction Set 3.33. Software Instructions The Software instructions cause a branch to the subprogram associated with each Software instruction. Its entry address (see section 2.4. Entry Tables), deduced from the OP-code of the Software instruction, is placed in the program counter PC. Data is saved in the register sequence beginning at register address FP + FL (FL = 0 is interpreted as FL = 16) in ascending order as follows: Stack address of the destination operand...

  • Page 93: Do Instruction

    E1-32XS User’s manual Page 3-43 3.33.1. Do Instruction The Do instruction is executed as a Software instruction. The associated subprogram is entered, the stack address of the destination operand and one double-word source operand are passed to it (see section 3.33.

  • Page 94: Floating-Point Instructions

    Page 3-44 Instruction Set 3.33.2. Floating-Point Instructions The Floating-Point instructions comply with the ANSI/IEEE standard 754-1985. In the present version, they are executed as Software instructions. The following description provides a general overview of the architectural integration. The basic instructions use single-precision (single-word) and double-precision (double- word) operands.
  • Page 95 E1-32XS User’s manual Page 3-45 Format Notation Operation FADD Ld, Ls Ld := Ld + Ls; FADDD Ld, Ls Ld//Ldf := (Ld//Ldf) + (Ls//Lsf); FSUB Ld, Ls Ld := Ld - Ls; FSUBD Ld, Ls Ld//Ldf := (Ld//Ldf) - (Ls//Lsf); Ld := Ld ∗...
  • Page 96 Page 3-46 Instruction Set A floating-point instruction, except a Floating-point Compare, can raise any of the exceptions Invalid Operation, Division by Zero, Overflow, Underflow or Inexact. FCMP and FCMPD can raise only the Invalid Operation exception (at unordered). FCMPU and FCMPUD cannot raise any exception.
  • Page 97 E1-32XS User’s manual Page 3-47 The table below shows the combinations of Floating-Point Compare and Branch in- structions to test all 14 floating-point relations: relation Compare Branch Branch exception on true on false if unordered FCMPU FCMPU ?≠ > FCMP ≥...

  • Page 99: Exceptions

    E1-32XS User’s manual Page 4-1 4. Exceptions 4.1. Exception Processing Exceptions are events which redirect the flow of control to a supervisor subprogram associated with the type of exception, that is, a trap occurs as a response to the exception. (See a detailed description of exceptions further below.) If exceptions coincide, the exception with the highest priority takes precedence over all exceptions with lower priority.

  • Page 100: Exception Types

    Page 4-2 Exceptions 4.2. Exception Types The following exception are types ordered by priorities, Reset has the highest priority. In case of coincidental exceptions, higher-priority exceptions overrule lower-priority exceptions. 4.2.1. Reset A Reset exception occurs on a transition of the RESET# signal from low to high or as a result of a watchdog overrun in IO3 Watchdog mode or after a reset following a clock- down command.

  • Page 101: Extended Overflow

    E1-32XS User’s manual Page 4-3 4.2.3. Extended Overflow An Extended Overflow condition is raised on an overflow caused by an add or subtract operation as part of the execution of one of the Extended instructions EMAC through EHCFFTSD when the Extended Overflow exception is enabled. The Extended Overflow exception is enabled by clearing bit 16 of the function control register FCR to zero.

  • Page 102: Trace Exception

    Page 4-4 Exceptions 4.2.6. Trace Exception A Trace exception occurs after each execution of an instruction except a Delayed Branch instruction when the trace mode is enabled (trace flag T = 1) and the trace pending flag P is one. After a Call instruction, a Trace exception is suppressed until the next instruction is executed regardless of the trace mode being enabled;...
  • Page 103 E1-32XS User’s manual Page 4-5 The stack address of a local register denoted by a backtracked instruction can be calculated according to the following formula: stack address of preceding stack frame := stack address of current stack frame - (((FP - saved FP) modulo 64) * 4); -- bits 5..0 of the difference (FP - saved FP) are used zero-expanded -- * 4 converts word difference ⇒...

  • Page 105: Timer And Cpu Clock Modes

    E1-32XS User’s manual Page 5-1 5. Timer and CPU Clock Modes 5.1. Overview The on-chip timer is controlled via three registers: Timer prescaler register TPR Timer register TR Timer compare register TCR The timer prescaler register also controls the processor clock output of the PLL circuit. G21..G23 can be addressed only via the high global flag H by a MOV or MOVI instruction.

  • Page 106: Timer Register Tr

    Page 5-2 Timer and CPU Clock Modes Bits Name Description LoadEnable 1 = TPR update is delayed until current prescaler time unit ends 0 = TPR update is performed immediately 30..29 reserved 28..26 ClockDivider CPU Clock Divider Control 111 = reserved 110 = reserved 101 = reserved 100 = CPU clock = XTAL1 clock / 2...

  • Page 107: Timer Compare Register Tcr

    E1-32XS User’s manual Page 5-3 5.1.3. Timer Compare Register TCR The content of the TCR is compared continuously with the content of the timer register TR. An unsigned modulo comparison is performed according to: result(31..0) := TR(31..0) - TCR(31..0) = 0, the TR is higher than or equal to the TCR. result(31) When the timer interrupt is enabled (FCR(23) = 0) and the value in the TR is higher than or equal to the value in the TCR, a timer interrupt is generated.

  • Page 108: Additional Power Saving

    Page 5-4 Timer and CPU Clock Modes Power-down mode can be set by a program sequence as in the following example: PowerDownIO 1 << 27 | %1110 << 22 ; Bits 27, 25..23, 22 STW.IOA 0, 0, PowerDownIO ; set power-down mode LDW.IOA 0, L4, PowerDownIO | 8 ;...

  • Page 109: Sleep Mode

    E1-32XS User’s manual Page 5-5 5.1.6. Sleep Mode To further reduce power dissipation, the processor can be set into sleep mode. In this case, the clock of the processor is completely switched off. When a quartz crystal is used for processor clock generation, it is also switched off.

  • Page 111: Bus Interface

    E1-32XS User’s manual Page 6-1 6. Bus Interface 6.1. Bus Control General The processor provides on-chip all functions for controlling memory and peripheral devices, including RAS-CAS multiplexing, DRAM refresh and parity generation and checking. Supported DRAM types include Fast Page Mode, EDO, and Synchronous DRAM.

  • Page 112: Boot Width Selection

    Table 6.2: Data bus width encoding for memory area MEM3 For the E1-16XS processor the BOOTW pin is connected to the BOOTB pin internally. Thus the BOOTB pin can be used to select between 8-bit and 16-bit MEM3 bus width.

  • Page 113: Dram Row Address Bits Multiplexing

    E1-32XS User’s manual Page 6-3 For Fast Page Mode DRAM, the OE# processor signal is not switched, it always remains high during DRAM accesses. The DRAM’s OE# signal must be connected to ground. For EDO DRAM, the processor’s OE# signal must be connected to the corresponding DRAM signal.

  • Page 114: Sdram Bus Access

    SDRAM chip selects can be selected from address bits A21 to A28. The second SDRAM chip select signal is not available on the . See the SDRAM E1-16XS Control Register description in section 6.5. 6.1.4.1. SDRAM Row Address Bits Multiplexing For row access and column access, the address bits are multiplexed corresponding to the SDRAM address mapping table given below depending on the Page Size Code (PSC).

  • Page 115: Sdram Mode Register Setting

    The table lists the SDRAM pins and the corresponding E1-32XS pins for all the SDRAM signals. 16XS SDRAM pin E1-32XS pin E1-16XS pin Signal CAS3# CAS1# SDRAM Clock signal SDCLK SDRAM Clock Enable signal SDRAM first bank chip select CS0# —...

  • Page 116: I/O Bus Access

    MCR must be set to 1 if SDRAM is used. 6.2. I/O Bus Access Hyperstone provides a completely separate I/O address range which makes it possible to connect numerous peripheral devices each with individual behavior. Bus timing and access mode for an I/O access is specified by bits 11..3 of the I/O address.
  • Page 117 E1-32XS User’s manual Page 6-7 For I/O accesses, address setup, access and bus hold time can be specified by bits in the I/O address as described in Figure 6.1. Reserved bits must always be supplied as zero when specifying an I/O address in a program. Reserved (must be 0) I/O Address and/or I/O Chip Select E1-16X: 6 Bits...

  • Page 118: Bus Control Register Bcr

    Page 6-8 Bus Interface 6.3. Bus Control Register BCR Global register G20 is the write-only bus control register BCR. The BCR defines the pa- rameters (bus timing, refresh control) for accessing external memory located in address spaces MEM0..MEM3. All bits of the BCR are set to one on Reset. They are intended to be initialized according to the hardware environment.
  • Page 119 E1-32XS User’s manual Page 6-9 Bits Name Description Mem1Hold Bus hold time for address space MEM1 When BCR(22) = 1: 1 = 2 clock cycles 0 = 1 clock cycle When BCR(22) = 0: 1 = 1 clock cycle 0 = 0 clock cycles 22..20 Mem1Access Access time for address space MEM1...
  • Page 120 Page 6-10 Bus Interface Bits Name Description MEM0 = DRAM (MCR(21) = 0): 19..18 RasPrecharge RAS precharge time for address space MEM0 when MCR(8)=0 when MCR(8)=1 11 = 4 clock cycles 6 clock cycles 10 = 3 clock cycles 5 clock cycles 01 = 2 clock cycles 4 clock cycles 00 = 1 clock cycle...
  • Page 121 E1-32XS User’s manual Page 6-11 Bits Name Description Mem2Setup Address setup time for address space MEM2 1 = 1 clock cycle 0 = 0 clock cycles 2..0 Mem2Hold Bus hold time for address space MEM2 111 = 7 clock cycles 110 = 6 clock cycles 101 = 5 clock cycles 100 = 4 clock cycles...

  • Page 122: Memory Control Register Mcr

    Page 6-12 Bus Interface 6.4. Memory Control Register MCR Global register G27 is the write-only memory control register MCR. The MCR controls additional parameters for the external memory and the mapping of the entry table. All bits of the MCR are set to one on Reset except for the MEM3BusSize bits that are initialized from the BOOTW and BOOTB pads.
  • Page 123 E1-32XS User’s manual Page 6-13 Bits Name Description MEM0 = DRAM (MCR(21) = 0): DRAMType 1 = Fast Page Mode DRAMs 0 = EDO DRAMs 14..12 EntryTableMap 111 = MEM3 110 = reserved 101 = reserved 100 = reserved 011 = Internal RAM (IRAM) 010 = MEM2 001 = MEM1 000 = MEM0...

  • Page 124: Memx Parity Disable

    Page 6-14 Bus Interface Bits Name Description 7..6 MEM3BusSize 11 = 8 bit 10 = 16 bit 01 = reserved 00 = 32 bit 5..4 MEM2BusSize 11 = 8 bit 10 = 16 bit 01 = reserved 00 = 32 bit 3..2 MEM1BusSize 11 = 8 bit...

  • Page 125: Dramtype And Dramtype2

    E1-32XS User’s manual Page 6-15 6.4.3. DRAMType and DRAMType2 When the MEM0 memory type is set to DRAM (MCR(21) = 0), bits 15 and 22 of the MCR act as control bits for selecting the DRAM type as specified in the following table. The default setting is Fast Page Mode DRAM.

  • Page 126: Sdram Control Register Sdcr

    (identical) bank of SDRAM devices, setting CS1Enable to 0 enables the generation of the chip select signal CS1# for this second bank of SDRAM devices. This feature is not supported on the , the CS1Enable bit must be set to 1 in this case. E1-16XS...

  • Page 127: Cs1Select

    One 64 Mbit SDRAM device (4 banks × 1M × 16 bits) is connected to the to form E1-16XS a 16 bit wide 8 Mbyte SDRAM memory space. Column addresses are SDRAM pins A0 to A7, row address pins are SDRAM pins A0 to A11. There are two bank address pins BA0 and BA1.

  • Page 128: Input Status Register Isr

    Page 6-18 Bus Interface 6.6. Input Status Register ISR Global register G25 is the read-only input status register ISR. The ISR reflects the input levels at the pins IO1..IO3 as well as the input levels at the four interrupt pins INT1..INT4 and contains the EventFlag, the EqualFlag, the WatchdogFlag and the ClockOnFlag.

  • Page 129: Function Control Register Fcr

    E1-32XS User’s manual Page 6-19 6.7. Function Control Register FCR Global register G26 is the write-only function control register FCR. The FCR controls the polarity and function of the I/O pins IO1..IO3 and the interrupt pins INT1..INT4, the timer interrupt mask and priority, the bus lock, the CLKOUT pin and the Extended Overflow exception.
  • Page 130 Page 6-20 Bus Interface Bits Name Description BusLock DMA Access: 1 = Non-Locked 0 = Locked out EOVDisable Extended Overflow Exception: 1 = Disabled 0 = Enabled 15..14 reserved 13..12 IO3Control IO3 Control State: 11 = IO3Standard Mode 10 = Watchdog Mode 01 = IO3Timing Mode 00 = IO3TimerInterrupt Mode CLKOUTControl2...

  • Page 131: Clkoutcontrol And Clkoutcontrol2

    E1-32XS User’s manual Page 6-21 6.7.1. CLKOUTControl and CLKOUTControl2 The CLKOUTControl and CLKOUTControl2 fields control the function of the CLKOUT pin according to the following table: FCR(11) FCR(19) FCR(18) CLKOUT function Output reflects CLKOUTPolarity Processor clock Processor clock / 2 Processor clock / 4 Processor clock / 6 Processor clock / 8...

  • Page 132: On Io3Direction = Input

    Page 6-22 Bus Interface 6.9.3.1. On IO3Direction = Input: When input signal IO3Level = IO3Polarity, the EventFlag ISR(8) is set and the current contents of the TR(15..0) is copied to the WCR. Thus, the time of the event indicated by the 16 low-order bits of the TR is captured in the WCR.

  • Page 133: Bus Signals

    6.10.1. Bus Signals for the E1-32XS Processor The following table is an overview of the bus signals of the microproc- hyperstone E1-32XS essor. For a detailed description of the function of the bus signals refer to section 6.10.3. Bus Signal Description.

  • Page 134: Bus Signals For The E1-16Xs Processor

    Programmable Input / Output Boot bus width selection input for MEM3 BOOTB RESET# Reset Input Power Supply Voltage, processor core VCCint GNDint Ground, processor core Power Supply Voltage, processor I/O Ground, processor I/O Total: Table 6.13: Bus Signals for the E1-16XS Processor...

  • Page 135: Bus Signal Description

    E1-32XS User’s manual Page 6-25 6.10.3. Bus Signal Description The following section describes the bus signals for both the hyperstone E1-32XS microprocessor in detail. 16XS In the following signal description, the signal states are defined as I = input, O = output and Z = three-state (inactive).
  • Page 136 , DP0, DP1, DP2 and DP3 correspond E1-32XS to D31..D24, D23..D16, D15..D8 and D7..D0 respectively. With , DP0 and DP1 correspond to D15..D8 and D7..D0 E1-16XS respectively. At a write access, all data parity signals are activated during the address setup, write and bus hold cycles.
  • Page 137 D31..D24, D23..D16, D15..D8 and D7..D0 respectively. With the , CAS0# and CAS1# correspond to the column E1-16XS address enable signals for D15..D8 and D7..D0 respectively. If the SDRAM interface is used, these signals are redefined as SDRAM control signals.
  • Page 138 Page 6-28 Bus Interface States Names Output Enable for SRAM, EPROM, EDO DRAM, and SDRAM. OE# is active low on a SRAM, EPROM or DRAM (except Fast Page Mode) read access. IORD# I/O Read Strobe, optionally I/O data strobe. The use of IORD# is specified in the I/O address.
  • Page 139 E1-32XS User’s manual Page 6-29 States Names INT1..INT4 Interrupt Request. A signal of a specified level on any of the INT1..INT4 interrupt request pins causes an interrupt exception when the interrupt lock flag L is zero and the corresponding INTxMask bit in FCR is not set. The INTxPolarity bits in FCR specify the level of the INTx signals: INTxPolarity = 1 causes an interrupt on a high input signal level, INTxPolarity = 0 causes an interrupt on a low input signal level.

  • Page 140: Bus Cycles

    Page 6-30 Bus Interface 6.11. Bus Cycles 6.11.1. SRAM and ROM Accesses 6.11.1.1. SRAM and ROM Single-Cycle Read Access Clock Chip Select Address Bus addr. 1 addr. 2 addr. 3 addr. 4 addr. 5 WE0#..WE3# data 1 data 2 data 3 data 4 data 5 Data Bus...

  • Page 141: Sram And Rom Multi-Cycle Read Access

    E1-32XS User’s manual Page 6-31 6.11.1.3. SRAM and ROM Multi-Cycle Read Access Clock Chip Select Address Bus WE0#..WE3# Data Bus Address Access time Bus hold setup time 2..16 cycles time 0..3 cycles 0..7 cycles Figure 6.4: SRAM and ROM Multi-Cycle Read Access 6.11.1.4.

  • Page 142: Mem2 Read Access With Wait Pin

    Page 6-32 Bus Interface 6.11.2. MEM2 Read Access with WAIT Pin INT3Polarity = Inverted, address setup time = 0 cycles, bus hold time = 0 cycles Clock Chip Select Address Bus WE0#..WE3# WAIT Data Bus Access time next access (minimum 4 cycles) or bus hold time if specified Figure 6.6: MEM2 Read Access with WAIT Pin...

  • Page 143: I/O Read Access

    E1-32XS User’s manual Page 6-33 6.11.3. I/O Read Access Clock Chip Select Address Bus IORD# Data Bus Address Access time Bus hold setup time 2..16 cycles time 0..6 cycles 0..6 cycles Figure 6.7: I/O Read Access...

  • Page 144: I/O Read Access With Wait Pin

    Page 6-34 Bus Interface 6.11.4. I/O Read Access with WAIT Pin address setup time = 0 cycles, bus hold time = 0 cycles, INT3Polarity = Inverted Clock Chip Select Address Bus WAIT IORD# Data Bus Access time next access (minimum 4 cycles) or bus hold time if specified Figure 6.8: I/O Read Access with WAIT Pin...

  • Page 145: I/O Write Access

    E1-32XS User’s manual Page 6-35 6.11.5. I/O Write Access Clock Chip Select Address Bus IORD# IOWR# Data Bus Address Access time Bus hold setup time 2..16 cycles time 0..6 cycles 1..7 cycles Figure 6.9: I/O Write Access Note: If IORD# is used as I/O data strobe, IORD# instead of IOWR# is activated low.

  • Page 146: Dram

    Page 6-36 Bus Interface 6.11.6. DRAM 6.11.6.1. Fast Page Mode DRAM Access Clock Address Bus valid high order bits Address Bus undefined row address col. addr. col. addr. low order bits RAS# CAS0#..CAS3# RAS precharge time RAS to CAS delay time CAS access CAS access 1..6 cycles...

  • Page 147: Edo Dram Single-Cycle Access

    E1-32XS User’s manual Page 6-37 6.11.6.2. EDO DRAM Single-Cycle Access Clock Address Bus valid high order bits Address Bus row address col. addr. col. addr. undefined low order bits RAS# CAS0#..CAS3# RAS precharge time RAS to CAS delay time CAS access CAS access 1..6 cycles 1..4 cycles...

  • Page 148: Edo Dram Multi-Cycle Access

    Page 6-38 Bus Interface 6.11.6.3. EDO DRAM Multi-Cycle Access Clock Address Bus valid high order bits Address Bus row addr. column address column address undefined low order bits RAS# CAS0#..CAS3# RAS to CAS CAS access time CAS access time precharge time delay time 1..6 cycles 1..6 cycles...

  • Page 149: Fast Page Mode Or Edo Dram Refresh

    E1-32XS User’s manual Page 6-39 6.11.6.4. Fast Page Mode or EDO DRAM Refresh Clock undefined Address Bus RAS# CAS# RAS precharge time RAS to CAS delay time CAS access 1..6 cycles 1..4 cycles time 1..6 cycles Figure 6.13: DRAM Refresh Note: The type of refresh that is performed is CAS Before RAS.

  • Page 150: Sdram Access

    Page 6-40 Bus Interface 6.11.6.5. SDRAM Access CPU CLK (internal) SDCLK precharge activate read/write read/write Control Figure 6.14: SDRAM Command Execution Note: SDRAM executes precharge, activate, and then read/write commands In this example BCR: RAS precharge 4 cycles, RAS-to-CAS delay 4 cycles, CAS access 2 cycles SDCR: SDCLKSelect = 1...

  • Page 151: Dc Characteristics

    E1-32XS User’s manual Page 6-41 6.12. DC Characteristics 6.12.1. Absolute Maximum Ratings Case temperature T under Bias: 0°C to +85°C extended temperature range on request Storage Temperature: -65°C to +150°C Voltage on any Pin with respect to ground: -0.5V to + 3.8V 6.12.2.

  • Page 152: Ac Characteristics

    Page 6-42 Bus Interface 6.13. AC Characteristics 6.13.1. Processor Clock and CLKIN The maximum internal processor clock frequency of the hyperstone E1-32XS E1-16XS is 115 MHz. The internal PLL of the multiplies the clock at the input hyperstone E1-32XS E1-16XS pin CLKIN by ½, 1, 2, 4 or 8.

  • Page 153: Mechanical Data

    7.1. hyperstone E1-32XS, 144-Pin LQFP Package 7.1.1. Pin Configuration - View from Top Side INT1 INT2 INT3/WAIT INT4 RQST CLKOUT BOOTW hyperstone E1-32XS XTAL2 XTAL1/CLKIN CAS1# RAS# CAS2# CAS3# CS1# CS2# CS3# IORD# IOWR# WE2# WE3# Figure 7.1: hyperstone E1-32XS, 144-Pin LQFP Package...

  • Page 154: Pin Cross Reference By Pin Name

    Page 7-2 Mechanical Data 7.1.2. Pin Cross Reference by Pin Name Signal Location Signal Location Signal Location Signal Location CS3# IOWR# RAS# RESET# RQST GNDint GNDint GNDint VCCint GNDint VCCint GNDint VCCint GNDint VCCint BOOTB GRANT# VCCint BOOTW INT1 VCCint CAS0# INT2 CAS1#...

  • Page 155: Pin Cross Reference By Location

    E1-32XS User’s manual Page 7-3 7.1.3. Pin Cross Reference by Location Location Signal Location Signal Location Signal Location Signal BOOTB WE3# WE2# GRANT# IORD# RESET# GNDint GNDint VCCint VCCint CAS3# CAS2# CAS1# XTAL1/CLKIN XTAL2 GNDint GNDint VCCint VCCint WE0# WE1# BOOTW CAS0# CLKOUT...

  • Page 156: Hyperstone E1-16Xs, 100-Pin Lqfp Package

    7.2. hyperstone E1-16XS, 100-Pin LQFP Package 7.2.1. Pin Configuration - View from Top Side INT1 INT2 INT3/WAIT INT4 RQST CLKOUT hyperstone E1-16XS XTAL2 XTAL1/CLKIN RAS# CAS0# CAS1# CS1# CS2# CS3# IORD# IOWR# WE0# WE1# Figure 7.2: hyperstone E1-16XS, 100-Pin LQFP Package...

  • Page 157: Pin Cross Reference By Pin Name

    E1-32XS User’s manual Page 7-5 7.2.2. Pin Cross Reference by Pin Name Signal Location Signal Location Signal Location Signal Location CAS1# IOWR# CLKOUT CS1# RAS# CS2# RESET# CS3# RQST GNDint GNDint GNDint GNDint GNDint VCCint GNDint VCCint GRANT# VCCint INT1 VCCint INT2 VCCint...

  • Page 158: Pin Cross Reference By Location

    Page 7-6 Mechanical Data 7.2.3. Pin Cross Reference by Location Signal Location Signal Location Signal Location Signal Location BOOTB WE1# WE0# GRANT# IORD# RESET# GNDint GNDint VCCint VCCint CAS1# CAS0# GNDint XTAL1/CLKIN GNDint VCCint XTAL2 VCCint CLKOUT RAS# GNDint GNDint VCCint RQST VCCint...

  • Page 159: Hyperstone E1-32Xsb, 144-Pin Tfbga Package

    GNDint VCCint GNDint VCCint GNDint XTAL2 XTAL1/ VCCint GNDint VCCint GNDint VCCint GNDint CAS1# CAS2# CLKIN CS1# CAS0# CAS3# IORD# RAS# CS2# BOOTB WE1# WE3# WE2# CS3# IOWR# WE0# 9 10 11 12 Figure 7.3: hyperstone E1-32XSB, 144-Pin TFBGA Package...

  • Page 160: Pin Cross Reference By Pin Name

    Page 7-8 Mechanical Data 7.3.2. Pin Cross Reference by Pin Name Signal Location Signal Location Signal Location Signal Location CS3# IOWR# RAS# RESET# RQST GNDint GNDint GNDint VCCint GNDint VCCint GNDint VCCint GNDint VCCint BOOTB GRANT# VCCint BOOTW INT1 VCCint CAS0# INT2 CAS1#...

  • Page 161: Pin Cross Rreference By Location

    E1-32XS User’s manual Page 7-9 7.3.3. Pin Cross Rreference by Location Location Signal Location Signal Location Signal Location Signal CS1# VCCint GNDint VCCint GNDint VCCint GNDint CAS0# RESET# CAS3# INT3/WAIT RQST IORD# RAS# CS2# BOOTB WE1# INT1 INT4 WE3# CLKOUT XTAL2 WE2# CS3#...

  • Page 162: Hyperstone E1-16Xsb, 100-Pin Tfbga Package

    GNDint GNDint INT2 WAIT VCCint VCCint VCCint GNDint INT1 INT4 RQST XTAL1/ CS2# RAS# CAS0# XTAL2 CLKIN CS1# CS3# VCCint VCCint VCCint WE1# CAS1# IOWR# BOOTB GNDint GNDint GNDint WE0# IORD# 9 10 Figure 7.4: hyperstone E1-16XSB, 100-Pin TFBGA Package...

  • Page 163: Pin Cross Reference By Pin Name

    E1-32XS User’s manual Page 7-11 7.4.2. Pin Cross Reference by Pin Name Signal Location Signal Location Signal Location Signal Location CAS1# IOWR# CLKOUT CS1# RAS# CS2# RESET# CS3# RQST GNDint GNDint GNDint GNDint GNDint VCCint GNDint VCCint GRANT# VCCint INT1 VCCint INT2 VCCint...

  • Page 164: Pin Cross Rreference By Location

    Page 7-12 Mechanical Data 7.4.3. Pin Cross Rreference by Location Location Signal Location Signal Location Signal Location Signal VCCint VCCint VCCint GNDint INT1 WE1# INT4 CAS1# IOWR# BOOTB RESET# GNDint GRANT# GNDint CS2# GNDint CLKOUT RAS# RQST WE0# IORD# GNDint GNDint XTAL1/CLKIN K3 INT2...

  • Page 165: Package Dimensions

    E1-32XS User’s manual Page 7-13 7.5. Package Dimensions 7.5.1. Package Dimensions LQFP Index Figure 7.5: hyperstone E1-32XS, E1-16XS LQFP Package Outline Symbol Term Definition Standoff height Height from ground plane to bottom edge of package Package height Height of package itself E, D Overall length &...
  • Page 166 (0.018) (0.024) (0.030) 0.50 (0.0197) 0.17 0.22 0.27 (0.007) (0.009) (0.011) θ 0° 7° (0°) (7°) hyperstone E1-16XS, 100-Pin LQFP Package Symbol Dimensions in Millimeters Dimensions in Inches Min. Nom. Max. Min. Nom. 0.05 0.10 0.15 (0.002) (0.004) (0.006) 1.35 1.40...
  • Page 167 E1-32XS User’s manual Page 7-15 7.5.2. Package Dimensions TFBGA bottom view: side view: Figure 7.6: hyperstone E1-32XSB, E1-16XSB TFBGA Package Outline...
  • Page 168 Page 7-16 Mechanical Data hyperstone E1-32XSB, 144-Pin TFBGA Package Dimensions in mm Dimensions in Inch Symbol 11.90 12.00 12.10 0.469 0.472 0.476 8.80 0.346 0.80 0.031 11.90 12.00 12.10 0.469 0.472 0.476 8.80 0.346 0.80 0.031 4.40 0.173 4.40 0.173 1.40...

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