HopeRF RF 65 Manuals

Manuals and User Guides for HopeRF RF 65. We have 1 HopeRF RF 65 manual available for free PDF download: Manual

HopeRF RF 65 Manual

HopeRF RF 65 Manual (72 pages)

Low Power Integrated UHF Receiver With -120dBm High Sensitivity

Brand: HopeRF | Category: Receiver | Size: 2 MB

Table of Contents

Table of Contents
2
1 General Description

8
- Simplified Block Diagram
  8
- Pin and Marking Diagram
  9
  - Pin Description
    10
2 Electrical Characteristics

11
- ESD Notice
  11
  - Absolute Maximum Ratings
    11
- Operating Range
  11
  - Chip Specification
    12
  - Power Consumption
    12
  - Frequency Synthesis
    12
  - Receiver
    13
  - Digital Specification
    14
3 Chip Description

15
- Power Supply Strategy
  15
- Low Battery Detector
  15
- Frequency Synthesis
  15
  - Reference Oscillator
    15
  - CLKOUT Output
    16
  - PLL Architecture
    16
  - Lock Time
    17
  - Lock Detect Indicator
    17
  - Receiver Description
    17
  - Block Diagram
    17
  - LNA - Single to Differential Buffer
    18
  - Automatic Gain Control
    18
  - Figure 6. AGC Thresholds Settings
    19
  - Continuous-Time DAGC
    20
  - Quadrature Mixer - Adcs - Decimators
    20
  - Channel Filter
    20
  - DC Cancellation
    21
  - Complex Filter - OOK
    22
  - Rssi
    22
  - Cordic
    22
  - Bit Rate Setting
    22
  - FSK Demodulator
    23
  - OOK Demodulator
    24
  - Figure 9. Floor Threshold Optimization
    25
  - Bit Synchronizer
    26
  - Frequency Error Indicator
    26
  - Automatic Frequency Correction
    27
  - Optimized Setup for Low Modulation Index Systems
    28
    
    Temperature Sensor
    29
    
    Timeout Function
    29
4 Operating Modes

30
- Basic Modes
  30
- Automatic Sequencer and Wake-Up Times
  30
  - Receiver Startup Time
    30
  - Figure 14. Rx Startup - no AGC, no AFC
    31
  - Rx Start Procedure
    32
  - Optimized Frequency Hopping Sequences
    32
  - Listen Mode
    33
    
    Timings
    33
    
    Criteria
    34
    
    End of Cycle Actions
    34
    
    RC Timer Accuracy
    35
  - Automodes
    36
5 Data Processing

37
- Overview
  37
  - Block Diagram
    37
  - Data Operation Modes
    37
  - Control Block Description
    38
    
    SPI Interface
    38
    
    Fifo
    39
    
    Sync Word Recognition
    40
    
    Packet Handler
    41
    
    Control
    41
  - Digital IO Pins Mapping
    42
    
    DIO Pins Mapping in Continuous Mode
    42
    
    DIO Pins Mapping in Packet Mode
    42
  - Continuous Mode
    43
    
    General Description
    43
    
    Rx Processing
    43
  - Packet Mode
    44
    
    General Description
    44
    
    Packet Format
    44
    
    Figure 28. Fixed Length Packet Format
    45
    
    Figure 29. Variable Length Packet Format
    46
    
    Processing (Without AES)
    47
    
    Aes
    47
    
    Handling Large Packets
    48
    
    Packet Filtering
    48
    
    DC-Free Data Mechanisms
    50
    
    Figure 33. Data De-Whitening
    51
6 Configuration and Status Registers

52
- General Description
  52
- Common Configuration Registers
  55
- Receiver Registers
  58
- IRQ and Pin Mapping Registers
  60
- Packet Engine Registers
  62
- Temperature Sensor Registers
  65
- Test Registers
  65
7 Application Information

66
- Crystal Resonator Specification
  66
- Reset of the Chip
  66
  - Por
    66
  - Manual Reset
    67
- Reference Design
  67
8 Packaging Information

69
- Package Outline Drawing
  69
- Thermal Impedance
  69
9 Chip Revisions

70
- RC Oscillator Calibration
  70
- Listen Mode
  70
  - Resolutions
    70
  - Exiting Listen Mode
    71
- OOK Floor Threshold Default Setting
  71
- AFC Control
  71
  - Afcautoclearon
    71
  - Afclowbetaon and Lowbetaafcoffset
    71
- Continuousdagc
  71

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