HopeRF RF 65 Manual

Low power integrated uhf receiver with -120dbm high sensitivity
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Low Power Integrated UHF Receiver With -120dBm High Sensitivity
GENERAL DESCRIPTION
The RF65 is a highly integrated RF receiver capable of
operation over a wide frequency range, including the
3 1 5 , 433,868 and 915 MHz license-free ISM (Industry
Scientific and Medical) frequency bands. Its highly
integrated architecture allows for a minimum of external
components whilst maintaining maximum design flexibility.
All major RF communication parameters are programmable
and most of them can be dynamically set. The RF65 offers
the unique advantage of programmable narrow-band and
wide-band communication modes without the need to
modify external components. The RF65 is optimized for
low power consumption while offering high sensitivity and
channelized operation. TrueRF™ technology enables a
lowcost external component count (elimination of the SAW
filter) whilst still satisfying ETSI and FCC regulations.
APPLICATIONS
Automated Meter Reading
Wireless Sensor Networks
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
MARKETS
Europe: EN 300-220-1
North America: FCC Part 15.247, 15.249,
15.231
Narrow Korean and Japanese bands
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com
VBAT1&2
VR_ANA
VR_DIG
Power Distribution System
LNA
Single to
Mixers
Differential
RFIN
Division by
2, 4 or 6
Tank
Inductor
Frac-N PLL
Loop
NC
Filter
Synthesizer
NC
XO
NC
32 MHz
XTAL
RC
Oscillator
Σ/Δ
Modulators
RESET
SPI
RSSI
AFC
GND
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GND
KEY PRODUCT FEATURES
High Sensitivity: down to -120 dBm at 1.2 kbps
High Selectivity: 16-tap FIR Channel Filter
Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Low current: Rx = 16 mA, 100nA register retention
Constant RF performance over voltage range of chip
FSK Bit rates up to 300 kb/s
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK and OOK demodulation
Built-in Bit Synchronizer performing Clock Recovery
Incoming Sync Word Recognition
115 dB+ Dynamic Range RSSI
Automatic RF Sense with ultra-fast AFC
Packet engine with CRC, AES-128 encryption and 66-
byte FIFO
Built-in temperature sensor and Low Battery indicator
ORDERING INFORMATION
Part Number
RF65
QFN 28 Package - Operating Range [-40;+85° C]
Pb-free, Halogen free, RoHS/WEEE compliant product
RF65
Delivery
MOQ / Multiple
Tape & Reel
3000 pieces
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Summary of Contents for HopeRF RF 65

  • Page 1 Europe: EN 300-220-1  QFN 28 Package - Operating Range [-40;+85° C]  North America: FCC Part 15.247, 15.249,  Pb-free, Halogen free, RoHS/WEEE compliant product 15.231  Narrow Korean and Japanese bands Page 1 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 2: Table Of Contents

    3.4.12. FSK Demodulator ............................23 3.4.13. OOK Demodulator ..........................24 3.4.14. Bit Synchronizer ............................ 26 3.4.15. Frequency Error Indicator........................26 3.4.16. Automatic Frequency Correction ......................27 3.4.17. Optimized Setup for Low Modulation Index Systems ................28 Page 2 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 3 5.5.6. Packet Filtering............................48 5.5.7. DC-Free Data Mechanisms ........................50 Configuration and Status Registers ........................52 6.1. General Description ............................52 6.2. Common Configuration Registers ......................... 55 6.3. Receiver Registers ............................58 Page 3 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 4 9.2.2. Exiting Listen Mode ..........................71 9.3. OOK Floor Threshold Default Setting ......................71 9.4. AFC Control ..............................71 9.4.1. AfcAutoClearOn ............................71 9.4.2. AfcLowBetaOn and LowBetaAfcOffset..................... 71 9.5. ContinuousDagc............................71 Page 4 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 5 Figure 35. Manual Reset Timing Diagram ........................67 Figure 36. Application Schematic ..........................67 Figure 37. Package Outline Drawing ........................... 68 Figure 38. Listen Mode Resolutions, V2a ........................69 Figure 39. Listen Mode Resolution, V2b ........................69 Page 5 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 6 Table 24. Temperature Sensor Registers ........................65 Table 25. Test Registers .............................. 65 Table 26. Crystal Specification ............................. 66 Table 27. Chip Identification ............................70 Table 28. Revision History ............................72 Page 6 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 7 Shift Register IDentificator Stby Standby Intermediate Frequency Transmitter Interrupt ReQuest Microcontroller International Telecommunication Union Voltage Controlled Oscillator LFSR Linear Feedback Shift Register Crystal Oscillator Low Noise Amplifier eXclusive OR Local Oscillator Page 7 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 8: General Description

    2, 4 or 6 DIO0 Tank DIO1 Inductor DIO2 Frac-N PLL Loop DIO3 Filter Synthesizer DIO4 DIO5 32 MHz XTAL Control Blocks Frequency Synthesis Primarily Analog Receiver Blocks Primarily Digital Figure 1. Block Diagram Page 8 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 9: Pin And Marking Diagram

    The following diagram shows the pin arrangement of the QFN package, top view. Figure 2. Pin Diagram RF65 Figure 3. Marking Diagram Notes yyww refers to the date code xxxxxx refers to the lot number Page 9 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 10: Pin Description

    SPI Chip select input Connect to GND or Do not connect Do not connect Ground RFIN RF input Ground Do not connect Do not connect Connect to GND or Do not connect Page 10 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 11: Electrical Characteristics

    ° C RF Input Level 2.3. Operating Range Table 3 Operating Range Symbol Description Unit VDDop Supply voltage Operational temperature range ° C Clop Load capacitance on digital ports RF Input Level Page 11 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 12: Chip Specification

    20 MHz step 25 MHz step FSTEP Frequency synthesizer step 61.0 FSTEP = FXOSC/2 RC Oscillator frequency After calibration 62.5 Bit rate, FSK Programmable kbps Bit rate, OOK Programmable 32.768 kbps Page 12 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 13: Receiver

    = 200 kHz, BR = 100 kb/s TS_RE_AGC Receiver wake-up time, from PLL RxBw = 10 kHz, BR = 4.8 kb/s &AFC lock state, AGC and AFC enabled RxBw = 200 kHz, BR = 100 kb/s Page 13 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 14: Digital Specification

    NSS falling edge to SCK rising nsetup edge NSS hold time from SCK falling edge to NSS rising nhold edge, normal mode NSS high time between SPI nhigh accesses T_DATA DATA hold and setup time Page 14 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 15: Chip Description

    The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an appropriate value of decoupling capacitor, C TCXO 32 MHz Figure 4. TCXO Connection Page 15 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 16: Clkout Output

    Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. Page 16 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 17: Lock Time

    Phase Output Demodulator RFIN Module RSSI Output Demodulator Bypassed in FSK Local Oscillator Figure 5. Receiver Block Diagram The following sections give a brief description of each of the receiver blocks. Page 17 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 18: Lna - Single To Differential Buffer

    Notes - the AGC procedure must be performed while receiving preamble in FSK mode - in OOK mode, the AGC will give better results if performed while receiving a constant “1” sequence Page 18 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 19: Figure 6. Agc Thresholds Settings

    RssiThreshold accordingly 3.4.3.2. AGC Reference The AGC reference level is automatically computed in the RF65, according to: AGC Reference [dBm] = -174 + NF + DemodSnr +10.log(2*RxBw) + FadingMargin [dBm] Page 19 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 20: Continuous-Time Dagc

    Bit Rate cannot be set at a higher value than 2 times the single-side receiver bandwidth (BitRate < 2 x RxBw) The single-side channel filter bandwidth RxBw is controlled by the parameters RxBwMant and RxBwExp in RegRxBw: Page 20 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 21: Dc Cancellation

    DC cancellation is required in zero-IF architecture receivers to remove any DC offset generated through self-reception. It is built-in the RF65 and its adjustable cutoff frequency fc is controlled in RegRxBw: Page 21 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 22: Complex Filter - Ook

     Amplitude output: used by the RSSI block, for FSK demodulation, AGC and automatic gain calibration purposes. Q(t) Real-time Magnitude Real-time Phase I(t) Figure 7. Cordic Extraction 3.4.11. Bit Rate Setting Page 22 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 23: Fsk Demodulator

    0.5 ≤ β The output of the FSK demodulator can be fed to the Bit Synchronizer (described in section 3.4.14), to provide the companion processor with a synchronous data stream in Continuous mode. Page 23 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 24: Ook Demodulator

    OokFixedThresh determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals (i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly. Page 24 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 25: Figure 9. Floor Threshold Optimization

    Fixed Threshold: The value is selected through OokFixedThresh  Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with DC-free encoded data. Page 25 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 26: Bit Synchronizer

    This function provides information about the frequency error of the local oscillator (LO) compared with the carrier frequency of a modulated signal at the input of the receiver. When the FEI block is launched, the frequency error is measured and the Page 26 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 27: Automatic Frequency Correction

    . The AFC can be launched:  Each time the receiver is enabled, if AfcAutoOn = 1  Upon user request, by setting bit AfcStart in RegAfcFei, if AfcAutoOn = 0 Page 27 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 28: Optimized Setup For Low Modulation Index Systems

    When the optimized AFC routine is enabled, the receiver startup time can be computed as follows (refer to section 4.2.1): TS_RE_AGC&AFC (optimized AFC) = Tana + 4.Tcf + 4.Tdcc + 3.Trssi + 2.Tafc + 2.Tpllafc Page 28 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 29: Temperature Sensor

    Timeout interrupt is generated TimeoutRssiThresh x 8 x Tbit after RssiThreshold flag has been raised. This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power mode. Page 29 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 30: Operating Modes

    It is highly recommended to use the built-in sequencer of the RF65, to optimize the delays when setting the chip in receive mode. It guarantees the shortest startup times, hence the lowest possible energy usage, for battery operated systems. The startup times of the receiver can be calculated from the following: Page 30 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 31: Figure 14. Rx Startup - No Agc, No Afc

    Figure 16. Rx Startup - AGC and AFC The different timings shown above are as follows: Note The above timings represent maximum settling times, and shorter settling times may be observed in real cases Page 31 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 32: Rx Start Procedure

    (3) Turn the receiver back to Rx mode (4) Respect the Rx start procedure, described in section 4.2.4 Note the above sequence assumes that the sequencer is turned on (SequencerOff=0 in RegOpMode). Page 32 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 33: Listen Mode

    Table 13 Range of Durations in Listen Mode ListenResolX Min duration Max duration ( ListenCoef = 1 ) ( ListenCoef = 255 ) 64 us 16 ms 4.1 ms 1.04 s 0.26 s 67 s Page 33 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 34: Criteria

    Mode. Listen mode stops and must be disabled. Chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then resumes in Idle state. FIFO content is lost at next Rx wakeup. Page 34 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 35: Rc Timer Accuracy

    For applications enduring large temperature variations, and for which the power supply is never removed, RC calibration can be performed upon user request. RcCalStart in RegOsc1 can be used to trigger this calibration, and the flag RcCalDone will be set automatically when the calibration is over. Page 35 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 36: Automodes

    Some typical examples of AutoModes usage are described below :  Automatic reception (AutoRx) : Mode = Rx, IntermediateMode = Sleep, EnterCondition = CrcOk, ExitCondition = falling edge of FifoNotEmpty  Page 36 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 37: Data Processing

    Depending on the optional features activated (CRC, AES, etc) the maximum payload length is limited to FIFO size, 255 bytes or unlimited. Each of these data operation modes is described fully in the following sections. Page 37 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 38: Control Block Description

    In FIFO mode, if the address was the FIFO address then the bytes will be read at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented at each new byte received. Page 38 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 39: Fifo

    1, note that the FIFO will also be cleared.  FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below. Page 39 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 40: Sync Word Recognition

    The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync word and sets SyncAddressMatch when a match is detected. This is illustrated in Figure 24 below. Page 40 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 41: Packet Handler

    The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5. 5.2.5. Control The control block configures and controls the full chip's behavior according to the settings programmed in the configuration registers. Page 41 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 42: Digital Io Pins Mapping

    Data FifoFull PayloadReady LowBat RxReady SyncAddress LowBat FifoNotEmpty SyncAddress ModeReady PllLock PllLock AutoMode Timeout Rssi Note Received Data is only shown on the Data signal between RxReady and PayloadReady’s rising edges Page 42 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 43: Continuous Mode

    Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode). Page 43 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 44: Packet Mode

    In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF overhead (no length byte field is required). All nodes should be programmed with the same packet length value. Page 44 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 45: Figure 28. Fixed Length Packet Format

    Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2 bytes, i.e. length + address or message byte. An illustration of a variable length packet is shown below. It contains the following fields: Page 45 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 46: Figure 29. Variable Length Packet Format

    Payload Fields processed and removed in Rx Message part of the payload Optional User provided fields which are part of the payload Figure 30. Unlimited Length Packet Format Page 46 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 47: Processing (Without Aes)

    The decryption process takes approximately 7.0 us per 16-byte block. Thus for a maximum of 4 blocks (i.e. 64 bytes) it can take up to 28 us for completing the cryptographic operations. Page 47 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 48: Handling Large Packets

    Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated. When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted. Note Sync Word values containing 0x00 byte(s) are forbidden Page 48 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 49 FIFO. The CRC is based on the CCITT polynomial as shown below. This implementation also detects errors due to leading and trailing zeros. Page 49 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 50: Dc-Free Data Mechanisms

    The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved. Page 50 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 51: Figure 33. Data De-Whitening

    XORing it with a random sequence generated in a 9-bit LFSR, shown in Figure 33. Payload de-whitening is thus made transparent for the user, who still retrieves NRZ data from the FIFO. De-whitened Data Received Data Figure 33. Data De-Whitening Page 51 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 52: Configuration And Status Registers

    Reserved12 0x09 0x13 Reserved13 0x1A 0x14 Reserved14 0x40 0x15 Reserved15 0xB0 0x16 Reserved16 0x7B 0x17 Reserved17 0x9B 0x18 RegLna 0x08 0x88 LNA settings 0x19 RegRxBw 0x86 0x55 Channel Filter BW Control Page 52 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 53 Payload length setting 0x39 RegNodeAdrs 0x00 Node address 0x3A RegBroadcastAdrs 0x00 Broadcast address 0x3B RegAutoModes 0x00 Auto modes settings 0x3C RegFifoThresh 0x0F 0x8F Fifo threshold 0x3D RegPacketConfig2 0x02 Packet mode settings Page 53 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 54 - Reset values are automatically refreshed in the chip at Power On Reset - Default values are the HopeRF recommended register values, optimizing the device operation - Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 6 Page 54 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 55: Common Configuration Registers

    Default value: 4.8 kb/s 0x00 unused Reserved05 (0x05) 0x52 unused Reserved06 (0x06) Frf(23:16) 0xe4 MSB of the RF Local Oscillator RegFrfMsb (0x07) Frf(15:8) 0xc0 Middle byte of the RF Local Oscillator RegFrfMid (0x08) Page 55 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 56 4.3). 10→ chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then resumes in Idle state. FIFO content is lost at next Rx wakeup. 11→ Reserved unused Page 56 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 57 4.2.1) (0x0F) = ListenCoefRx ⋅ ListenResolRx ListenRx Version 0x23 Version code of the chip. Bits 7-4 give the full revision RegVersion number; bits 3-0 give the metal mask revision number. (0x10) Page 57 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 58: Receiver Registers

    Channel filter bandwidth control: FSK Mode: DccFreqAfc DccFreq parameter used during the AFC RegAfcBw (0x1A) RxBwMantAfc RxBwMant parameter used during the AFC RxBwExpAfc 011 * RxBwExp parameter used during the AFC Page 58 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 59 1→ RSSI sampling is finished, result available RssiStart Trigger a RSSI measurement when set. Always reads 0. RssiValue 0xFF Absolute value of the RSSI in dBm, 0.5dB steps. RegRssiValue RSSI = -RssiValue/2 [dBm] (0x24) Page 59 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 60: Irq And Pin Mapping Registers

    SyncAddressMatch r/rwc Set when Sync and Address (if enabled) are detected. Cleared when leaving Rx or FIFO is emptied. This bit is read only in Packet mode, rwc in Continuous mode Page 60 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 61 Rx mode if Rssi interrupt doesn‟t occur (0x2A) (i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxStart is disabled TimeoutRssiThresh 0x00 Timeout interrupt is generated TimeoutRssiThresh*16*T RegRxTimeout2 after Rssi interrupt if PayloadReady interrupt doesn‟t (0x2B) occur. 0x00: TimeoutRssiThresh is disabled Page 61 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 62: Packet Engine Registers

    Sync word. (0x35) Used if SyncOn is set and (SyncSize +1) >= 7. 7-0 SyncValue(7:0) 0x01 RegSyncValue8 byte of Sync word. (0x36) Used if SyncOn is set and (SyncSize +1) = 8. Page 62 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 63 111→ Rising edge of Timeout 1-0 IntermediateMode Intermediate mode: 00→ Sleep mode (SLEEP) 01→ Standby mode (STDBY) 10→ Receiver mode (RX) 11→ Reserved unused RegFifoThresh (0x3C) 6-0 FifoThreshold 0001111 Used to trigger FifoLevel interrupt. Page 63 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 64 (0x4A) 7-0 AesKey(23:16) 0x00 RegAesKey14 byte of cipher key (0x4B) 7-0 AesKey(15:8) 0x00 RegAesKey15 byte of cipher key (0x4C) 7-0 AesKey(7:0) 0x00 RegAesKey16 byte of cipher key (LSB byte) (0x4D) Page 64 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 65: Temperature Sensor Registers

    0x10→ Improved margin, use if AfcLowBetaOn=1 0x30→ Improved margin, use if AfcLowBetaOn=0 RegTestAfc 7-0 LowBetaAfcOffset 0x00 AFC offset set for low modulation index systems, used if (0x71) AfcLowBetaOn=1. Offset = LowBetaAfcOffset x 488 Hz Page 65 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 66: Application Information

    Chip is ready from 10 ms this point on Figure 34. POR Timing Diagram Please note that any CLKOUT activity can also be used to detect that the chip is ready. Page 66 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 67: Manual Reset

    Note In very cost-sensitive and/or size-constrained applications where it is acceptable to degrade the receiver sensitivity by approximately 2 dB, L1 and C1 can be omitted. ADVANCED COMMUNICATIONS & SENSING DATASHEET Page 67 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 68 5.6 pF 5.6 pF 12 pF 12 pF 6.8 nH 5.6 nH air core or multilayer Notes - (1) Inductor values may change when using multilayer type components Page 68 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 69: Packaging Information

    8.2. Thermal Impedance The thermal impedance of this package is: Theta ja = 23.8° C/W typ., calculated from a package in still air, on a 4-layer FR4 PCB, as per the Jedec standard. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com Page 69...
  • Page 70: Chip Revisions

    On the RF65 V2a, the Listen mode resolutions were identical for the Idle phase and the Rx phase. They are now independently configurable, adding flexibility in the setup of the Listen mode. Figure 38. Listen Mode Resolutions, V2a Figure 39. Listen Mode Resolution, V2b Page 70 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 71: Exiting Listen Mode

    Those two bits enable a functionality that was not available on the silicon version V2a. 9.5. ContinuousDagc This register enables a functionnality that is only available in the silicon version V2c. Page 71 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...
  • Page 72 NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY Fax: 86-755-82973550 OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS Email: sales@hoperf.com DOCUMENT. Website: http://www.hoperf.com http://www.hoperf.cn ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved. Page 72 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com...

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