FTDI FT51A Manuals

FTDI FT51A Manuals

Manuals and User Guides for FTDI FT51A. We have 1 FTDI FT51A manual available for free PDF download: Application Note

FTDI FT51A Application Note

FTDI FT51A Application Note (171 pages)

Brand: FTDI | Category: Control Unit | Size: 4 MB

Table of Contents

Table of Contents

2
- Introduction
  8
- Overview
  8
- Features
  8
- Scope
  8
- Hardware Reference
  10
- Table 2.1 FT51A SFR Map
  10
- Hardware Access
  11
- Registers Accessed by SFR
  11
- Registers Accessed through I/O Ports
  11
- Table 2.2 FT51A Peripherals
  11
- Register Descriptions
  12
- Table 2.3 Register Bit Type Definitions
  12
- Device Control Registers
  13
- Table 2.4 Device Control Register Addresses
  13
- Device_Control_Register
  14
- Table 2.5 Device Control Register
  14
- System_Clock_Divider
  15
- Table 2.6 System and Clock Divider Register
  15
- Top_Usb_Enable
  17
- Table 2.7 USB Control Register
  17
- Table 2.9 Interrupt Enable 0 Register
  18
- Peripheral_Ien0
  18
- Table 2.8 Interrupt Status 0 Register
  18
- Peripheral_Int0
  18
- Peripheral_Int1
  19
- Table 2.10 Interrupt Status 1 Register
  19
- Peripheral_Ien1
  20
- Pin_Config
  20
- Mtp_Control
  20
- Table 2.11 Interrupt Enable 1 Register
  20
- Table 2.12 Pin Config Register
  20
- Table 2.14 MTP Address (Lower) Register
  21
- Table 2.13 MTP Control Register
  21
- MTP_ADDR_L, MTP_ADDR_U and MTP_PROG_DATA
  21
- MTP_CRC_CTRL, MTP_CRC_RESULT_L and MTP_CRC_RESULT_U
  22
- Table 2.15 MTP Address (Upper) Register
  22
- Table 2.16 MTP Data Register
  22
- Table 2.17 MTP CRC Control Register
  22
- Table 2.18 MTP CRC Result (Lower) Register
  22
- Pin_Package_Config
  23
- Top_ Security_Level
  23
- Table 2.19 MTP CRC Result (Upper) Register
  23
- Table 2.20 Pin Package Type Register
  23
- Table 2.21 Top Level Security Register
  24
- SPI Master
  26
- Figure 2.1 SPI Master Schematic Diagram
  26
- Table 2.22 SPI Master Register Addresses
  27
- Spi_Master_Control
  28
- Spi_Master_Tx_Data
  28
- Spi_Master_Rx_Data
  28
- Table 2.23 SPI Master Control Register
  28
- Table 2.24 SPI Master Transmit Register
  28
- Table 2.25 SPI Master Receive Register
  28
- Spi_Master_Ien
  29
- Table 2.26 SPI Master Interrupt Enable Register
  29
- Spi_Master_Int
  30
- Table 2.27 SPI Master Interrupt Status Register
  30
- Spi_Master_Setup
  31
- Table 2.28 SPI Master Setup Register
  31
- Table 2.29 SPI Master Mode Numbers
  31
- Spi_Master_Clk_Div
  32
- Spi_Master_Data_Delay
  32
- Table 2.30 SPI Master Clock Divisor Register
  32
- Table 2.31 SPI Master Data Delay Register
  32
- Table 2.34 SPI Master Transfer Size (Upper) Register
  33
- Table 2.33 SPI Master Transfer Size (Lower) Register
  33
- Table 2.32 SPI Master Slave Select Setup
  33
- Spi_Master_Transfer_Size
  33
- Spi_Master_Ss_Setup
  33
- Spi_Master_Transfer_Pending
  34
- Use Cases
  34
- Table 2.35 SPI Master Transfer Pending Register
  34
- SPI Slave
  37
- Table 2.36 SPI Slave Register Addresses
  37
- Figure 2.2 SPI Slave Schematic Diagram
  37
- Table 2.38 SPI Slave Transmit Register
  38
- Table 2.37 SPI Slave Control Register
  38
- Spi_Slave_Tx_Data
  38
- Spi_Slave_Control
  38
- Spi_Slave_Rx_Data
  39
- Spi_Slave_Ien
  39
- Table 2.39 SPI Slave Receive Register
  39
- Table 2.40 SPI Slave Interrupt Enable Register
  39
- Spi_Slave_Int
  40
- Table 2.41 SPI Slave Interrupt Status Register
  40
- Spi_Slave_Setup
  41
- Table 2.42 SPI Slave Setup Register
  41
- Table 2.43 SPI Slave Mode Numbers
  41
- Figure 2.3 I C Master Schematic Diagram
  42
- Table 2.45 I 2 C Master Slave Address Register
  42
- Table 2.44 I 2 C Master Register Addresses
  42
- I2Cmsa
  42
- I2C Master
  42
- I2Cmcr
  43
- Table 2.46 I 2 C Master Control Register
  43
- I2Cmsr
  44
- I2Cmbuf
  44
- Table 2.47 I 2 C Master Status Register
  44
- Table 2.48 I 2 C Master Data Buffer Register
  44
- Table 2.49 I 2 C Master Timer Period Register
  45
- Use Case
  45
- I2Cmtp
  45
- I2C Slave
  48
- I2Csoa
  48
- Table 2.50 I 2 C Slave Register Addresses
  48
- Table 2.51 I 2 C Slave Address Register
  48
- Figure 2.4 I C Slave Schematic Diagram
  48
- I2Cscr
  49
- I2Cssr
  49
- Table 2.52 I 2 C Slave Control Register
  49
- Table 2.53 I C Slave Status Register
  50
- Table 2.54 I 2 C Slave Data Buffer Register
  50
- Use Case
  50
- I2Csbuf
  50
- Uart
  52
- Table 2.55 UART Register Addresses
  52
- Table 2.69 UART Flow Control Status Register
  52
- Table 2.56 UART Control Register
  53
- Table 2.58 UART Data Receive Register
  53
- Table 2.57 UART DMA Control Register
  53
- Table 2.59 UART Data Transmit Register
  53
- Uart_Tx_Data
  53
- Uart_Rx_Data
  53
- Uart_Dma_Ctrl
  53
- Uart_Control
  53
- Uart_Tx_Ien
  54
- Uart_Tx_Int
  54
- Table 2.60 UART Transmit Status Interrupt Enable Register
  54
- Table 2.61 UART Transmit Status Interrupt Register
  54
- Uart_Rx_Ien
  55
- Uart_Rx_Int
  55
- Table 2.62 UART Receive Status Interrupt Enable Register
  55
- Table 2.63 UART Receive Status Interrupt Register
  55
- Uart_Line_Ctrl
  56
- Table 2.64 UART Line Control Register
  56
- Table 2.67 UART Baud Rate 2 Register
  57
- Table 2.66 UART Baud Rate 1 Register
  57
- Table 2.65 UART Baud Rate 0 Register
  57
- Uart_Baud
  57
- UART Baud Rate Example
  58
- Uart_Flow_Ctrl
  58
- Table 2.68 UART Flow Control Register
  58
- Figure 2.5 UART Baud Rate Example Calculations
  58
- Uart_Flow_Stat
  59
- Gpios
  60
- Digital GPIO Pads
  60
- Table 2.70 GPIO DIO Digital Control Register Addresses
  60
- Analogue GPIO Pads
  61
- Table 2.71 GPIO DIO Digital Control Registers
  61
- Table 2.72 GPIO AIO Digital Control Register Addresses
  62
- Table 2.73 GPIO AIO Digital Control Registers
  63
- Iomux
  64
- Iomux_Control
  64
- Table 2.74 IOMUX Register Addresses
  64
- Table 2.75 IOMUX Control Register
  64
- Table 2.76 IOMUX Output Pad Select Register
  65
- Table 2.77 IOMUX Output Signal Select Register
  65
- Table 2.78 IOMUX Input Signal Select Register
  65
- Iomux_Input_Sig_Sel
  65
- Iomux_Output_Pad_Sel
  65
- Iomux_Output_Sig_Sel
  65
- Iomux_Input_Pad_Sel
  66
- IOMUX Pad Values
  66
- Table 2.79 IOMUX Input Pad Select Register
  66
- IOMUX Output Signal Mapping Values
  67
- Table 2.80 IOMUX Pad Values
  67
- IOMUX Input Signal Mapping Values
  69
- Table 2.81 IOMUX Output Signal Mapping Values
  69
- Use Cases
  70
- Table 2.82 IOMUX Input Signal Mapping Values
  70
- Table 2.84 Analogue IO Register Addresses
  71
- Table 2.85 Analogue IO Control Register
  71
- Aio_Control
  71
- Table 2.83 Available AIO Ports
  71
- Analogue IO Ports
  71
- Implementation
  72
- AIO Configuration
  72
- Figure 2.6 Pad Distribution
  72
- Table 2.86 AIO Mode Control Register Addresses
  73
- Table 2.87 AIO Mode Control Bits
  73
- Table 2.88 AIO Mode Control 0 Register
  73
- Table 2.89 AIO Mode Control 1 Register
  74
- Table 2.90 AIO Mode Control 2 Register
  74
- Table 2.91 AIO Mode Control 3 Register
  74
- AIO ADC Mode
  75
- Table 2.92 AIO ADC Register Addresses
  77
- Table 2.93 AIO ADC Sample Select 0 Register
  77
- Table 2.94 AIO ADC Sample Select 1 Register
  77
- AIO Interrupts
  78
- Table 2.95 AIO ADC Sample Result (Lower) Registers
  78
- Table 2.96 AIO ADC Sample Result (Upper) Registers
  78
- Table 2.97 AIO Interrupt Register Addresses
  78
- Table 2.98 AIO Interrupts 0-7 Register
  79
- Table 2.99 AIO Interrupts 8-15 Register
  79
- Table 2.101 AIO Interrupt Enables 8-15 Register
  80
- Table 2.100 AIO Interrupt Enables 0-7 Register
  80
- Global Mode
  80
- Table 2.102 AIO Global Mode Register Addresses
  81
- Table 2.103 AIO Global Mode Select 0-7 Register
  82
- Table 2.104 AIO Global Mode Select 8-15 Register
  82
- Differential Mode
  83
- Table 2.105. Recommended Global Port Selection
  83
- Table 2.106 AIO Differential Register Addresses
  83
- Settling Times
  84
- Table 2.107 AIO Differential Enable Register
  84
- Table 2.110 AIO Cell Sample and Hold Counter Upper Register
  85
- Table 2.109 AIO Cell Sample and Hold Counter Lower Register
  85
- Table 2.108 AIO Settling Times Register Addresses
  85
- Table 2.111 Clock Divider Register
  86
- ADC Programming Flow
  87
- USB Full Speed Device Controller
  88
- Endpoint Buffer Management
  88
- Table 2.112 USB Full Speed Device Controller Register Addresses
  88
- Table 2.113 Endpoint Configuration for EP0 and EP1
  88
- Table 2.114 Endpoint Configuration for EP2
  89
- Table 2.115 Example Buffer Configuration
  90
- Table 2.116 Endpoint Maximum Packet Size
  91
- Command Summary
  92
- Table 2.117 Default Command Set
  93
- Table 2.118 Enhanced Command Set
  96
- Initialization Commands
  97
- Table 2.119 Address Enable Register
  97
- Table 2.120 Endpoint Enable Register
  97
- Table 2.121 Configuration Register (Byte 1)
  98
- Table 2.122 Clock Division Factor Register (Byte 2)
  99
- Table 2.123 Endpoint Configuration Register
  99
- Data Flow Commands
  100
- Table 2.124 Interrupt Register Byte 1
  100
- Table 2.125 Interrupt Register Byte 2
  100
- Table 2.127 Interrupt Register Byte 4 (for Enhanced Mode)
  101
- Table 2.126 Interrupt Register Byte 3 (for Enhanced Mode)
  101
- Table 2.128 Endpoint Status Register
  102
- Table 2.129 Endpoint Last Transaction Status Register
  102
- Table 2.130 Transaction Error Code
  103
- Table 2.131 Endpoint Buffer Status Register
  104
- Table 2.132 Endpoint Control Register
  105
- General Commands
  106
- Table 2.133 Frame Number LSB Register
  106
- Table 2.134 Frame Number MSB Register
  106
- Pulse Width Modulation
  107
- Table 2.135 PWM Register Addresses
  108
- Figure 2.7 Square Wave with 50 % Duty Cycle
  108
- Figure 2.8 Square Wave with 20 % Duty Cycle
  109
- Table 2.136 PWM Control Register
  109
- Pwm_Control
  109
- Pwm_Int_Ctrl
  110
- Pwm_Prescaler
  110
- Pwm_Cnt16_Lsb
  110
- Table 2.137 PWM Ctrl 1 Register
  110
- Table 2.138 PWM Prescaler Register
  110
- Table 2.139 PWM Counter LSB Register
  110
- Table 2.141 PWM Comparator LSB Register
  111
- Table 2.143 PWM Toggle Enable Register
  111
- Table 2.142 PWM Comparator MSB Register
  111
- Pwm_Cmp16_0_Msb - Pwm_Cmp16_7_Msb
  111
- Table 2.140 PWM Counter MSB Register
  111
- Pwm_Cmp16_0_Lsb - Pwm_Cmp16_7_Lsb
  111
- Pwm_Cnt16_Msb
  111
- Pwm_Out_Toggle_En_0 - Pwm_Out_Toggle_En_7
  111
- Table 2.144 PWM out Clear Enable Register
  112
- Figure 2.9 Pulse Waveform Generated by 8 Comparators
  112
- Table 2.145 PWM Control Block Register
  112
- Table 2.146 PWM Initialisation Register
  112
- Use Cases
  112
- Pwm_Init
  112
- Pwm_Ctrl_Bl_Cmp8
  112
- Pwm_Out_Clr_En
  112
- Table 2.147 Programming 8 FT51A Comparators to Generate above Waveform
  113
- Table 2.148 Programming 2 FT51A Comparators for 50 % Duty Cycle
  113
- Table 2.149. PWM Ranges
  114
- Timers
  116
- Timer_Control
  117
- Table 2.150 Timer Register Addresses
  117
- Table 2.151 Timer Control Register
  117
- Table 2.154 Timer Control 3 Register
  118
- Table 2.153 Timer Control 2 Register
  118
- Table 2.152 Timer Control 1 Register
  118
- Timer_Control_3
  118
- Timer_Control_1
  118
- Timer_Control_2
  118
- Timer_Control_4
  119
- Timer_Int
  119
- Table 2.155 Timer Control 3 Register
  119
- Table 2.156 Timer Control 3 Register
  119
- Table 2.158 Timer Watchdog Register
  120
- Table 2.161 Timer Prescaler MSB Register
  120
- Table 2.160 Timer Write MSB Register
  120
- Table 2.159 Timer Write LSB Register
  120
- Timer_Write_Ls
  120
- Table 2.157 Timer Control 3 Register
  120
- Timer_Presc_Ls
  120
- Timer_Write_Ms
  120
- Timer_Wdg
  120
- Timer_Select
  120
- Table 2.162 Timer Prescaler MSB Register
  121
- Table 2.163 Timer Read MSB Register
  121
- Table 2.164 Timer Read MSB Register
  121
- Timer_Read_Ms
  121
- Timer_Read_Ls
  121
- Timer_Presc_Ms
  121
- Use Cases
  122
- Table 2.165 Timers Normal Operation
  122
- Table 2.166 Available Timer Ranges (in Seconds)
  124
- Figure 2.10 Timer Range for Uint32_T Timer
  125
- Dma
  128
- Dma_Control_X
  131
- Table 2.167 DMA Register Addresses
  131
- Table 2.168 DMA Control Register
  131
- Table 2.170 DMA Interrupts Enable Register
  132
- Dma_Irq_Ena_X
  132
- Table 2.169 DMA Enable/Reset Register
  132
- Dma_Enable_X
  132
- Dma_Irq_X
  133
- Dma_Src_Mem_Addr_L_X
  133
- Dma_Src_Mem_Addr_U_X
  133
- Dma_Dest_Mem_Addr_L_X
  133
- Table 2.171 DMA Interrupts Register
  133
- Table 2.172 IO Peripheral DMA Source Memory Address LSB Register
  133
- Table 2.173 IO Peripheral DMA Source Memory Address MSB Register
  133
- Table 2.174 IO Peripheral DMA Destination Memory Address LSB Register
  133
- Table 2.177 IO Peripheral DMA IO Address MSB Register
  134
- Table 2.176 IO Peripheral DMA IO Address LSB Register
  134
- Table 2.175 IO Peripheral DMA Destination Memory Address MSB Register
  134
- Dma_Src_Mem_Addr_U_X
  134
- Dma_Dest_Mem_Addr_U_X
  134
- Dma_Io_Addr_L_X
  134
- Table 2.179 IO Peripheral DMA Transfer Byte Count MSB Register
  135
- Table 2.181 IO Peripheral DMA Current Transfer Byte Count MSB Register
  135
- Table 2.180 IO Peripheral DMA Current Transfer Byte Count LSB Register
  135
- Table 2.182 IO Peripheral DMA FIFO DATA Register
  135
- Table 2.178 IO Peripheral DMA Transfer Byte Count LSB Register
  135
- Dma_Fifo_Data_X
  135
- Dma_Curr_Cnt_L_X
  135
- Dma_Trans_Cnt_U_X
  135
- Dma_Trans_Cnt_L_X
  135
- Dma_Afull_Trigger_X
  136
- Use Cases
  136
- Table 2.183 IO Peripheral DMA Almost Full Trigger Value
  136
- Application Guide
  138
- Libraries
  138
- Configuration Library
  138
- USB Library
  139
- DMA Library
  142
- UART Library
  143
- SPI Master Library
  144
- I2C Master Library
  145
- I2C Slave Library
  146
- AIO Library
  146
- IOMUX Library
  147
- Watchdog Library
  147
- DFU Library
  148
- LCD Library
  149
- TMC Library
  149
- USB Applications
  151
- Initialising USB Device
  151
- Descriptors
  152
- Standard Requests
  154
- Call-Backs
  158
- Class and Vendor Requests
  158
- Main Function
  159
- Sending and Receiving Data
  160
- Link Power Management
  160
- Contact Information
  162
- Appendix A - References
  163
- Document References
  163
- Acronyms and Abbreviations
  164
Appendix B - List of Tables & Figures List of Tables

165
- Appendix B - List of Tables & Figures
  165
- List of Tables
  165
- List of Figures
  169
- Appendix C - Revision History
  171

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