Force Computers SYS68K/CPU-41 Manuals

Manuals and User Guides for Force Computers SYS68K/CPU-41. We have 1 Force Computers SYS68K/CPU-41 manual available for free PDF download: User Manual

Force Computers SYS68K/CPU-41 User Manual (372 pages)

Brand: Force Computers | Category: Control Unit | Size: 7 MB

This Page was Intentionally Left Blank

4
- Table of Contents
  4
- General Information
  
  7
- The Processor
  
  14
  - The CPU 68040
    14
  - The Shared RAM
    16
  - The DRM-01/4
    16
  - The DRM-01/16
    17
  - The SRM-01/4
    18
  - The SRM-01/8
    19
  - The System EPROM
    20
  - The Local SRAM
    20
  - The Local FLASH EPROM
    20
  - The Boot EPROM
    20
  - The FGA-002
    21
  - The PI/T 68230
    22
  - The I/O Configuration of PI/T1
    23
  - The I/O Configuration of PI/T2
    23
  - The Real Time Clock 72423
    24
  - The DUSCC 68562
    25
  - The I/O Configuration of DUSCC1 and DUSCC2
    26
  - The EAGLE Modules
    28
  - The Vmebus Interface
    28
  - The Monitor of the CPU Board
    30
  - Default Jumper Settings on the CPU Board
    31
  - Figure 2-1: Location Diagram for All Jumperfields
    33
  - Figure 2-2: the Front Panel of the CPU Board
    34
- Specifications of the Cpu Board
  
  36
- Ordering Information
  
  38
- History of Manual Revisions
  
  40
Table of Contents

46
- 1 General Overview
  
  48
  - The Rotary Switches
    48
  - The Function Switch Positions
    48
  - Connection of the Terminal
    50
  - The Default Hardware Setup
    52
- 2 Installation in the Rack
  
  54
  - Power on
    54
  - Correct Operation
    55
- 3 Environmental Requirements
  
  56
Table of Contents

59
- General Information
  
  65
- The Processor
  
  67
  - The CPU 68040
    67
  - Hardware Interface of the 68040
    67
  - General Operation
    67
  - The Instruction Set
    67
  - Vector Table of the 68040
    68
- The Local Bus
  
  71
  - The FGA-002 Gate Array
    71
  - The Shared RAM
    72
  - General Operation
    72
  - Shared RAM Information
    72
  - The DRM-03
    74
  - RAM Type Information for the DRM-03
    75
  - Summary of the DRM-03
    75
  - The DRM-05
    76
  - RAM Type Information for the DRM-05
    77
  - Summary of the DRM-05
    77
  - The SRM-01/4
    78
  - RAM Type Information for the SRM-01/4
    79
  - Summary of the SRM-01/4
    79
  - The SRM-01/8
    80
  - RAM Type Information for the SRM-01/8
    81
  - Summary of the SRM-01/8
    81
  - The System EPROM Area
    82
  - Memory Organization of the System EPROM Area
    82
  - Usable Device Types for the EPROM Area
    85
  - Access Time Selection of the System EPROM Area
    88
  - Address Map of the System EPROM Area
    88
  - Summary of the EPROM Area
    88
  - The Flxibus
    89
  - Introduction to the Flxibus
    89
  - The Local FLASH EPROM
    90
  - Memory Organization of the FLASH EPROM
    90
  - Programming the FLASH EPROM
    91
  - Address Map of the FLASH EPROM
    91
  - Summary of the Local FLASH Memory
    91
  - Jumper Settings for B16
    91
  - Location Diagram of Jumperfield B16
    92
  - The Local SRAM
    93
  - Memory Organization of the User SRAM
    93
  - The Address Map of the SRAM Area
    96
  - Summary of the SRAM Area
    96
  - The Boot EPROM
    97
  - Summary of the Boot EPROM Area
    97
  - The DUSCC 68562
    99
  - Address Map of the DUSCC1 Registers
    100
  - RS232 Hardware Configuration of Port #1 and #2
    102
  - Cable for the Micro D-Sub Connector
    108
  - RS422/RS485 Hardware Configuration of Ports #1 and #2
    108
  - RS232 and RS422/RS485 Driver Modules FH002 and FH003
    115
  - Summary of DUSCC1
    115
  - Address Map of the DUSCC2 Registers
    116
  - RS232 Hardware Configuration of Ports #3 and #4
    118
  - Cable for the Micro D-Sub Connector
    122
  - RS422/RS485 Hardware Configuration of Port #3 and #4
    122
  - RS232 and RS422/RS485 Driver Modules FH002 and FH003
    128
  - Summary of DUSCC2
    128
  - The PI/T 68230
    129
  - Address Map of the PI/T1 Registers
    130
  - I/O Configuration of PI/T1
    131
  - Rotary Switches
    132
  - Lock Cycles
    134
  - Interrupt Request Signal
    135
  - A24 Slave Mode
    135
  - Reserved Lines
    135
  - Summary of PI/T1
    136
  - Address Map of the PI/T2 Registers
    137
  - I/O Configuration of PI/T2
    138
  - Memory Size Recognition
    139
  - Board Identification
    139
  - Interrupt Request Signal
    139
  - Bit I/O Port
    140
  - Modlow
    142
  - RAM Module Configuration Signals
    142
  - Timer Irq/Reset
    143
  - Pirq
    143
  - Enable A24 Slave Mode
    143
  - Reserved Line
    144
  - Summary of PI/T2
    144
  - The Real Time Clock (RTC) 72423
    145
  - Address Map of the RTC Registers
    145
  - RTC Programming
    145
  - Summary of the RTC
    149
- FUNCTION SWITCHES and INDICATION Leds
  
  150
  - RESET Function Switch
    150
  - ABORT Function Switch
    150
  - Run" Led
    151
  - Bm" Led
    151
  - Rotary Switches
    151
- The Cpu Board Interrupt Structure
  
  154
- Vmebus Interface
  
  156
  - Vmebus Master Interface
    156
  - Data Transfer Size of the Vmebus Interface
    156
  - Address Modifier Implementation
    159
  - Vmebus Slave Interface
    163
  - The Access Address
    163
  - Data Transfer Size of the Shared RAM
    163
  - Address Modifier Decoding and A24 Slave Mode
    163
  - The Vmebus Interrupt Handler
    166
  - Vmebus Arbitration
    167
  - Four Available Vmebus Arbiters
    167
  - The On-Board Four Level Arbiter
    167
  - The Vmebus Release Function
    173
  - Release Every Cycle (REC)
    173
  - Release on Request (ROR)
    173
  - Release after Timeout (RAT)
    173
  - Release on Bus Clear (RBCLR)
    174
  - Release When Done (RWD)
    174
  - Release Voluntary (RV)
    174
  - Release on ACFAIL (ACFAIL)
    174
  - The Vmebus Interrupter
    176
  - The Interrupt Generation Register
    176
  - The SYSCLK Driver
    178
  - Exception Signals
    180
  - RESET Generation
    182
  - The Front Panel RESET Switch
    182
  - The Voltage Sensor Module FH001
    182
  - Vmebus RESET Conditions
    184
  - Receive RESET from Vmebus
    184
  - Drive RESET to Vmebus
    184
  - Default Configuration of Jumperfield B13
    184
  - The RESET Instruction
    186
Introduction to Vmeprom in Use with the Sys68K/Cpu-40/41

235
- 1 General
  
  237
  - General Information
    237
  - Features of VMEPROM
    238
  - Power-Up Sequence
    238
  - Front Panel Switches
    239
  - RESET Switch
    239
  - ABORT Switch
    239
  - Control Switches
    239
  - Default Memory Usage of VMEPROM
    244
  - Default EPROM Usage of VMEPROM
    245
- 2 Details of the Cpu Board
  
  247
  - EPROM/RAM Layout
    247
  - On-Board I/O Devices
    248
  - Base Addresses of Onboard I/O Devices
    248
  - Base Addresses of EAGLE Module Devices
    249
  - On-Board Interrupt Sources
    250
  - Off-Board Interrupt Sources
    251
  - The On-Board Real Time Clock
    251
- 3 Concept of Vmeprom
  
  253
  - Getting Started
    253
  - Command Line Syntax
    253
  - VMEPROM Commands
    254
- 4 Special Vmeprom Commands for Cpu Board
  
  255
Appendix To the Introduction to Vmeprom

269
- Vmebus Board Setup
  
  270
  - Vmebus Memory
    270
  - A2. Sys68K/Sio-1/Sio-2
    271
  - A3. Sys68K/Isio-1/2
    272
    
    SYS68K/ISCSI-1 Disk Controller
    273
    
    Local FDC and SCSI Controller
    274
  - A6. Boards with a Running Management Entity (ME
    275
  - A6.1 UART Driver
    275
    
    Onboard EAGLE Module
    275
    
    Offboard EAGLE Modules
    276
  - A6.2 Disk Driver
    277
- S-Record Formats
  
  278
  - S-Record Types
    278
  - S-Record Example
    279
- System RAM Definitions
  
  281
- Task Control Block Definitions
  
  283
- Interrupt Vector Table of VMEPROM
  
  286
- Benchmark Source Code
  
  288
- Special Locations
  
  294
- Generation of Applications in EPROM
  
  296
  - General Information
    296
  - H1.1 Replacing the User Interface
    296
- Introduction to the RAM Port
  
  298
  - Accessing the RAM Port through the ACI
    298
  - Acquire the RAM Port
    299
  - Reading Data from the RAM Port
    300
  - Writing Data to the RAM Port
    301
  - Accessing the RAM Port from VMEPROM
    302
  - The Internal Structure of the RAM Port
    304
- Minimum Demands for Device Driver Tasks in Order to Run with VMEPROM
  
  306
  - Device Driver Tasks for Serial Devices
    306
  - Device Driver Tasks for Block Devices
    309
  - Floppy Devices
    309
  - SCSI Devices
    314
Table of Contents

321
- 1 Introduction
  
  322
  - The Logical Devices
    325
  - The Command Control Buffers
    326
- 2 The Complete Description of All Commands Provided by the Application Command Interface
  
  329
  - The OPEN Command
    329
  - The CLOSE Command
    339
  - The READ Command
    341
  - The WRITE Command
    345
  - The SERVICE Command
    349
  - The Get Logical Device Number Service
    353
- 3 Command Chaining
  
  354
  - The CCB_ALLOCATE Command
    356
  - The CCB_FREE Command
    358
- 4 Error Codes
  
  360
- 5 The Following Example Shows How to Communicate with the ACI
  
  363

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Force Computers SYS68K/CPU-41 Manuals

Force Computers SYS68K/CPU-41 User Manual (372 pages)

Table of Contents

This Page was Intentionally Left Blank

General Information

The Processor

Specifications of the Cpu Board

Ordering Information

History of Manual Revisions

Table of Contents

1 General Overview

2 Installation in the Rack

3 Environmental Requirements

Table of Contents

General Information

The Processor

The Local Bus

FUNCTION SWITCHES and INDICATION Leds

The Cpu Board Interrupt Structure

Vmebus Interface

Introduction to Vmeprom in Use with the Sys68K/Cpu-40/41

1 General

2 Details of the Cpu Board

3 Concept of Vmeprom

4 Special Vmeprom Commands for Cpu Board

Appendix To the Introduction to Vmeprom

Vmebus Board Setup

S-Record Formats

System RAM Definitions

Task Control Block Definitions

Interrupt Vector Table of VMEPROM

Benchmark Source Code

Special Locations

Generation of Applications in EPROM

Introduction to the RAM Port

Minimum Demands for Device Driver Tasks in Order to Run with VMEPROM

Table of Contents

1 Introduction

2 The Complete Description of All Commands Provided by the Application Command Interface

3 Command Chaining

4 Error Codes

5 The Following Example Shows How to Communicate with the ACI

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