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Force Computers SYS68K/CPU-40 User Manual

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SYS68K/CPU-40/41
User's Manual
Edition No. 8
February 1997
P/N 202368
FORCE COMPUTERS Inc./GmbH
All Rights Reserved
This document shall not be duplicated, nor its contents used
for any purpose, unless express permission has been granted.
Copyright by FORCE COMPUTERS

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  • Page 1 SYS68K/CPU-40/41 User’s Manual Edition No. 8 February 1997 P/N 202368 FORCE COMPUTERS Inc./GmbH All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE COMPUTERS...
  • Page 2 INTRODUCTION...
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  • Page 4: Table Of Contents

    TABLE OF CONTENTS GENERAL INFORMATION ......... . . Features of the CPU Board .
  • Page 5 LIST OF FIGURES Figure 1-1: Photo of the CPU Board ..........Figure 1-2: Block Diagram of the CPU Board .
  • Page 6 This page was intentionally left blank...

  • Page 7: General Information

    A broad range of operating systems and kernels is available for the CPU board. However, as with all FORCE COMPUTERS' CPU cards, VMEPROM firmware is provided with the board at no extra cost. VMEPROM is a Real Time Kernel and is installed on the CPU board in the two 16-bit wide EPROM sockets,...

  • Page 8: Figure 1-1: Photo Of The Cpu Board

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 1-1: Photo of the CPU Board...

  • Page 9: Figure 1-2: Block Diagram Of The Cpu Board

    SECTION 1 INTRODUCTION Figure 1-2: Block Diagram of the CPU Board...
  • Page 10 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 1.1 Features of the CPU 3Board 68040 microprocessor: 25.0 MHz on CPU-40B/41B/x 68040 microprocessor: 33.0 MHz on CPU-40D/41D/x Shared DRAM Module: 4 Mbyte DRAM with Burst Read/Write and Parity Generation and Checking (DRM-01/4) 16 Mbyte DRAM with Burst Read/Write and Parity Generation and...

  • Page 11: Features Of The Cpu Board

    SECTION 1 INTRODUCTION Features of the CPU Board (cont'd) Four-level VMEbus arbiter SYSCLK driver VMEbus interrupter (IR 1-7) VMEbus interrupt handler (IH 1-7) Support for ACFAIL* and SYSFAIL Bus timeout counters for local and VMEbus access (15 µsec) VMEPROM, Real Time Multitasking Kernel with monitor, file manager and debugger...

  • Page 12: Table 1-1: The Memory Map

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The following table summarizes the memory map of the CPU board. Table 1-1: The Memory Map Start Type Address Address 00000000 003FFFFF Shared Memory (4 Mbyte) 00000000 007FFFFF Shared Memory (8 Mbyte) or 00000000 00FFFFFF...

  • Page 13: Table 1-2: The Base Addresses Of The Local I/O Devices

    SECTION 1 INTRODUCTION This table gives a brief overview of the local I/O devices and the equivalent base address. Table 1-2: The Base Addresses of the Local I/O Devices BASE ADDRESS DEVICE $FF803000 72423 $FF802000 DUSCC1 68562 $FF802200 DUSCC2 68562 $FF800C00 PI/T1 68230...

  • Page 14: The Processor

    SECTION 1 INTRODUCTION 2. THE PROCESSOR 2.1 The CPU 68040 The 68040 is a third generation full 32 bit enhanced microprocessor. The 68040 is upward object code compatible with the 68030, 68020, 68010 and 68000 line of microprocessors. The 68040 combines a central processing unit core, an instruction cache, a data cache, a memory management unit, and an enhanced bus controller.
  • Page 15 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Features of the 68040 Nonmultiplexed 32 bit address and data buses 16 general purpose address and data registers (32 bit wide) 8 floating point data registers (80 bit wide) Two supervisor stack pointers (32 bit wide)

  • Page 16: The Shared Ram

    SECTION 1 INTRODUCTION 2.2 The Shared RAM On this CPU board the shared RAM is placed on a module to allow the adaption of DRAM or SRAM to the base board. All signals which are needed to control the shared RAM are available on the RAM module connector. Therefore RAM devices with different access times can also be used on this CPU board to take advantage of the 68040 with higher frequency if it becomes available.

  • Page 17: The Drm-01/16

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.2.2 The DRM-01/16 The DRM-01/16 is a 16 Mbyte RAM module which is used on the CPU-40B/16. Features of the DRM-01/16 16 Mbyte DRAM Burst READ and Burst WRITE capability Parity Generation and Checking Asynchronous refresh is provided every 14µs Accessible via VMEbus The access address for the 68040 is $00000000 to $00FFFFFF.

  • Page 18: The Srm-01/4

    SECTION 1 INTRODUCTION 2.2.3 The SRM-01/4 The SRM-01/4 is a 4 Mbyte RAM module which is used on the CPU-41B/4. Features of the SRM-01/4 4 Mbyte SRAM Burst READ and Burst WRITE capability Battery Backup via VMEbus Accessible via VMEbus The access address for the 68040 is $00000000 to $003FFFFF.

  • Page 19: The Srm-01/8

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.2.4 The SRM-01/8 The SRM-01/8 is an 8 Mbyte RAM module which is used on the CPU-41B/8. Features of the SRM-01/8 8 Mbyte SRAM Burst READ and Burst WRITE capability Battery Backup via VMEbus Accessible via VMEbus The access address for the 68040 is $00000000 to $007FFFFF.

  • Page 20: The System Eprom

    SECTION 1 INTRODUCTION 2.3 The System EPROM The CPU board offers two 40-pin EPROM sockets for the installation of two 16-bit wide EPROM devices. The EPROMs present a full 32-bit data path to the processor enabling maximum performance. The following devices are supported in the system EPROM area: Supported Device Types in the System EPROM Area: Organization Total Memory Capacity...

  • Page 21: The Fga-002

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.7 The FGA-002 One of the main features on this CPU board is the FGA-002 Gate Array with 24,000 gates and 281 pins. The FGA-002 controls the local bus and builds the VMEbus interface. It also includes a DMA controller, a complete interrupt handler, message broadcast interface (FMB), timer functions, mailbox locations, and a VMEbus interrupter.

  • Page 22: The Pi/T 68230

    SECTION 1 INTRODUCTION 2.8 The PI/T 68230 The MC68230 Parallel Interface/Timer (PI/T) provides versatile double buffered parallel interfaces and an operating system oriented timer for MC68000 systems. The parallel interfaces operate in unidirectional or bidirectional modes, 8 or 16 bits wide. The PI/T timer contains a 24 bit wide counter and a 5 bit prescaler. Features of the PI/T MC68000 Bus Compatible Port Modes Include: Bit I/O...

  • Page 23: The I/O Configuration Of Pi/T1

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.8.1 The I/O Configuration of PI/T1 Port A is connected to the two 4 bit HEX rotary switches provided on the front panel for application dependent settings. Port B is used for programming the local base address for A24 accesses from the VMEbus.

  • Page 24: The Real Time Clock 72423

    SECTION 1 INTRODUCTION 2.9 The Real Time Clock 72423 There is a Real Time Clock (RTC) 72423 installed on the CPU board. The CPU board contains a self supportive battery to sustain the RTC during power down. Features of the RTC Built-in quartz oscillator makes regulation unnecessary and allows easy design Direct bus compatibility (120 ns access time) Incorporated built-in time (hour, minute, second), and date (year, month, week, day) counters...

  • Page 25: The Duscc 68562

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.10 The DUSCC 68562 The Dual Universal Serial Communications Controller (DUSCC) 68562 is installed to communicate with terminals, computers, or other equipment. The DUSCC is a single chip MOS-LSI communications device providing two independent, multiprotocol, full duplex receiver/transmitter channels in a single package.

  • Page 26: The I/O Configuration Of Duscc1 And Duscc2

    SECTION 1 INTRODUCTION 2.10.1 The I/O Configuration of DUSCC1 and DUSCC2 The four channels may be configured to function as a RS232 or RS422/RS485 compatible interface. Termination resistors can be installed to adapt various cable lengths and reduce reflections upon the selection of the RS422/RS485 compatible interface.
  • Page 27 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The I/O signals of channel 1 can be connected to the VME connector P2 in parallel to the 9-pin Micro D-Sub connector as follows: Signal Input Output VME Connector Description Data Carrier Detect Receive Data...

  • Page 28: The Eagle Modules

    SECTION 1 INTRODUCTION 2.11 The EAGLE Modules EAGLE modules are I/O subsystems designed not only to increase the functionality of the board but to add the exact I/O features to fit the application requirement. EAGLE modules connect directly onto the FLXi of the base board.
  • Page 29 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Each of the listed modes is software programmable inside the gate array. The bus request level of the CPU board is jumper or software selectable (BRO-3). The DMA controller installed in the FGA-002 on the CPU board is able to access the VMEbus interface independently from the microprocessor, enabling VMEbus communication to take place without impacting the processing capabilities of the rest of the board for number crunching or servicing on-board I/O.

  • Page 30: The Monitor Of The Cpu Board

    SECTION 1 INTRODUCTION 2.13 The Monitor of the CPU board Every CPU board contains VMEPROM, a real time multitasking monitor debugger. It consists of a powerful real time kernel, file manager and monitor/debugger with 68040 line assembler/disassembler. The monitor/debugger includes all functions to control the real time kernel and file manager as well as all tools required for program debugging such as breakpoints, tracing, memory display, memory modify and host communication.

  • Page 31: Default Jumper Settings On The Cpu Board

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.14 Default Jumper Settings on the CPU Board The following are the default jumper settings and a location diagram displaying all jumpers. Default Jumper Settings for the CPU Jumperfield Description Default Schematics Connection Reset Voltage Sensor...
  • Page 32 SECTION 1 INTRODUCTION Default Jumper Settings for VMEbus Jumperfield Description Default Schematics Connection Four level Arbiter Request Level SYSCLK SH10 SYSFAIL Receive VMEbus RESET Drive VMEbus RESET Default Jumper Settings for Test Jumperfield Description Default Schematics Connection Clock Signal to CPU SH16 Headers for 12 Bit I/O and 8 Bit I/O Jumperfield...

  • Page 33: Figure 2-1: Location Diagram For All Jumperfields

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 2-1: Location Diagram for All Jumperfields 2-20...

  • Page 34: Figure 2-2: The Front Panel Of The Cpu Board

    SECTION 1 INTRODUCTION Figure 2-2: The Front Panel of the CPU Board 2-21...
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  • Page 36: Specifications Of The Cpu Board

    SECTION 1 INTRODUCTION 3. SPECIFICATIONS OF THE CPU BOARD CPU Type 68040 CPU Clock Frequency CPU-40B/x 25.0 MHz CPU-40D/x 33.0 MHz Shared DRAM Capacity with Parity CPU-40X/4 4 Mbytes CPU-40X/16 16 Mbytes Shared SRAM Capacity CPU-41X/4 4 Mbytes CPU-41X/8 8 Mbytes SRAM Capacity with On-board Battery Backup 128 Kbytes FLASH EPROM...
  • Page 37 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS This page intentionally left blank...

  • Page 38: Ordering Information

    SECTION 1 INTRODUCTION 4. ORDERING INFORMATION SYS68K/CPU-40B/4-00 25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial I/O channels, FLXi, VMEPROM. Documentation included. SYS68K/CPU-40B/4-01 25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial I/O channels, EAGLE-01C (SCSI, floppy disk and Ethernet Interface), VMEPROM.
  • Page 39 VMEPROM update service for the SYS68K/CPU-40 series. SYS68K/VMEPROM/UM VMEPROM User's Manual excluding the SYS68K/CPU-40 description. SYS68K/CPU-40/UM User's Manual for the SYS68K/CPU-40 product, including VMEPROM User's Manual and EAGLE-01C User's Manual (separately available as EAGLE-01C/UM). SYS68K/FGA-002/UM User's Manual for the FGA-002 Gate Array.

  • Page 40: History Of Manual Revisions

    SECTION 1 INTRODUCTION 5. HISTORY OF MANUAL REVISIONS Revision No. Description Date of Last Change First Print. FEB/05/1991 The following sections/pages have been changed: APR/16/1991 Section 1: Page 2-16 (EPROM Description) Section 3: Pages 3-11, 3-12, 3-14, 3-15 (EPROM Description) Section 4: Page F-1 (EPROM Description) Sections 7, 8, and 9: These have been changed to adapt to VMEPROM Version 2.74...
  • Page 41 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Section 3: DRM-01/4 and DRM-01/16 have been MAR/14/1996 replaced by DRM-03 and DRM-05 respectively. Appendix F-2: The description of jumperfield B13 has been corrected. Editorial Changes Febr/18/1997...
  • Page 42 INSTALLATION...
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  • Page 44 W A R N I N G TO AVOID MALFUNCTIONS AND COMPONENT DAMAGE, PLEASE READ THE COMPLETE INSTALLATION PROCEDURE BEFORE THE BOARD IS INSTALLED IN A VMEBUS ENVIRONMENT. C A U T I O N To ensure proper functioning of the product over its usual lifetime, take the following precautions before handling the board.
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  • Page 46 TABLE OF CONTENTS GENERAL OVERVIEW ........... The Rotary Switches .
  • Page 47 This page was intentionally left blank...

  • Page 48: General Overview

    SECTION 2 INSTALLATION 1. GENERAL OVERVIEW Easy installation of the CPU board is provided since the memory map, the I/O devices, and the interfaces are configured to communicate with a standard terminal containing RS232 interface. The monitor (VMEPROM) boots up automatically with the setup of the rotary switches on the front panel. 1.1 The Rotary Switches Two rotary switches are installed on the CPU board to configure the startup of the VMEPROM or a user program.
  • Page 49 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 1-1: Front Panel of CPU Board and the Rotary Switch Positions...

  • Page 50: Connection Of The Terminal

    SECTION 2 INSTALLATION 1.3 Connection of the Terminal The terminal must be connected to the 9-pin Micro D-Sub connector 1 on the CPU board. The board is delivered with a 9-pin Micro D-Sub to 9-pin D-Sub adapter cable. The following communication setup is used for interfacing the terminal. Please configure the terminal to this setup.
  • Page 51 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 1-2: Pinout of the Micro D-Sub and D-Sub Connector for RS232 A) Micro DSUB Male Connector Soldered B) Micro DSUB and DSUB Female Connectors on the Adapter/Terminal Cable on the CPU Board RS232 RS232...

  • Page 52: The Default Hardware Setup

    SECTION 2 INSTALLATION 1.4 The Default Hardware Setup The VMEbus interface is configured to be used immediately, without any changes. This results in a default hardware setup which may conflict with other boards installed in the rack. The following signals are driven/received from the CPU board: Signal Driven Received...
  • Page 53 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS This page intentionally left blank...

  • Page 54: Installation In The Rack

    SECTION 2 INSTALLATION 2. INSTALLATION IN THE RACK The CPU board can immediately be mounted into a VME rack at slot 1. CAUTION Switch off power before installing the board to avoid electrical damage to the components. The CPU board contains a special ejector (the handles). The board must be plugged in, and the screws on the front panel tightened up to guarantee proper installation.

  • Page 55: Correct Operation

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.2 Correct Operation To test the correct operation of the CPU board, the following command must be typed in: ? SELFTEST<cr> It is a matter of a few seconds until all tests are completed. Once all tests are completed, the following...

  • Page 56: Environmental Requirements

    SECTION 2 INSTALLATION 3. ENVIRONMENTAL REQUIREMENTS This board was specified and tested for reliable operation under certain environmental conditions. Based on our performance tests, this board is capable of operating within the temperature range of 0 C to 50 C when used inside of a FORCE TARGET-32 chassis.
  • Page 57 HARDWARE USER'S MANUAL...
  • Page 58 This page was intentionally left blank...
  • Page 59 TABLE OF CONTENTS GENERAL INFORMATION ..........1-1 THE PROCESSOR .
  • Page 60 3.6.1 Memory Organization of the User SRAM ....... . 3-23 3.6.2 The Address Map of the SRAM Area .
  • Page 61 ABORT Function Switch .........."RUN"...
  • Page 62 LIST OF FIGURES Figure 2-1: Jumper Setting for B17 ..........Figure 2-2: Location Diagram of Jumperfields B17 .
  • Page 63 LIST OF TABLES Table 2-1: Exception Vector Assignments ........Table 3-1: Address Map of the EPROM Area .
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  • Page 65: General Information

    A broad range of operating systems and kernels is available for the CPU board. However, as with all FORCE COMPUTERS' CPU cards, VMEPROM firmware is provided with the board at no extra cost. VMEPROM is a Real Time Kernel and is installed on the CPU board in the 16-bit wide EPROM sockets,...
  • Page 66 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS This page intentionally left blank...

  • Page 67: The Processor

    SECTION 3 HARDWARE USER'S MANUAL 2. THE PROCESSOR 2.1 The CPU 68040 2.1.1 Hardware Interface of the 68040 The 68040 uses a nonmultiplexed 32-bit address and 32-bit data bus. The 68040 does not support the dynamic bus sizing like the 68020 or 68030. On this CPU board the dynamic bus sizing is built in external hardware (two programmable gate arrays).

  • Page 68: Vector Table Of The 68040

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.3 Vector Table of the 68040 The following table lists all vectors defined and used by the 68040 CPU. Table 2-1: Exception Vector Assignments Vector Vector Offset Assignment Number(s) (Hex) Reset Initial Interrupt Stack Pointer...
  • Page 69 SECTION 3 HARDWARE USER'S MANUAL For test purposes the clock signal for the microprocessor is connected via jumper B17 to the devices. When using the CPU board, this jumper must be inserted according to the following figure. CAUTION If jumper B17 is removed, damage may be caused to the devices on the CPU board. Figure 2-1: Jumper Setting for B17 +)))))))), +)))))))),...
  • Page 70 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 2-2: Location Diagram of Jumperfields B17...

  • Page 71: The Local Bus

    SECTION 3 HARDWARE USER'S MANUAL 3. THE LOCAL BUS 3.1 The FGA-002 Gate Array The FGA-002 Gate Array featured on this CPU board has 24,000 gates and 281 pins. The FGA-002 Gate Array controls the local bus and builds the interface to the VMEbus. It also includes a DMA controller, complete interrupt management, a message broadcast interface (FMB), timer functions, and mailbox locations.

  • Page 72: The Shared Ram

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.2 The Shared RAM On this CPU board the shared RAM is placed on a module to allow the adaptation of DRAM or SRAM to the base board. All signals which are needed to control the shared RAM are available on the RAM module connector.
  • Page 73 SECTION 3 HARDWARE USER'S MANUAL The following table shows the information which can be read and the corresponding PI/T bit. The RAM modules which are accessible are described in the following chapters which also contain the RAM Type Information description. RAM Type Information on PI/T2 PI/T Bit Name...

  • Page 74: The Drm-03

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.2.3 The DRM-03 The following CPU board is assembled with the DRM-03. CPU Board RAM Module RAM Capacity CPU-40B/4/xx DRM-03/4 4 Mbyte "xx" contains the EAGLE module number and is independent of the RAM module.

  • Page 75: Ram Type Information For The Drm-03

    SECTION 3 HARDWARE USER'S MANUAL Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait Type Frequency Cycles Counted Cycles for States for States for From TS to TA Burst Cycles Normal Cycles Burst Cycles for Normal Cycles CPU-40/B...

  • Page 76: The Drm-05

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.2.6 The DRM-05 The following CPU boards are assembled with the DRM-05. CPU Board RAM Module RAM Capacity CPU-40B/16/xx DRM-05/16 16 Mbyte CPU-40B/32/xx DRM-05/32 32 Mbyte "xx" contains the EAGLE module number and is independent of the RAM module.

  • Page 77: Ram Type Information For The Drm-05

    SECTION 3 HARDWARE USER'S MANUAL Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait Type Frequency Cycles Counted Cycles for States for States for From TS to TA Burst Cycles Normal Cycles Burst Cycles for Normal Cycles...

  • Page 78: The Srm-01/4

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.2.9 The SRM-01/4 The following CPU boards are assembled with the SRM-01/4. CPU Board RAM Module CPU-41B/4/xx SRM-01/4 "xx" contains the EAGLE module number and is independent for the RAM module. The SRM-01/4 is a 4 Mbyte RAM module using Static Memory devices. The RAM module has the following features.

  • Page 79: Ram Type Information For The Srm-01/4

    SECTION 3 HARDWARE USER'S MANUAL 3.2.10 RAM Type Information for the SRM-01/4 The following information can be read from the PI/T2. RAM Type Information PI/T Bit Name Value MCD4 MCD1 MCD2 RAMTYP BURST PARITY 3.2.11 Summary of the SRM-01/4 Capacity 4 Mbytes Address Range $00000000 to $003FFFFF...

  • Page 80: The Srm-01/8

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.2.12 The SRM-01/8 The following CPU boards are assembled with the SRM-01/8. CPU Board RAM Module CPU-41B/8/xx SRM-01/8 "xx" contains the EAGLE module number and is independent for the RAM module. The SRM-01/8 is an 8 Mbyte RAM module which is used on the CPU-41B/8.

  • Page 81: Ram Type Information For The Srm-01/8

    SECTION 3 HARDWARE USER'S MANUAL 3.2.13 RAM Type Information for the SRM-01/8 The following information can be read from the PI/T2. RAM Type Information PI/T Bit Name Value MCD4 MCD1 MCD2 RAMTYP BURST PARITY 3.2.14 Summary of the SRM-01/8 Capacity 8 Mbytes Address Range $00000000 to $007FFFFF...

  • Page 82: The System Eprom Area

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.3 The System EPROM Area The first two read cycles after RESET of the microprocessor are fetches of the Initial Interrupt Stack Pointer and the Initial Program Counter. These cycles are executed under addresses $0 and $4 respectively. A special control logic maps the System EPROM Area down to this address to start the CPU from the installed EPROMs.
  • Page 83 SECTION 3 HARDWARE USER'S MANUAL Figure 3-2: Location Diagram of the System EPROM Area 3-13...
  • Page 84 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The following read only cycles can be forced to the System EPROM Area: Byte: 8 Bits Word: 16 Bits Long Word: 32 Bits The processor supports long word read instructions to odd addresses, resulting in byte and word accesses which meet the 68040 boundary requirements.

  • Page 85: Usable Device Types For The Eprom Area

    SECTION 3 HARDWARE USER'S MANUAL Example for Data Transfers: The following instruction is fully supported from the System EPROM Area: MOVE.X ($FF00 000Y), D0 X = B = Byte 1 Byte X = W = Word 2 Bytes X = L = Long Word 4 Bytes Y = 0 Y = 1...
  • Page 86 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-3: Configuration Jumper Settings of System EPROM Area Jumperfield B11 Jumpersetting: Device: Organization: 27C210 64K x 16 27C2048 128K x 16 (DEFAULT) UNDEFINED 256K x 16 UNDEFINED 512K x 16 3-16...
  • Page 87 SECTION 3 HARDWARE USER'S MANUAL Figure 3-4: Location Diagram of Jumperfield B11 Configuration of the System EPROM Area 3-17...

  • Page 88: Access Time Selection Of The System Eprom Area

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.3.3 Access Time Selection of the System EPROM Area The access time of the System EPROM Area is software programmable in the FGA-002 Gate Array. It can be adapted to various access speeds of the EPROM devices. A complete description of the FGA-002 Gate Array can be found in the related manual.

  • Page 89: The Flxibus

    SECTION 3 HARDWARE USER'S MANUAL 3.4 The FLXibus The CPU board can be used with or without an I/O subsystem, called an "EAGLE" Module. The EAGLE module increases the functionality of the board and adds extra I/O features to fit the application requirement.

  • Page 90: The Local Flash Eprom

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.5 The Local FLASH EPROM The CPU board holds a 128K x 8 FLASH EPROM which allows data storage without the need of a battery or supply via the +5VSTDBY VMEbus line. 3.5.1 Memory Organization of the FLASH EPROM The FLASH EPROM is connected with the data lines D24 to D31.

  • Page 91: Programming The Flash Eprom

    SECTION 3 HARDWARE USER'S MANUAL 3.5.2 Programming the FLASH EPROM The software and hardware to erase and program the FLASH EPROM is installed on the CPU board. For detailed information on how to program the FLASH EPROM, please refer to the CPU-40 VMEPROM description which is located in Section 7 and Section 8 of this manual.

  • Page 92: Location Diagram Of Jumperfield B16

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.5.6 Location Diagram of Jumperfield B16 3-22...

  • Page 93: The Local Sram

    SECTION 3 HARDWARE USER'S MANUAL 3.6 The Local SRAM The SRAM allows the user to retain data even when the power supply is switched off. A battery provides the voltage for the SRAM standby mode. With Jumper B20, it is possible to select either the on board battery or the +5VSTDBY of the VMEbus for backup supply.
  • Page 94 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS All combinations of the listed instructions are allowed and possible. This SRAM can be used to save special settings of the FGA-002 as described in Section 7 , Introduction to VMEPROM of this manual. The following figure shows the location diagram of Jumperfield B20 for the backup supply. The default configuration uses the on board battery.
  • Page 95 SECTION 3 HARDWARE USER'S MANUAL Figure 3-5: Location Diagram of the Backup Supply Jumperfield B1 and B20 3-25...

  • Page 96: The Address Map Of The Sram Area

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.6.2 The Address Map of the SRAM Area The address range of the SRAM Area is mapped via the FGA-002 and a PAL and is unchangeable. The SRAM is used by the boot software and therefore not fully available to the user. Please refer to the FGA- 002 User's Manual, Section 10, Boot Software .

  • Page 97: The Boot Eprom

    SECTION 3 HARDWARE USER'S MANUAL 3.7 The Boot EPROM The CPU board contains one 28-pin EPROM which is used to boot up the processor and run a program to initialize register contents of the FGA-002 Gate Array. This program finishes in such a manner that the System EPROM appears to have booted the CPU Board.
  • Page 98 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-6: Location Diagram of the Boot EPROM 3-28...

  • Page 99: The Duscc 68562

    SECTION 3 HARDWARE USER'S MANUAL 3.8 The DUSCC 68562 The Dual Universal Serial Communications Controller 68562 (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multiprotocol, full duplex receiver/ transmitter channels in a single package. Each channel consists of a receiver, a transmitter, a 16 bit multifunction counter/timer, a digital phaselocked loop (DPLL), a parity/CRC generator and checker, and associated control circuits.

  • Page 100: Address Map Of The Duscc1 Registers

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.8.1 Address Map of the DUSCC1 Registers The following tables contain the complete register map of the DUSCC1. Table 3-2: Serial I/O Port #1 (DUSCC1) Register Address Map Port Base Address: $FF802000 Address Offset Reset...
  • Page 101 SECTION 3 HARDWARE USER'S MANUAL Table 3-3: Serial I/O Port #2 (DUSCC1) Register Address Map Port Base Address: $FF802000 Address Offset Reset Mode Label Description Value $FF802020 DUSCMR1 Channel Mode Reg 1 $FF802021 DUSCMR2 Channel Mode Reg 2 $FF802022 DUSSS1R SYN1/Secondary Adr Reg 1 $FF802023 DUSS2R...

  • Page 102: Rs232 Hardware Configuration Of Port #1 And #2

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.8.2 RS232 Hardware Configuration of Port #1 and #2 Ports #1 and #2 are built around the DUSCC (J19). The DUSCC is connected to the local 8 bit data bus. The RS232 interfaces of port #1 and #2 are identical except that port #1 is additionally wired to a 0 resistor field which allows connection to the VMEbus P2 connector.
  • Page 103 SECTION 3 HARDWARE USER'S MANUAL The following figure shows the location diagram of the 0 resistor fields R563 to R569 and the figure afterwards displays the connection between the DUSCC and the VMEbus Connector P2, and the Micro D- Sub connector. CAUTION Before installing the 0 resistors to generate the port #1 availability on the VMEbus P2 Connector,...
  • Page 104 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-7: Location Diagram of the 0 Resistors R563 to R569 3-34...
  • Page 105 SECTION 3 HARDWARE USER'S MANUAL Figure 3-8: RS232 Connection Between DUSCC1 and VMEbus Connector P2 DUSCC FH002 68562 VME P2 CHANNEL Pin No. Pin No. Figure 3-9: RS232 Connection Between DUSCC1 and Micro D-Sub Connector DUSCC FH002 68562 CHANNEL G ND Pin No.
  • Page 106 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The devices are labeled as shown in the following chart. Port# Channel Connector 1/VME P2 The next figure shows the pinout of the Micro D-Sub connector for RS232. The figure on the next page displays the location of the RS232 configuration jumperfields.
  • Page 107 SECTION 3 HARDWARE USER'S MANUAL Figure 3-11: Location Diagram of RS232 Configuration Jumperfields B3, B4, B5, and B6 3-37...

  • Page 108: Cable For The Micro D-Sub Connector

    The CPU board is delivered with one 9-pin Micro D-Sub to 9-pin D-Sub Adapter Cable. Additional cables or a 9-pin Micro D-Sub to 25-pin D-Sub Adapter Cable are available from FORCE COMPUTERS. 3.8.4 RS422/RS485 Hardware Configuration of Ports #1 and #2 The CPU board is delivered with RS232 compatible interface buffers installed on all serial I/O ports.
  • Page 109 SECTION 3 HARDWARE USER'S MANUAL The 0 resistors are not installed in the default configuration because it may conflict with the EAGLE module. Signal Input Output VME Connector P2 Description TXD- Transmit Data RTS- Request to Send CTS+ Clear to Send RXD+ Receive Data TXD+...
  • Page 110 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-12: Location Diagram of the 0 Resistors R563 to R569 3-40...
  • Page 111 SECTION 3 HARDWARE USER'S MANUAL Figure 3-13: RS422/RS485 Connection between DUSCC1 and VMEbus Connector P2 DUSCC FH003 68562 VMEbus P2 CHANNEL RXD+ RXD- Pin No. Pin No. CTS+ CTS- RTS- RTS+ OU 2 TXD- OU 1 TXD+ CT S Table 3-6: RS422/RS485 Configuration Jumperfield Settings B3, B4 B5, B6 +)))))),...
  • Page 112 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-14: RS422/RS485 Pinout of the Micro D-Sub and D-Sub Connectors A) Micro DSUB Male Connector B) Micro DSUB and DSUB Female Connectors Soldered on the CPU Board on the Adapter/Terminal Cable RS422/RS485 RS422/RS485 RXD-...
  • Page 113 SECTION 3 HARDWARE USER'S MANUAL Figure 3-15: Location Diagram of RS422/RS485 Configuration Jumperfields B3, B4, B5, and B6 3-43...
  • Page 114 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-16: Location Diagram of RS232/RS422/RS485 Driver/Receivers J20 and J21 plus Resistor Arrays J22 and J23 3-44...

  • Page 115: Rs232 And Rs422/Rs485 Driver Modules Fh002 And Fh003

    3.8.5 RS232 and RS422/RS485 Driver Modules FH002 and FH003 To save space and to be able to vary the interface, FORCE COMPUTERS has developed the RS232 and RS422/RS485 modules with the FH002 and FH003. These 21-pin SIL modules are installed with sockets so that they may be easily changed.

  • Page 116: Address Map Of The Duscc2 Registers

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.8.7 Address Map of the DUSCC2 Registers The following tables contain the complete register map of DUSCC2. Table 3-8: Serial I/O Port #3 (DUSCC2) Register Address Map Port Base Address : $FF802200 Address Offset Reset Mode...
  • Page 117 SECTION 3 HARDWARE USER'S MANUAL Table 3-9: Serial I/O Port #4 (DUSCC2) Register Address Map Port Base Address : $FF802220 Address Offset Reset Mode Label Description Value $FF802220 DUSCMR1 Channel Mode Reg 1 $FF802221 DUSCMR2 Channel Mode Reg 2 $FF802222 DUSSS1R SYN1/Secondary Adr Reg 1 $FF802223 DUSS2R...

  • Page 118: Rs232 Hardware Configuration Of Ports #3 And #4

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Table 3-10: Ports #3 and #4 (DUSCC2) Common Registers Address Map Port Base Address : $FF802200 Address Offset Reset Mode Label Description Value $FF80221B DUSCMR1 Channel Mode Reg 1 $FF80221E DUSCMR2 Channel Mode Reg 2...
  • Page 119 SECTION 3 HARDWARE USER'S MANUAL Figure 3-17: Connection Between DUSCC2 and D-Sub Connector for RS232 DUSCC FH002 68562 CHANNEL Pin No. Pin No. The devices are labeled as shown in the following chart. Port # Channel Connector The location diagram of the RS232 Configuration Jumperfields is found in the figure on the next page. The default setting of the RS232 configuration jumperfield is shown in the next table.
  • Page 120 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-18: Location Diagram of RS232 Configuration Jumperfields B7 through B10 3-50...
  • Page 121 SECTION 3 HARDWARE USER'S MANUAL The following is the displayed pinout of the D-Sub connector for RS232 Configuration. Figure 3-19: RS232 Pinout of the Micro D-Sub and D-Sub Connectors A) Micro DSUB Male Connector Soldered B) Micro DSUB and DSUB Female Connectors on the Adapter/Terminal Cable on the CPU Board RS232...

  • Page 122: Cable For The Micro D-Sub Connector

    The CPU board is delivered with one 9-pin Micro D-Sub to 9-pin D-Sub Adapter Cable. Additional cables or a 9-pin Micro D-Sub to 25-pin D-Sub Adapter Cable are available by order from FORCE COMPUTERS. 3.8.10 RS422/RS485 Hardware Configuration of Port #3 and #4 The CPU board is delivered with RS232 compatible interface buffers installed on all serial I/O ports.
  • Page 123 SECTION 3 HARDWARE USER'S MANUAL Figure 3-20: Connection between DUSCC2 and Micro D-Sub Connector for RS422/RS485 TXD- TXD+ RTS- RTS+ CTS+ DUSCC FH003 CTS- 68562 RXD+ CHANNEL RXD- RXD- Pin No. Pin No. SO U The devices are labeled according to the following chart. Port # Channel Connector...
  • Page 124 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-21: Location Diagram of RS422/RS485 Configuration Jumperfields B7 through B10 3-54...
  • Page 125 SECTION 3 HARDWARE USER'S MANUAL Figure 3-22: RS422/RS485 Pinout of the Micro D-Sub and D-Sub Connectors A) Micro DSUB Male Connector B) Micro DSUB and DSUB Female Connectors Soldered on the CPU Board on the Adapter/Terminal Cable RS422/RS485 RS422/RS485 RXD- TXD- RXD- TXD+...
  • Page 126 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The following table shows the PCB locations and devices that have to be inserted according to the RS232/RS422/RS485 configuration. Table 3-13: PCB Locations for RS232/RS422/RS485 Configuration RS232 Devices RS422/RS485 Devices Port # Driver and Receiver FH002...
  • Page 127 SECTION 3 HARDWARE USER'S MANUAL Figure 3-23: Location Diagram of RS232/RS422/RS485 Driver/Receiver J25/J26 and Resistor Arrays J27/J28 3-57...

  • Page 128: Rs232 And Rs422/Rs485 Driver Modules Fh002 And Fh003

    3.8.11 RS232 and RS422/RS485 Driver Modules FH002 and FH003 To save space and to be able to vary the interface, FORCE COMPUTERS has developed the RS232 and RS422/RS485 modules with the FH002 and FH003. These 21-pin SIL modules are installed with sockets so that they may be easily changed.

  • Page 129: The Pi/T 68230

    SECTION 3 HARDWARE USER'S MANUAL 3.9 The PI/T 68230 The MC68230 Parallel Interface/Timer provides versatile double buffered parallel interfaces and an operating system oriented timer. The parallel interfaces operate in unidirectional or bidirectional modes, either 8 or 16 bits wide. The PI/T contains a 24 bit wide counter and a 5 bit prescaler. Features of the PI/T MC68000 Bus Compatible Port Modes Include: Bit I/O...

  • Page 130: Address Map Of The Pi/T1 Registers

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.9.1 Address Map of the PI/T1 Registers PI/T1 is accessible via the 8 bit local I/O bus (byte mode). The following table shows the register layout of the PI/T1. Table 3-14: PI/T1 Register Layout Default I/O Base Address: $FF80 0000...

  • Page 131: I/O Configuration Of Pi/T1

    SECTION 3 HARDWARE USER'S MANUAL 3.9.2 I/O Configuration of PI/T1 The following table lists all I/O signals connected to PI/T1. The functions of these signals are described in the corresponding chapter. Additional information is provided in the PI/T data sheet, included in Section No.

  • Page 132: Rotary Switches

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.9.3 Rotary Switches There are two rotary switches installed on the front panel of the CPU board. The position of each switch can be read in via port A of the PI/T1. The next figure outlines the front panel and the position of the rotary switches.
  • Page 133 SECTION 3 HARDWARE USER'S MANUAL Figure 3-24: CPU Board Front Panel and Rotary Switch Positions 3-63...

  • Page 134: Lock Cycles

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.9.4 Lock Cycles On the initial cycle of a line access, a retry causes the MC68040 processor to retry the bus cycle. A retry signaled during the second, third, or fourth cycle of a line transfer is recognized by the processor as a bus error, and causes the processor to abort the line transfer and start an access fault exception subroutine.

  • Page 135: Interrupt Request Signal

    SECTION 3 HARDWARE USER'S MANUAL 3.9.5 Interrupt Request Signal TOUT: The PI/T1 pin 37 is used as an interrupt request line. The 24 bit timer can generate interrupt requests at a software programmable level. This interrupt request line is connected to the IRQ #2 of the FGA-002. PIRQ: The PI/T pin 33 is used to generate an interrupt depending on the handshake lines of the PI/T.

  • Page 136: Summary Of Pi/T1

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.9.8 Summary of PI/T1 Device 68230 PI/T Access Address $FF800C00 Port Width Byte Interrupt Request Level Software programmable FGA-002 Interrupt Channel (Timer IRQ) Local IRQ #2 3-66...

  • Page 137: Address Map Of The Pi/T2 Registers

    SECTION 3 HARDWARE USER'S MANUAL 3.9.9 Address Map of the PI/T2 Registers The PI/T2 is accessible via the 8 bit local I/O bus (byte mode). The following table shows the register layout of PI/T2. Table 3-16: PI/T2 Register Layout Default I/O Base Address: $FF80 0000 Default Offset: $0000 0E00 Default Name: PI_T2 Address...

  • Page 138: I/O Configuration Of Pi/T2

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.9.10 I/O Configuration of PI/T2 The following table lists all I/O signals connected to PI/T2. The functions of these signals are described in the corresponding chapter. Additional information is provided in the PI/T data sheet, included in Section No.

  • Page 139: Memory Size Recognition

    SECTION 3 HARDWARE USER'S MANUAL 3.9.11 Memory Size Recognition PB0-PB2: From these lines, the on-board memory capacity can be read in by software. Please refer to chapter 3.2 The Shared RAM for detailed information. 3.9.12 Board Identification PB3-PB7: From these lines, the CPU board identification number can be read in by software. Every CPU board has its own number.

  • Page 140: Bit I/O Port

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.9.14 12 Bit I/O Port PA0-PA7, H1-H4: This 12 bit I/O port is routed to a 24-pin header B12 allowing flat cable connection. Eight bits are connected to PI/T2 port A and are used as inputs or outputs; the remaining four bits are connected to the PI/T2 handshake pins.
  • Page 141 SECTION 3 HARDWARE USER'S MANUAL Figure 3-25: Location Diagram of Header B12 3-71...

  • Page 142: Modlow

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.9.15 MODLOW This line is driven low by an Eagle Module if there is one inserted. Be sure to leave this pin undriven by the PI/T. If no Eagle Module is inserted and this signal is driven low the local IACK daisy chain is not closed! 3.9.16 RAM Module Configuration Signals...

  • Page 143: Timer Irq/Reset

    SECTION 3 HARDWARE USER'S MANUAL 3.9.17 Timer IRQ/Reset PC3: This line can be connected to FGA-002 LIRQ 3 or to the RESET operation via jumperfield B18. An interrupt can be requested by the PI/T timer or directly by programming this line to low, when the jumper is inserted in 2-3.

  • Page 144: Reserved Line

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.9.20 Reserved Line PC1: This line is not used. In order to retain compatibility to following versions, this line should not be used in any applications. 3.9.21 Summary of PI/T2 Device 68230 PI/T Access Address...

  • Page 145: The Real Time Clock (Rtc) 72423

    SECTION 3 HARDWARE USER'S MANUAL 3.10 The Real Time Clock (RTC) 72423 There is an RTC 72423 installed on the CPU board, containing its own battery to maintain the RTC function during power down. 3.10.1 Address Map of the RTC Registers The RTC 72423 is a four bit device.
  • Page 146 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-26: RTC Programming Example /***************************************** read RTC 72421 and load to RAM 30-Oct-87 M.S. *****************************************/ setclock(sy) register struct SYRAM *sy; register struct rtc7242 *rtc = RTC2; register long count=100000l; while(--count) { rtc->dcontrol = 1;...
  • Page 147 SECTION 3 HARDWARE USER'S MANUAL The following figure shows the location diagram of jumperfield B20 for backup supply. The default configuration uses the onboard battery. Please note that the SRAM on this CPU board is also supplied via this jumperfield. +))), +))), Battery is connected to...
  • Page 148 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 3-27: Location Diagram of the Backup Supply Jumperfield B1 and B20 3-78...

  • Page 149: Summary Of The Rtc

    SECTION 3 HARDWARE USER'S MANUAL 3.10.3 Summary of the RTC Device 72423 RTC Access Address $FF80 3000 Access Mode Byte only Supported Transfers Byte only, the upper 4 bits are to be ignored for read and write accesses Battery Type Varta CR 1/3 or equivalent Interrupt Request Level Software programmable...

  • Page 150: Function Switches And Indication Leds

    SECTION 3 HARDWARE USER'S MANUAL 4. FUNCTION SWITCHES AND INDICATION LEDs The following paragraphs describe all switches and indicator LEDs. Figure 4-1 shows the front panel of the CPU board. 4.1 RESET Function Switch A reset of all on-board I/O devices and the CPU is performed if the RESET switch is pushed to the "UP" position.

  • Page 151: Run" Led

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 4.3 "RUN" LED The first LED below the RESET and ABORT switch is the RUN LED. This bicolor LED is green if the processor is not in HALT state. It is red during the RESET phase, and when the processor is in HALT state.
  • Page 152 SECTION 3 HARDWARE USER'S MANUAL Figure 4-1: Front Panel of the CPU Board...
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  • Page 154: The Cpu Board Interrupt Structure

    SECTION 3 HARDWARE USER'S MANUAL 5. THE CPU BOARD INTERRUPT STRUCTURE All interrupts on the CPU board are handled via the FGA-002 or the hardware which is controlling the FLXibus. The interrupts of the FLXibus and the interrupts handled by the FGA-002 are daisy chained. If an interrupt occurs on the FLXibus with the same priority as an interrupt occurring through the FGA-002, the priority is as follows: Priority of the Onboard Interrupts...
  • Page 155 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The chart below shows the connection between local devices and the local interrupt request of the FGA-002. Device Base Address Function Local Interrupt FGA-002 Pin Request Number Number $FF803000 PI/T1 $FF800C00 Timer IRQ PI/T2 $FF800E00...

  • Page 156: Vmebus Interface

    SECTION 3 HARDWARE USER'S MANUAL 6. VMEBUS INTERFACE The CPU board contains a VMEbus interface which is compatible with the following standards: IEEE 1014 The VMEbus interface supports 8, 16, 32 bit, and unaligned data transfers. The extended, standard, and short I/O address modifier codes are implemented to interface to all existing VMEbus products.
  • Page 157 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Table 6-1: Data Bus Size of the VMEbus Start Address End Address Type Transfer Size XXXX XXXX* F9FF FFFF VME:A32 PROGRAMMABLE FB00 0000 FBFE FFFF VME:A24 PROGRAMMABLE FBFF 0000 FBFF FFFF VME:A16 FC00 0000 FCFE FFFF...
  • Page 158 SECTION 3 HARDWARE USER'S MANUAL Table 6-2: Defined VMEbus Transfer Cycles (D32 Mode) Transfer Type D31-D24 D23-D16 D14-D8 D7-D0 Supported Byte Byte Word Long Word Unaligned Word Unaligned Long Word A Unaligned Long Word B RMW Byte RMW Byte RMW Word RMW Long Word RMW = Read Modify Write Table 6-3: Defined VMEbus Transfer Cycles (D16 Mode)

  • Page 159: Address Modifier Implementation

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 6.1.2 Address Modifier Implementation The VMEbus defines three different Address Modifier Ranges as shown in the following table: Table 6-4: Address Ranges Mode Used Address Lines Short Form Extended Addressing A1-A31 Standard Addressing A1-A24 Short I/O A1-A15 All allowed and defined Address Modifier (AM) Codes are listed in the next table.
  • Page 160 SECTION 3 HARDWARE USER'S MANUAL Table 6-5: Address Modifier Codes Address Modifier Function Code Standard Supervisory Block Transfer Standard Supervisory Program Access Standard Supervisory Data Access Reserved Standard Privileged Block Transfer Standard Privileged Program Access Standard Privileged Data Access Reserved Reserved Reserved Reserved...
  • Page 161 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The Address Modifier Codes (cont'd) Address Modifier Function Code Standard Supervisory Block Transfer Standard Supervisory Program Access Standard Supervisory Data Access Reserved Standard Privileged Block Transfer Standard Privileged Program Access Standard Privileged Data Access Reserved...
  • Page 162 SECTION 3 HARDWARE USER'S MANUAL Table 6-6: Address Modifier Codes Used on the CPU Board Address Range Address Modifier Code XXXX XXXX* 001110 SPA VMEbus (Extended Access) 001101 SDA A32 : D32, D24, D16, D8 001010 NPA F9FF FFFF 001001 NDA FBFF 0000 111110 SPA VMEbus (Standard Access)

  • Page 163: Vmebus Slave Interface

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 6.2 VMEbus Slave Interface 6.2.1 The Access Address The onboard shared RAM of the CPU board is also accessible from the VMEbus side. Both the begin and end address are programmable in 4 Kbyte increments inside the FGA-002. The complete address decoding for the shared RAM logic is performed inside the FGA-002 Gate Array.
  • Page 164 SECTION 3 HARDWARE USER'S MANUAL The following table shows which PI/T bit belongs to which address line. A31 to A24 for FGA-002 in A24 Slave Mode PI/T1 Port B Bit Address Line The value of these bits must be programmed according to the access address inside the FGA-002. For example if the shared RAM access address for VMEbus is programmed to: Start Address $10000000 End Address $10400000...
  • Page 165 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The following table shows the function of the PI/T2 Port C bit 7. PI/T2 Port C Bit 7 Enable VMEbus Slave Accesses A32/A24 The following table shows the allowed AM Codes for VMEbus accesses to the Shared RAM.

  • Page 166: The Vmebus Interrupt Handler

    SECTION 3 HARDWARE USER'S MANUAL 6.3 The VMEbus Interrupt Handler All seven VMEbus interrupt request (IRQ) signals are connected to the interrupt handling logic on the FGA-002 Gate Array. Each of the VMEbus IRQ signals can be separately enabled or disabled. The FGA-002 Gate Array allows high end multiprocessor environment board usage with distributed interrupt handling.

  • Page 167: Vmebus Arbitration

    Prioritized Round Robin 4-Level Arbiter The arbiter modes a, b, and c above are defined in the VMEbus standard and mode d has been developed by FORCE COMPUTERS and implemented on the CPU board. The arbiter mode used is application dependent.
  • Page 168 SECTION 3 HARDWARE USER'S MANUAL The VMEbus Arbiter/Requester/Interrupter LCA has three internal registers which are one byte wide. One of the registers is used to control the VMEbus Requester and the VMEbus Arbiter. It can be accessed on address $FF803E02. Table 6-8: VMEbus Arbiter/Requester Register Layout Default I/O Base Address: $FF800000...
  • Page 169 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Request Level The control of the request level on VMEbus can be done either by software (bit 7 is set to one) or by hardware (bit 7 is set to zero). If the control of the request level is done by hardware the request level is selected via jumperfield B19. The jumpersettings for the VMEbus request levels 0 to 3 are shown in figure 6-1: Requester/Arbiter Jumperfield B19.
  • Page 170 SECTION 3 HARDWARE USER'S MANUAL Arbiter Enable/Disable The onboard VMEbus arbiter can enabled or disabled via the third jumper of jumperfield B19 (see Figure 6-1: Requester/Arbiter Jumperfield B19). The setting of the jumper can be read by software via bit 6 of the requester/arbiter register (see Table 6-9: Description of Requester/Arbiter Register Bits).
  • Page 171 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 6-1: Requester/Arbiter Jumperfield B19 Arbiter Enabled Arbiter Disabled B19 (default) Bus Request Level 3 Bus Request Level 2 Bus Request Level 1 Bus Request Level 0 6-16...
  • Page 172 SECTION 3 HARDWARE USER'S MANUAL Figure 6-2: Location Diagram of Jumperfield B19 6-17...

  • Page 173: The Vmebus Release Function

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 6.4.3 The VMEbus Release Function The CPU board contains several different software selectable bus release functions to relinquish VMEbus mastership. The Bus Release Operation is independent of whether or not the on-board arbiter is enabled and independent of the Bus Request level.

  • Page 174: Release On Bus Clear (Rbclr)

    SECTION 3 HARDWARE USER'S MANUAL 6.4.3.4 Release on Bus Clear (RBCLR) The RBCLR function allows the bus mastership release if an external arbiter asserts the BCLR* signal of the VMEbus. This function then overrides the ROR function timing limitations. The RBCLR Mode is only for CPU cycles to the VMEbus and not for DMA cycles.
  • Page 175 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Table 6-12: Bus Release Functions Function Enabled Release Every Cycle RBCLR BR(0,1,2) = 0 Timeout RBCLR BR(0,1,2) = 0 or Timeout or BCLR = 0 RBCLR X = don't care Y = cannot be disabled...

  • Page 176: The Vmebus Interrupter

    SECTION 3 HARDWARE USER'S MANUAL 6.5 The VMEbus Interrupter The VMEbus Interrupter on the CPU board can generate interrupts on the VMEbus interrupt levels IRQ1 to IRQ7. The interrupts can be generated by software. The interrupter can generate a byte wide interrupt vector which is software programmable.
  • Page 177 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Table 6-14: Description of the IRQ Generation Register Value Mode Description No function VMEbus interrupt IRQ1 Active Inactive (automatically set to zero again) VMEbus interrupt IRQ2 Active Inactive (automatically set to zero again) VMEbus interrupt IRQ3...

  • Page 178: The Sysclk Driver

    SECTION 3 HARDWARE USER'S MANUAL 6.6 The SYSCLK Driver The CPU board contains all circuities to support the SYSCLK signal. The output signal is a stable 16 MHz signal with a 50/50 high/low cycle. The driver circuitry for the SYSCLK signal has a current driver capacity of 64 [mA]. The SYSCLK signal can be enabled and disabled via a jumper setting at B13.
  • Page 179 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 6-4: Location Diagram of B13 6-24...

  • Page 180: Exception Signals

    SECTION 3 HARDWARE USER'S MANUAL 6.7 Exception Signals The VMEbus defines the signals ACFAIL, SYSFAIL, and RESET for signaling exceptions or status. The ACFAIL and the SYSFAIL signals of the VMEbus are connected to the FGA-002 Gate Array. The FGA-002 may be programmed to generate interrupts on SYSFAIL and ACFAIL. For detailed information please refer to the FGA-002 User's Manual.
  • Page 181 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 6-6: Location Diagram of Jumperfield B13 6-26...

  • Page 182: Reset Generation

    SECTION 3 HARDWARE USER'S MANUAL 6.8 RESET Generation There is an IEEE 1014 compatible SYSRESET* driver installed on the CPU board. The RESET generator circuitry is operable if the power supply VCC is at least 3 volts. The RESET signal can be asserted (low) on any one of the following conditions: Front Panel RESET switch toggled Voltage Sensor detects VCC below limit (4.8V)
  • Page 183 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 6-8: Location Diagram of Jumperfield B2 6-28...

  • Page 184: Vmebus Reset Conditions

    SECTION 3 HARDWARE USER'S MANUAL 6.8.3 VMEbus RESET Conditions 6.8.3.1 Receive RESET from VMEbus In order to receive a RESET from the VMEbus on the CPU board, jumper B13, 4-5 must be inserted. If removed, the SYSRESET signal from the VMEbus is not monitored on the CPU board. 6.8.3.2 Drive RESET to VMEbus To drive the RESET signal on the VMEbus, jumper B13, 3-6 must be inserted on the CPU board.
  • Page 185 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Figure 6-9: Location Diagram of Jumperfield B13 6-30...

  • Page 186: The Reset Instruction

    SECTION 3 HARDWARE USER'S MANUAL 6.8.4 The RESET Instruction The RESET instruction of the microprocessor is designed to reset peripherals under program control, without resetting the processor itself. This instruction is fully supported by the CPU board. The RESET instruction triggers the RESET generator and resets all peripherals on the board driving RESET to low. At this point the processor on the CPU itself will not be reset.
  • Page 187 APPENDIX TO THE HARDWARE USER'S MANUAL...
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  • Page 189 LIST OF APPENDICES SPECIFICATION OF THE CPU BOARD MEMORY MAP OF THE CPU BOARD ADDRESS ASSIGNMENT AND REGISTER LAYOUT OF THE I/O DEVICES PIN ASSIGNMENTS OF THE EPROM SOCKETS Pin Assignment for EPROM Area CIRCUIT SCHEMATICS OF CPU BOARD Circuit Schematics of DRM-01 Circuit Schematics of SRM-10 DEFAULT JUMPER SETTINGS ON THE CPU BOARD CONNECTOR PIN ASSIGNMENT...
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  • Page 191 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX A SPECIFICATIONS OF THE CPU BOARD CPU Type 68040 CPU Clock Frequency CPU-40B/x 25.0 MHz CPU-40D/x 33.0 MHz Shared DRAM Capacity with Parity CPU-40X/4 4 Mbytes CPU-40X/16 16 Mbytes CPU Clock Frequency CPU-41B/x 25.0 Mhz CPU-41D/x...
  • Page 192 SYS68K/CPU-40/41 FORCE COMPUTERS SPECIFICATIONS OF THE CPU BOARD CONTINUED Power Requirements +5V min/min 5.2A/6.0A +12V min/max 0.1A/0.3A -12V min/max 1.0A/0.3A 0 to +50 - C Operating Temperature with Forced Air Cooling Storage Temperature -40 to +85C Relative Humidity (noncondensing) 0 to 95% Board Dimensions 234x160mm/9.2x6.3in...
  • Page 193 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX B MEMORY MAP OF THE CPU BOARD Start Type Address Address 00000000 003FFFFF Shared Memory (4 Mbyte) 00000000 007FFFFF Shared Memory (8 Mbyte) or 00000000 00FFFFFF Shared Memory (16 Mbyte) 00400000 F9FFFFFF VMEbus Addresses (4 Mbyte Shared Memory) A32: D32, D24, D16, D8...
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  • Page 195 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX C ADDRESS ASSIGNMENT AND REGISTER LAYOUT OF THE I/O DEVICES Serial I/O Port #1 (DUSCC1) Register Layout Port Base Address: $FF802000 Address Offset Reset Mode Label Description Value $FF802000 DUSCMR1 Channel Mode Reg 1 $FF802001 DUSCMR2 Channel Mode Reg 2...
  • Page 196 SYS68K/CPU-40/41 FORCE COMPUTERS Serial I/O Port #2 (DUSCC1) Register Layout Port Base Address: $FF802000 Address Offset Reset Mode Label Description Value $FF802020 DUSCMR1 Channel Mode Reg 1 $FF802021 DUSCMR2 Channel Mode Reg 2 $FF802022 DUSSS1R SYN1/Secondary Adr Reg 1 $FF802023...
  • Page 197 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL Serial I/O Port #3 (DUSCC2) Register Address Map Port Base Address : $FF802200 Address Offset Reset Mode Label Description Value $FF802200 DUSCMR1 Channel Mode Reg 1 $FF802201 DUSCMR2 Channel Mode Reg 2 $FF802202 DUSSS1R SYN1/Secondary Adr Reg 1...
  • Page 198 SYS68K/CPU-40/41 FORCE COMPUTERS Serial I/O Port #4 (DUSCC2) Register Address Map Port Base Address : $FF802220 Address Offset Reset Mode Label Description Value $FF802220 DUSCMR1 Channel Mode Reg 1 $FF802221 DUSCMR2 Channel Mode Reg 2 $FF802222 DUSSS1R SYN1/Secondary Adr Reg 1...
  • Page 199 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL PI/T1 Register Layout Default I/O Base Address: $FF80 0000 Default Offset: $0000 0C00 Default Name: PI_T1 Address Offset Reset Label Description Value FF800C00 PIT1 PGCR Port General Control Register FF800C01 PIT1 PSRR Port Service Request Register FF800C02 PIT1 PADDR...
  • Page 200 SYS68K/CPU-40/41 FORCE COMPUTERS PI/T2 Register Layout Default I/O Base Address: $FF80 0000 Default Offset: $0000 0E00 Default Name: PI_T2 Address Offset Reset Label Description Value FF800E00 PIT2 PGCR Port General Control Register FF800E01 PIT2 PSRR Port Service Request Register FF800E02...
  • Page 201 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL RTC Register Layout Default I/O Base Address: $FF80 0000 Default Offset: $0000 3000 Default Name: RTC Address Offset Label Description FF803000 RTC1SEC 1 Second Digit Register FF803001 RTC10SEC 10 Second Digit Register FF803002 RTC1MIN 1 Minute Digit Register...
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  • Page 203 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX D PIN ASSIGNMENTS OF THE EPROM SOCKETS Pin Assignment for EPROM Area...
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  • Page 205 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX E CIRCUIT SCHEMATICS OF CPU BOARD...
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  • Page 207 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL E.1 Circuit Schematics of DRM-01...
  • Page 208 SYS68K/CPU-40/41 FORCE COMPUTERS This page was intentionally left blank...
  • Page 209 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL E.2 Circuit Schematics of SRM-01...
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  • Page 211 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX F DEFAULT JUMPER SETTINGS ON THE CPU BOARD The following are the default jumper settings and a location diagram displaying all jumpers. Default Jumper Settings for the CPU Jumperfield Description Default Schematics Connection Reset Voltage Sensor...
  • Page 212 SYS68K/CPU-40/41 FORCE COMPUTERS Default Jumper Settings for VMEbus Jumperfield Description Default Schematics Connection Four level Arbiter Request Level SYSCLK SH10 SYSFAIL Drive VMEbus RESET Receive VMEbus RESET Default Jumper Settings for Test Jumperfield Description Default Schematics Connection Clock Signal to CPU...
  • Page 213 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL Location Diagram for All Jumperfields...
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  • Page 215 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX G CONNECTOR PIN ASSIGNMENTS OF CPU BOARD G.1 VMEbus/P1 Pin Assignments ROW A ROW B ROW C NUMBER SIGNAL SIGNAL SIGNAL MNEMONIC MNEMONIC MNEMONIC BBSY* BCLR* ACFAIL* BG0IN* BF0OUT* BG1IN* BG1OUT* BG2IN* BG2OUT* SYSCLK...
  • Page 216 SYS68K/CPU-40/41 FORCE COMPUTERS G.2 VMEbus/P2 Pin Assignments ROW A ROW B ROW C NUMBER SIGNAL SIGNAL SIGNAL MNEMONIC MNEMONIC MNEMONIC RESERVED EAGLE Module dependent EAGLE Module dependent or serial I/O interface if these pins are not used by an EAGLE module and...
  • Page 217 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX H GLOSSARY OF VME/1014 TERMS A type of module that provides or decodes an address on address line A01 through A15. A type of module that provides or decodes an address on address lines A01 through A23. A type of module that provides or decodes an address on address lines A01 through A31.
  • Page 218 SYS68K/CPU-40/41 FORCE COMPUTERS ARBITRATION BUS One of the four buses provided by the 1014 backplane. This bus allows an ARBITER module and several REQUESTOR modules to coordinate use of the DTB. ARBITRATION CYCLE An ARBITRATION CYCLE begins when the ARBITER senses a bus request. The ARBITER grants the bus to a REQUESTOR, which signals that the DTB is busy.
  • Page 219 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL BLOCK WRITE CYCLE A DTB cycle used to transfer a block of 1 to 256 bytes from a MASTER to a SLAVE. The block write cycle is very similar to the block read cycle. It uses a string of 1, 2, or 4 byte data transfers and the MASTER does not release the DTB until all of the bytes have been transferred.
  • Page 220 SYS68K/CPU-40/41 FORCE COMPUTERS A MASTER that sends and receives data 16 bits at a time over D00-D15, or A SLAVE that sends and receives data 16 bits at a time over D00-D15, or an INTERRUPT HANDLER that receives 16 bit STATUS/IDs over D00-D15, or an INTERRUPTER that sends 16 bit STATUS/IDs over D00-D15.
  • Page 221 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL FUNCTIONAL MODULE A collection of electronic circuitry that resides on one 1014 board and works together to accomplish a task. IACK DAISY CHAIN DRIVER A functional module which activates the interrupt acknowledge daisy chain whenever an INTERRUPT HANDLER acknowledges an interrupt request.
  • Page 222 SYS68K/CPU-40/41 FORCE COMPUTERS LOCATION MONITOR A functional module that monitors data transfers over the DTB in order to detect accesses to the locations it has been assigned to watch. When an access occurs to one of these assigned locations, the LOCATION MONITOR generates an on-board signal.
  • Page 223 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL REQUESTOR A functional module that resides on the same board as a MASTER or INTERRUPT HANDLER and requests use of the DTB whenever its MASTER or INTERRUPT HANDLER needs it. SERIAL CLOCK DRIVER A functional module that provides a periodic timing signal that synchronizes operation of the VMSbus.
  • Page 224 SYS68K/CPU-40/41 FORCE COMPUTERS SYSTEM CONTROLLER BOARD A board which resides in slot 1 of a 1014 backplane and has a SYSTEM CLOCK DRIVER, a DTB ARBITER, an IACK DAISY CHAIN DRIVER, and a BUS TIMER. Some also have a SERIAL CLOCK DRIVER, a POWER MONITOR or both.
  • Page 225 SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX I LITERATURE REFERENCE Please refer to the following books for more detailed information. MC 68040 Users Manual VMEbus Standards: 2618 S Shannon Tempe Arizona 85282 (602) 966-5936...
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  • Page 227 APPENDIX TO THE HARDWARE USER'S MANUAL APPENDIX J PRODUCT ERROR REPORT ALTHOUGH FORCE COMPUTERS HAS ACHIEVED A VERY HIGH STANDARD OF QUALITY IN PRODUCTS AND DOCUMENTATION, SUGGESTIONS FOR IMPROVEMENT ARE ALWAYS WELCOME. ANY FEEDBACK YOU CARE TO OFFER WOULD BE APPRECIATED.
  • Page 228 COPIES OF DATA SHEETS...
  • Page 229 COPIES OF DATA SHEETS RTC 72423 DUSCC 68562 PI/T 68230...
  • Page 230 USERS NOTES...
  • Page 231 USERS NOTES...
  • Page 232 USERS NOTES...
  • Page 233 OPTIONS/APPLICATIONS/MODIFICATIONS...
  • Page 234 INTRODUCTION TO VMEPROM IN USE WITH THE SYS68K/CPU-40/41...
  • Page 235 TABLE OF CONTENTS GENERAL ............. General Information .
  • Page 236 LIST OF TABLES Table 1: RAM Disk Usage ............Table 2: Program After Reset .

  • Page 237: General

    SECTION 7 INTRODUCTION TO VMEPROM 1. GENERAL 1.1 General Information This CPU board operates under the control of VMEPROM, an EPROM resident real time multiuser multitasking monitor program. VMEPROM provides the user with a debugging tool for single and multitasking real time applications. This manual describes those parts of VMEPROM which pertain to the hardware of the CPU.

  • Page 238: Features Of Vmeprom

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Features of VMEPROM cont'd Complete task management. I/O redirection to files or ports from the command line. Over 100 system calls to the kernel supported. Data conversion and file management functions. Task management system calls in addition to terminal I/O functions.

  • Page 239: Front Panel Switches

    SECTION 7 INTRODUCTION TO VMEPROM 1.4 Front Panel Switches 1.4.1 RESET Switch Pressing the RESET switch on the front panel causes all programs to terminate immediately and resets the processor and all I/O devices. When the VMEPROM kernel is started, it overwrites the first word in the user memory after the task control block with an EXIT system call.
  • Page 240 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The following describes the software definition for every switch: Upper Rotary Switch (SW2): Bit 3: If no EAGLE-01C is installed, this bit defines whether the Management Entity (ME) is to be started. In other words, if this bit is set to "1", the driver for all devices on the EAGLE module which are usable from VMEPROM will be installed.
  • Page 241 SECTION 7 INTRODUCTION TO VMEPROM Lower Rotary Switch (SW1): Bit 3: These two bits define which program is to be invoked after reset. Please refer to Table 2 for a detailed description. Bit 2: Bit 1: If this switch is "0", VMEPROM tries to execute a startup file after reset. The default filename is SY$STRT.
  • Page 242 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Table 1: RAM Disk Usage Bit 1 Bit 0 Upper Switch (SW2) RAM DISK AT TOP OF MEMORY (32 Kbytes) RAM DISK AT $FFC81000 (64 Kbytes) RAM DISK AT $40700000 (512 Kbytes) RAM DISK AT $40800000 (512 Kbytes)
  • Page 243 SECTION 7 INTRODUCTION TO VMEPROM Table 4: Examples in Using the Rotary Switches Rotary Switches Description Upper Lower The Management Entity (ME) is started if an EAGLE is not installed. No RAM Disk initialization will be done. The VMEbus data size is 32 bits. The RAM Disk is on top of memory.

  • Page 244: Default Memory Usage Of Vmeprom

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 1.4.4 Default Memory Usage of VMEPROM By default, VMEPROM uses the following memory assignment for the CPU board: MAIN MEMORY LAYOUT Start address End address Type $00000000 $000003FF Vector Table $00000400 $00000FFF System Configuration Data...

  • Page 245: Default Eprom Usage Of Vmeprom

    SECTION 7 INTRODUCTION TO VMEPROM 1.4.5 Default EPROM Usage of VMEPROM MEMORY LAYOUT OF THE SYSTEM EPROM 64444444444444444444444444444444444444444444444447 $FF000000 Initial Supervisor Stackpointer K))))))))))))))))))))))))))))))))))))))))))))))))M $FF000004 5))))))), Initial Program Counter K))))))))))))))))))))))))))))))))))))))))))))))))M $FF000008 5))))), * Pointer to VMEPROM Initialization K))))))))))))))))))))))))))))))))))))))))))))))))M $FF00000C 5))), * * Pointer to User Alterable Memory Locations K))))))))))))))))))))))))))))))))))))))))))))))))M * * *...
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  • Page 247: Details Of The Cpu Board

    SECTION 7 INTRODUCTION TO VMEPROM 2. DETAILS OF THE CPU BOARD 2.1 EPROM/RAM Layout Address Device 0000 0000 Local RAM ..* FF00 0000 EPROM Area FF7F FFFF FFC0 0000 SRAM Area FFC7 FFFF FFC8 0000 FLASH EPROM Area FFCF FFFF FFE0 0000 EPROM Area FFEF FFFF...

  • Page 248: On-Board I/O Devices

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.2 On-board I/O Devices 2.2.1 Base addresses of onboard I/O devices Table 5: On-board I/O Devices BASE ADDRESS DEVICE $FF803000 RTC 72423 $FF802000 DUSCC1 68562 $FF802200 DUSCC2 68562 $FF800C00 PI/T1 68230 $FF800E00 PI/T2 68230 $FFD00000...

  • Page 249: Base Addresses Of Eagle Module Devices

    SECTION 7 INTRODUCTION TO VMEPROM 2.2.2 Base Addresses of EAGLE Module Devices Because of the flexibility of the EAGLE module concept, the EAGLE Module ID-EPROM holds offsets for I/O device addresses. The complete I/O device base address is calculated as a base address provided by VMEPROM plus an offset.

  • Page 250: On-Board Interrupt Sources

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 2.3 On-board Interrupt Sources The following table shown is used for the on-board interrupt sources and levels which are defined by VMEPROM. All interrupt levels and vectors of the onboard I/O devices are software programmable via the FGA-002 Gate Array.

  • Page 251: Off-Board Interrupt Sources

    SECTION 7 INTRODUCTION TO VMEPROM 2.4 Off-board Interrupt Sources VMEPROM supports several VMEbus boards. As these boards are interrupt driven the level and vectors must be defined for VMEPROM to work properly. The following table shows the default setup of the interrupt levels and vectors of the supported hardware. For a detailed description of the hardware setup of the boards, please refer to the Appendix of this manual.
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  • Page 253: Concept Of Vmeprom

    SECTION 7 INTRODUCTION TO VMEPROM 3. CONCEPT OF VMEPROM 3.1 Getting Started After power-up or after RESET has been pressed, VMEPROM prints a banner showing the version and revision being used and prints the prompt ("? "). If the above message does not appear, check the following: Baud rate and character format setting of the terminal (default upon delivery of the CPU board is 9600 Baud, 8 data bits, 1 stop bit, no parity).

  • Page 254: Vmeprom Commands

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 3.3 VMEPROM Commands VMEPROM supports many commands. All of these commands are EPROM resident and are available at any time. Most of these commands are common for all versions of VMEPROM. All the common commands of VMEPROM are described in detail in the VMEPROM User's Manual. Those commands which are specific for the hardware of the CPU board are described in the following paragraphs of this manual.

  • Page 255: Special Vmeprom Commands For Cpu Board

    SECTION 7 INTRODUCTION TO VMEPROM 4. SPECIAL VMEPROM COMMANDS FOR CPU BOARD The following commands are implemented on the CPU board in addition to those listed in the VMEPROM User's Manual. 4.1 ARB - Set the Arbiter of the CPU Board Format: The ARB command allows the user to set the arbitration mode of the CPU board for VMEbus.

  • Page 256: Config - Search Vmebus For Hardware

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 4.2 CONFIG - Search VMEbus for Hardware Format: CONFIG This command searches the VMEbus for available hardware. It is useful if VMEPROM is started and bit 0 of the lower rotary switch on the front panel is set to "1", so that VMEPROM does not check the configuration by default.

  • Page 257: Fga - Change Boot Setup For Gate Array

    SECTION 7 INTRODUCTION TO VMEPROM 4.3 FGA - Change Boot Setup for Gate Array Format: Some registers of the gate array are definable by the user. The contents of this register are stored in the onboard battery SRAM in a short form. The boot software for the gate array will take these values after reset to initialize the gate array.

  • Page 258: Flush - Set Buffered Write Mode

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 4.4 FLUSH - Set Buffered Write Mode 4.4.1 EAGLE-01C Module Format: FLUSH FLUSH ? FLUSH ON FLUSH OFF This command flushes all modified hashing buffers for disk write or enable/disable buffered write mode for the local SCSI controller.

  • Page 259: Eagle Modules Together With The Management Entity (Me)

    SECTION 7 INTRODUCTION TO VMEPROM 4.4.2 EAGLE Modules together with the Management Entity (ME) Format: FLUSH FLUSH <disk number>, <time> The first command flushes all buffers on all disks in the system. The second command sets a flush time for the device driver task. The device driver task has to flush its buffers periodically every <time>...

  • Page 260: Fmb - Force Message Broadcast

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 4.5 FMB - Force Message Broadcast Format: FMB <slotlist>,<FMB channel>,<message> FMB [<FMB channel>] The FMB command allows sending a byte message to individual slots in the backplane, broadcast to all the boards, and getting a pending message.

  • Page 261: Functional - Perform Functional Test

    4.6 FUNCTIONAL - Perform Functional Test Format: FUNCTIONAL NOTE: This command is not designed for the user, but instead for internal purposes by FORCE COMPUTERS. 4.7 MEM - Set Data Bus Width of the VMEbus Format: MEM 16 MEM 32 This command can display or set the data bus width of the CPU board on the VMEbus.

  • Page 262: Prog - Program Flash Eprom

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 4.8 PROG - Program FLASH EPROM Format: PROG [<source>[,<destination>[,<length>[,<width>]]]] This command is used to program FLASH EPROMs. All parameters may be specified on the command line or may be entered interactively after the function has been invoked.

  • Page 263: Selftest - Perform On-Board Selftest

    SECTION 7 INTRODUCTION TO VMEPROM 4.9 SELFTEST - Perform On-board Selftest Format: SELFTEST This command performs a test of the on-board functions of the CPU board. It may only be run if no other tasks are created. If there are any other tasks no selftest will be made and an error will be reported.
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  • Page 265 SECTION 7 INTRODUCTION TO VMEPROM 5. INSTALLING A NEW HARD DISK The hard disk must be set to 256 bytes per block. The FRMT command of VMEPROM may be used to set all hard disk parameters, to format the Winchester and to divide the disk into logical partitions. Before starting the FRMT command, the number of the last logical block of the Winchester must be known.
  • Page 266 (cont'd) W0 Parameters Menu: A)lter, D)isplay, R)ead file, Q)uit Command: Q W0 Main Menu: 1)Parm 2)BadT 3)Form 4)Veri 5)Part 6)Writ P)Togl Q)Quit Command: 3 Sector Interleave = 0 Physical Tracks to FORMAT = 0,10219 Ready to FORMAT Winchester Drive 0 ? Y Sector Interleave Table: 0,1,2,3,4,5,6,7,8,9,10,11,12, 13,14,15,16,17,18,19,20,21,22,...
  • Page 267 SECTION 7 INTRODUCTION TO VMEPROM (cont'd) W0 Partitions Menu: A)lter, D)isplay, R)ecalc, Q)uit Command: Q W0 Main Menu: 1)Parm 2)BadT 3)Form 4)Veri 5)Part 6)Writ P)Togl Q)Quit Command: 6 Write to Disk Y)es, N)o, F)ile : Y Write to file (Y/N)?N W0 Main Menu: 1)Parm 2)BadT 3)Form 4)Veri 5)Part 6)Writ P)Togl Q)Quit Command: Q...
  • Page 268 APPENDIX TO THE INTRODUCTION TO VMEPROM...
  • Page 269 VMEbus Board Setup ..........VMEbus Memory .

  • Page 270: Vmebus Board Setup

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX A A. VMEbus Board Setup This appendix summarizes the changes to be made to the default setup of additional VMEbus boards so that they are VMEPROM compatible. Appendices A.2 through A.6 are available in EPROM, but are not installed.

  • Page 271: A2. Sys68K/Sio-1/Sio-2

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS A2. SYS68K/SIO-1/SIO-2 These two serial I/O boards are set to the base address $B00000 by default. VMEPROM expects the first SIO-1/SIO-2 boards at $FCB00000. This is in the standard VME address range (A24, D16, D8) with the address $B00000.

  • Page 272: A3. Sys68K/Isio-1/2

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM VMEPROM supports up to two serial I/O boards. These can be either the SIO-1/2 board, the ISIO-1/2 board, or a mixture of both. Please note that the first board of every type must be set to the first base address.

  • Page 273: Sys68K/Iscsi-1 Disk Controller

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS SIO-1 $FCB00000 ISIO-1 $FC960000 A4. SYS68K/ISCSI-1 Disk Controller VMEPROM supports up to two floppy disk drives and three Winchester disk drives together with the ISCSI-1 disk controller. The floppy drives must be jumpered to drive select 3 and 4 and can be accessed as disk number 0 and 1 out of VMEPROM.

  • Page 274: Local Fdc And Scsi Controller

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM A5. Local FDC and SCSI Controller NOTE: The following chapter only applies to those CPU boards which contain an installed EAGLE-01C Module. VMEPROM supports up to two floppy disk drives and three Winchester disk drives together with the local FDC and SCSI Controller.

  • Page 275: A6. Boards With A Running Management Entity (Me

    SYS68K/CPU-39 USER'S MANUAL FORCE COMPUTERS A6. Boards with a running Management Entity (ME) Four drivers are included in VMEPROM which manage the communication with the ME, two disk drivers and two UART drivers. Two of each type are necessary because one controls the onboard EAGLE module(s) and the other controls offboard modules.

  • Page 276: Offboard Eagle Modules

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM A6.1.2 Offboard EAGLE Modules To install the UART driver, type: ? INSTALL U8,$FF008410 Now the driver searches for up to 21 boards in the system if there is a ME running on it. Every serial device is installed.

  • Page 277: A6.2 Disk Driver

    SYS68K/CPU-39 USER'S MANUAL FORCE COMPUTERS After the INSTALL command the driver knows 12 serial channels. Logical Address UART $84000000 RAM port of the first IBC-20 $00000001 The first serial channel of the first IBC $00000002 The second serial channel of the first IBC-20...

  • Page 278: S-Record Formats

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX B B. S-Record Formats B1. S-Record Types Eight types of S-records have been defined to accommodate the needs of the encoding, transportation and decoding functions. VMEPROM supports S0, S1, S2, S3, S7, S8 and S9 records (S7 and S8 on load only). An S-record format module may contain S-records of the following types: The header record for each block of S-records.

  • Page 279: S-Record Example

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS B2. S-Record Example S214020000000004440002014660000CB241F8044CB1 S214020010203C0000020E428110C1538066FA487AE4 S214020020001021DF0008487A001221DF000C4E750E S21402003021FC425553200030600821FC41444452C2 XX.- Check-sum  XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Data  0200XX 24 bit Address  Byte Count  Record Type S9030000FC  Check-sum  0000 Data  Byte Count  Record Type...
  • Page 280 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX C C. System RAM Definitions /* SYRAM:H -- DEFINITION OF SYRAM BLOCK OF MEMORY 05-Jan-88 Revised to correspond to PDOS 3.3 BRIAN C. COOPER, EYRING RESEARCH INSTITUTE, INC. Copyright 1985-1988 #define /* number of tasks #define ((NT+3)&0xFC)

  • Page 281: System Ram Definitions

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS C. System RAM Definitions (cont'd) /*078*/ char _evtb[10]; /* 0-79 event table /*082*/ char _evto[2]; /* 80-95 output events /*084*/ char _evti[2]; /* 96-111 input events /*086*/ char _evts[2]; /* 112-127 system events /*088*/ char _ev128[16];...
  • Page 282 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX D D. Task Control Block Definitions #define MAXARG /* max argument count of the cmd line #define MAXBP /* max 10 breakpoints #define MAXNAME /* max 5 names in name buffer #define TMAX /* Max number of tasks #define ARGLEN...

  • Page 283: Task Control Block Definitions

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS D. Task Control Block Definitions (cont'd) /*40A*/ long _trc; /* trace vector /*40E*/ long _fpa[2]; /* floating point accumulator /*416*/ long *_fpe; /* fp error processor address /*41A*/ char *_clp; /* command line pointer /*41E*/ char *_bum;...
  • Page 284 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM D. Task Control Block Definitions (cont'd) /*654*/ WORD bpocc[MAXBP]; /* # of times the breakpoint should be /* skipped /*668*/ WORD bpcocc[MAXBP]; /* # of times the breakpoint is already /* skipped /*67C*/ LWORD bptadr;...
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  • Page 286: Interrupt Vector Table Of Vmeprom

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX E E. Interrupt Vector Table of VMEPROM Vector Vector Number/s Assignment Reset: Initial Interrupt Stack Pointer Reset: Initial Program Counter Bus Error Address Error Illegal Instruction Zero Divide CHK, CHK2 Instruction FTRAPcc, TRAPcc, TRAPV Instructions Privilege Violation Trace...
  • Page 287 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS cont'd..Vector Vector Assignment Number/s < User Defined THROUGH Disk Interrupt Vector < User Defined THROUGH < Vector numbers for up to 4 FC68165s THROUGH Mailbox 0 (Used from the ME) Mailbox 1 Mailbox 2...

  • Page 288: Benchmark Source Code

    APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX F F. Benchmark Source Code *************************************************************** ** Module name: Assembler benchmarks Version: 1.0 ** date started: 20-Apr-87 M.S. last update: 23-Apr-87 M.S. ** Copyright (c) 1986/87 FORCE Computers GmbH Munich *************************************************************** section 0 alt,P=68020,P=68881 xdef .benchex xdef .BEN1BEG,.BEN1END xdef .BEN2BEG,.BEN2END...
  • Page 289 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS (cont'd) * BENCH #3: SUBSTRING CHARACTER SEARCH 100.000 TIMES TAKEN FROM EDN 08/08/85 MOVE.L #100000,D4 @002 MOVE.L #15,D0 MOVE.L #120,D1 LEA.L EDN1DAT(PC),A1 LEA.L EDN1DAT1(PC),A0 BSR.S EDN1 SUBQ.L #1,D4 BNE.S @002 ****** BEGIN EDN BENCH #1 ******* EDN1 MOVEM.L D3/D4/A2/A3,-(A7)
  • Page 290 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM (cont'd) MOVEQ.L #1,D0 MOVEQ.L #11,D1 BSR.S EDN2 MOVEQ.L #1,D0 MOVE.W #123,D1 BSR.S EDN2 MOVEQ.L #3,D0 ; RESET MOVEQ.L #10,D1 BSR.S EDN2 MOVEQ.L #1,D0 MOVEQ.L #11,D1 BSR.S EDN2 MOVEQ.L #1,D0 MOVE.W #123,D1 BSR.S EDN2 SUBQ.L #1,D4...
  • Page 291 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS (cont'd) EDN3 MOVEM.L D1-D7,-(A7) MOVE.L D1,D2 MOVE.W D0,D7 SUBQ.W #2,D7 @010 ADDQ.L #1,D1 MOVE.L D1,D3 ADD.L D0,D2 MOVE.L D2,D4 @020 BFEXTU (A0){D3:1},D5 BFEXTU (A0){D4:1},D6 BFINS D5,(A0){D4:1} BFINS D6,(A0){D3:1} ADD.L D0,D3 ADDQ.L #1,D4 CMP.L D3,D4 BNE.S...
  • Page 292 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM (cont'd) * BENCH #8: FLOATING POINT 1.000.000 SINUS MOVE.L #1000000,D5 FMOVE.L #1,FP1 @010 FSIN.X SUBQ.L #1,D5 BNE.S @010 PAGE * BENCH #9: FLOATING POINT 1.000.000 MULTIPLICATIONS MOVE.L #1000000,D5 FMOVE.L #1,FP0 FMOVE.L #1,FP1 @010 FMUL.X FP0,FP1...
  • Page 293 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS (cont'd) * PDOS BENCHMARK #4: SEND TASK MESSAGE CLR.L ;SELECT TASK #0 LEA.L MES01(PC),A1 ;POINT TO MESSAGE MOVE.L #100000,D6 @000 XSTM ;SEND MESSAGE XKTM ;READ MESSAGE BACK SUBQ.L #1,D6 ;DONE? BGT.S @000 MES01 DC.B 'BENCH #13',0...

  • Page 294: Special Locations

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX G G. Special Locations The following table describes some special locations in the EPROM. These locations define the default setup of the name of the startup file, user program location and RAM disk addresses. These options can be selected by front panel switches.
  • Page 295 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The address of the following table is located at address $C relative to the beginning of the EPROM): Offset Size Default Description DS.B 22 'SY$STRT',0 Name of the startup file. It has to be a 0-terminated string.

  • Page 296: Generation Of Applications In Eprom

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX H H. Generation of Applications in EPROM H1. General Information In general, there are three ways to bind an application program in EPROMs to the VMEPROM kernel. In all cases the application program is executed in user mode. The XSUP system call can be used to switch to supervisor mode.
  • Page 297 SYS68K/CPU-39 USER'S MANUAL FORCE COMPUTERS b. Keep All Setups: To keep all setups the user program can be put into EPROM at an address which is located in address $10 relative to the EPROM start address (real address $FF000010). In this case, the front panel switches are defined as described in the "Introduction to VMEPROM".

  • Page 298: Introduction To The Ram Port

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX I I. Introduction to the RAM Port The Management Entity provides a RAM port accessible through the Application Command Interface and can be used as an character oriented input/output port of any VMEPROM task running on the same board as the Management Entity.

  • Page 299: Acquire The Ram Port

    SYS68K/CPU-39 USER'S MANUAL FORCE COMPUTERS I.1.1 Acquire the RAM port The OPEN command requests the establishment of a logical connection between an application and the RAM port; the appropriate Command Control Buffer is structured as presented in Figure 1 .

  • Page 300: Reading Data From The Ram Port

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM I.1.2 Reading Data from the RAM port The READ command initiates a data exchange between the character oriented RAM port and an application and the data is transferred from the RAM port to an application. The Command Control Buffer to read data from the RAM port is structured as described in Figure 5 .

  • Page 301: Writing Data To The Ram Port

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS I.1.3 Writing Data to the RAM port The WRITE command initiates a data exchange between the character oriented RAM port and an application and the data is transferred from the application to the RAM port.

  • Page 302: Accessing The Ram Port From Vmeprom

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM I.2 Accessing the RAM Port from VMEPROM VMEPROM is equipped with a UART driver to exchange data via the RAM port and to alter the operating mode of the RAM port. This RAM port UART driver is constructed like all other standard VMEPROM (PDOS) UART drivers and thus provides the same functions.
  • Page 303 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS reserved for the VMEPROM kernel's internal purpose F: reserved for the VMEPROM kernel's internal purpose Figure 4: RAM Port UART Driver's 'port' Flags...

  • Page 304: The Internal Structure Of The Ram Port

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM I.3 The Internal Structure of the RAM Port The RAM port provided by the Management Entity consists of an internal 32 bits width semaphore register and two 128 byte width circular buffers - the 'receive' and 'transmit' buffer - each equipped with two pointers to manage insertion and removal of data.
  • Page 305 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The RPINTR flag either causes to pass direclty a received character to the appropriate routine of the VMEPROM kernel dealing with character input, or to store the received character in the RAM port's internal receive buffer. If the RPINTR flag is cleared then all received data bytes are placed in the receive buffer as long as enough room is available in the buffer.

  • Page 306: Minimum Demands For Device Driver Tasks In Order To Run With Vmeprom

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM APPENDIX J J. Minimum Demands for Device Driver Tasks in Order to Run with VMEPROM J.1 Device Driver Tasks for Serial Devices The following commands have to be supported in order that VMEPROM works properly with the device driver task: OPEN VMEPROM executes the OPEN command with a data exchange mode of $C0000000.
  • Page 307 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS SERVICE Service codes from -1024 to -2047 are reserved for serial drivers; the codes from -1024 to -1279 are reserved for VMEPROM. Only one service code is used from VMEPROM. It is service number -1026. It has to set the UART parameter.
  • Page 308 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM service_parameter[2]: to define the number of stop bits VALUE NUMBER OF STOP BITS service_parameter[3]: to define the parity to be used VALUE PARITY even service_parameter[4]: to define the flow control to be used VALUE FLOW CONTROL...

  • Page 309: Device Driver Tasks For Block Devices

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS J.2 Device Driver Tasks for Block Devices J.2.1 Floppy Devices The following commands have to be supported in order that VMEPROM works properly with the device driver task: OPEN VMEPROM executes the OPEN command with a data exchange mode of $C0000000. Therefore, the device driver task has to support Direct Memory Access.
  • Page 310 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM READ The READ command is executed with a read mode of $80000000. Because of this the device driver task has to wait until the data is read. The parameters used are: _remnant[0]: the drive number (0 or 1) _remnant[1]: reserved (any value should be ignored) The following return values are allowed: VALUE...
  • Page 311 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS WRITE The WRITE command is executed with a write mode of $80000000. Because of this the device driver task has to wait until the data is written. The parameters used are: _remnant[0]: the drive number (0 or 1)
  • Page 312 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM CLOSE The CLOSE command is executed without any additional parameter. The return value is not used. SERVICE Service codes from -2048 to -3071 are reserved for floppy drivers; the codes from -2048 to -2303 are reserved for VMEPROM.
  • Page 313 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS service parameter[4]: number of heads (2) service parameter[5]: RW gap ($20) service parameter[6]: format gap ($36) service parameter[7]: density (1) VALUE Density High Density Double Density service parameter[8]: step rate (1) Parameters for the format floppy service:...

  • Page 314: Scsi Devices

    SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM J.2.2 SCSI Devices The following commands have to be supported in order that VMEPROM works properly with the device driver task. OPEN VMEPROM executes the OPEN command with a data exchange mode of $C0000000. Therefore, the device driver task has to support Direct Memory Access.
  • Page 315 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS READ The READ command is executed with a read mode of $80000000. Because of this the device driver task has to wait until the data is read. The parameters used are: _remnant[0]: SCSI bus ID as returned from the get device list service.
  • Page 316 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM WRITE The WRITE command is executed with a write mode of $80000000. Because of this the device driver task has to wait until the data is written. The parameters used are: _remnant[0]: SCSI bus ID as returned from the get device list service _remnant[1]: Logical block size VMEPROM uses a block size of 256 bytes.
  • Page 317 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS SERVICE Service codes from -3072 to -4095 are reserved for floppy drivers; the codes from -3072 to -3327 are reserved for VMEPROM. The following services have to be supported from the device driver task: SERVICE...
  • Page 318 SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM Parameters for the flush service: input parameter: nothing returned data: status Parameters for the transparent mode service: input parameter: service_parameter[0]: SCSI bus ID as returned from the get device list service service_parameter[1]: SCSI command (byte 0-3) service_parameter[2]: SCSI command (byte 4-7) service_parameter[3]: SCSI command (byte 8-11) service_parameter[4]: pointer to data buffer...
  • Page 319 THE APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE...
  • Page 320 This page was intentionally left blank...
  • Page 321 Table of Contents Introduction ............1-1 The Logical Devices .

  • Page 322: Introduction

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 1. Introduction Each base board equipped with one or more EAGLE module slots provides a unique software interface - called the Application Command Interface (ACI) - through which the application communicates with specific devices on the EAGLE modules. Furthermore, the interface offers the capability to gain various information about the EAGLE modules and the particular devices on the modules.
  • Page 323 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS As mentioned above the application accesses devices on an EAGLE module via a logical connection, rather than directly. Therefore, each device accessible through the Application Command Interface is identified by a unique logical device number which is provided by the interface.
  • Page 324 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE Depending on the command to be issued, the application has to prepare the first Command Control Buffer and has to set another semaphore that indicates that the Command Control Buffer is ready to be passed through the Application Command Interface.

  • Page 325: The Logical Devices

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 1.1 The Logical Devices The devices on available EAGLE modules cannot be accessed from the VMEbus directly, but the Application Command Interface provides a method to access devices on a "higher logical" level. Each device accessible through the Application Command Interface is identified by an unique "logical device number"...

  • Page 326: The Command Control Buffers

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 1.2 The Command Control Buffers As mentioned previously the Command Control Buffer is the basic data structure to issue commands through the Application Command Interface. This data structure of 256 bytes size consists of two logical parts.
  • Page 327 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The semaphores depicted in Figure 1 are defined and described in the following. The ALLOCATE semaphore indicates whether a Command Control Buffer is already acquired. If the ALLOCATE semaphore is cleared then the application may gain the ownership of the Command Control Buffer by setting this semaphore.
  • Page 328 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE long ( *ME_system_call ) ( ) This entry contains the address of a routine supplied by the Application Command Interface which provides specific services. This address is exclusively used by a device driver dealing with the device associated with the Command Control Buffer, and should not be altered by the application! struct _ccb *ccb_link This entry addresses a Command Control Buffer chained to this Command Control Buffer.

  • Page 329: The Complete Description Of All Commands Provided By The Application Command Interface

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE The Complete Description of All Commands Provided by The Application Command Interface The following subsections describe each command provided by the Application Command Interface in detail and discuss the appropriate structure of the Command Control Buffers to issue the particular command through the Application Interface, as well as the structure of the Command Control Buffer "returned"...
  • Page 330 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS _access_control_flags: The BUSY semaphore has to be set to indicate the readiness of the Command Control Buffer to be processed; all other semaphores within the Access Control Field have to be left unaffected. command: The value $00 indicates that the Command Control Buffer is used to issue the OPEN command through the Application Command Interface.
  • Page 331 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE The interrupt request level to be assigned to the particular interrupt is contained by bits 8 through 15 and has to be one of the MC680XX interrupt request levels. The Application Command Interface uses this value to set the corresponding Interrupt Control Register of the FORCE Gate Array-002 on the base board.
  • Page 332 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Table 1: The inquiry mode major and minor interrupt numbers Major Interrupt Number Minor Interrupt Number Interrupt Source VMEbus interrupt 1 VMEbus interrupt 2 VMEbus interrupt 3 VMEbus interrupt 4 VMEbus interrupt 5 VMEbus interrupt 6...
  • Page 333 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE The least significant eight bits of the response mode contain the major interrupt number and the minor interrupt number as shown in Figure 2. The major interrupt number specifies the interrupt class - one of the interrupts listed above -, whereas the minor interrupt number specifies which of the interrupts in the class is being used.
  • Page 334 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Table 2: The response mode major and minor interrupt numbers Major Interrupt Number Minor Interrupt Number Interrupt Source No interrupt, POLL mode VMEbus interrupt 1 VMEbus interrupt 2 VMEbus interrupt 3 VMEbus interrupt 4 VMEbus interrupt 5...
  • Page 335 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE data_exchange_mode: The data exchange mode defines the way the data has to be interchanged between the application and a physical device and describes the location of the data to be transferred. As shown in Figure 3 below, the most significant two bits specify the data exchange mode: the DMA semaphore specifies whether the data has to be transferred by Direct Memory Access or by the Microprocessor;...
  • Page 336 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS _remnant: This data area may be used by the device driver for additional parameters. For further information please refer to the detailed description of the device driver. When the OPEN command has been carried out the status of the completion of the command is returned through the same Command Control Buffer used to issue the command.
  • Page 337 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE ACI_E_OPEN_CCB_ALREADY_IN_USE: An attempt to establish a logical connection to a physical device is refused by the Application Command Interface due to the fact that the Command Control Buffer is already used for a logical connection to a device.
  • Page 338 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS *ccb: Addresses the Command Control Buffer allocated by the Application Command Interface. The assigned Control Buffer has to be used by the application to issue subsequent commands through the Application Command Interface. ccb_number: Contains the number of the assigned Command Control Buffer and has to be used whenever the application will gain the attention of the Application Command Interface by a FORCE Message Broadcast cycle.

  • Page 339: The Close Command

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 2.2 The CLOSE Command The CLOSE command requests to release a logical connection between the application and a physical device, and depending on the type of the physical device to reset the device. After the CLOSE command has been completed the application still owns the Command Control Buffer used to issue commands through the Application Command Interface.
  • Page 340 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS After the CLOSE command has been carried out, the status of the completion of the command is returned through the same Command Control Buffer used to issue the command. The corresponding Command Control Buffer is structured as described below.

  • Page 341: The Read Command

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 2.3 The READ Command The READ command initiates a data exchange between a device and the application. The data is transferred from a device to the application. If any data have to be read from a block oriented device then blocks of data are transferred;...
  • Page 342 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS block_number: If any data have to be read from a block oriented device then this entry specifies the number of the block where to start reading the number of blocks specified by count. In case of a character oriented device this entry is negligible.
  • Page 343 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE _remnant: This data area may be used by the device driver for additional parameters. For further information please refer to the detailed description of the device driver. When the READ command has been carried out by the device driver the completion status is returned through the same Command Control Buffer used to issue the command.
  • Page 344 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS ACI_E_INCONSISTENT_COMMAND_CHAIN: Inconsistent command chain ACI_E_BUS_ERROR: A BUS / ADDRESS ERROR occurred within a device driver. ACI_E_READ_NO_CONNECTION: The logical connection to a device does not exist For device driver dependent error codes please refer to the detailed description of the particular device driver.

  • Page 345: The Write Command

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 2.4 The WRITE Command The WRITE command initiates a data exchange between a device and the application. The data is transferred from the application to a device. If any data have to be written to a block oriented device then blocks of data are transferred;...
  • Page 346 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS block_number: If any data have to be written to a block oriented device then this entry specifies the number of the block where to start writing the number of blocks specified by count. In case of a character oriented device this entry is negligible.
  • Page 347 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE _remnant: This data area may be used by the device driver for additional parameters. For further information please refer to the detailed description of the device driver. When the WRITE command has been carried out by the device driver the status of the completion of the command is returned through the same Command Control Buffer used to issue the command.
  • Page 348 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS ACI_E_INCONSISTENT_COMMAND_CHAIN: Inconsistent command chain ACI_E_BUS_ERROR: A BUS / ADDRESS ERROR occurred within a device driver. ACI_E_WRITE_NO_CONNECTION: The logical connection to a device does not exist. For device driver dependent error codes please refer to the detailed description of the particular device driver.

  • Page 349: The Service Command

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 2.5 The SERVICE Command The SERVICE command requests special services provided by the Application Command Interface and a specific device driver. The Application Command Interface provides services to control the device driver's parameter, such as task priority etc., or to allocate additional memory which is dedicated to a logical connection;...
  • Page 350 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS service: Specifies the proper service to be carried out by the Application Command Interface or the appropriate device driver. A positive value identifies a service required of the Application Command Interface, whereas a negative value designates a service to be provided by the device driver.
  • Page 351 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE service_parameter: Depending on the required service further parameters are defined by this entry. The number and type of these parameters depend on the specific device driver. typedef struct _ccb_service_status unsigned long _access_control_flags; long ( *ME_system_call ) ( );...
  • Page 352 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS ACI_E_SERVICE_NO_CONNECTION: The logical connection to a device does not exist. ACI_E_SERVICE_NOT_SUPPORTED: Indicates that the specific device driver does not support any SERVICE command. ACI_SERVICE_UNKNOWN_SERVICE: Unknown service requested. For device driver dependent error codes please refer to the detailed description of the particular device driver.

  • Page 353: The Get Logical Device Number Service

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 2.5.1 The Get Logical Device Number Service The application has to issue the Get Logical Device Number service command to obtain a list of logical device numbers of devices of a particular type (e.g. a device that exchanges data via serial communication lines, a device that exchanges data through a parallel interface, etc.).The Application Command Interface returns a list of logical device numbers identifying all devices on the available EAGLE modules that are of the same type as specified by a parameter of the issued SERVICE command.

  • Page 354: Command Chaining

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 3. Command Chaining The Application Command Interface supports the capability to issue a sequence of commands through the interface which are executed in successive order. The commands are passed through the Application Command Interface in a chain of Command Control Buffers and each Command Control Buffer is used to issue a single command.
  • Page 355 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS Therefore, the following steps are recommended to build up a command chain: First, a logical connection has to be established between the application and a specific device using the OPEN command. When the application has established a logical connection, and has received its own Command Control Buffer through the Application Command Interface, it can issue the CCB_ALLOCATE command to acquire a specific number of Command Control Buffers.

  • Page 356: The Ccb_Allocate Command

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 3.1 The CCB_ALLOCATE Command The CCB_ALLOCATE command is used to acquire a specific number of Command Control Buffers which will be chained to the Command Control Buffer associated with the logical connection. The particular Command Control Buffer is structured as described below. typedef struct _ccb_allocate_command unsigned long...
  • Page 357 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS After the CCB_ALLOCATE command has been carried out, the status of the completion of the command in the same Command Control Buffer used to issue the command. The corresponding Command Control Buffer is structured as described below.

  • Page 358: The Ccb_Free Command

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE ACI_E_ALLOCATE_ILLEGAL_NUMBER_OF_CCBS: An illegal number of Command Control Buffers to be allocated has been specified. ACI_E_ALLOCATE_INSUFFICIENT_CCBS: No more Command Control Buffers available. ccb_number: Specifies the number of Command Control Buffers which have been allocated. *chain_head: Addresses the Command Control Buffer which is the first CCB in the chain.
  • Page 359 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS The corresponding Command Control Buffer is structured as described below. typedef struct _ccb_free_status unsigned long _access_control_flags; long ( *ME_system_call ) ( ); *ccb_link; long last_command; unsigned long _reserved[ 7 ]; long status; unsigned long reserved[ 52 ];...

  • Page 360: Error Codes

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 4. Error Codes This section lists all error codes which are returned through the Application Command Interface to indicate the fail states detected by the Application Command Interface. All error codes returned by a particular device driver, dealing with a specific device on an EAGLE module, are described in the appropriate "Firmware User's Manual"...

  • Page 361: Error Codes Related To The Close Command

    SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS 4.3 Error Codes Related To The CLOSE Command ACI_E_CLOSE_NO_CONNECTION ACI_E_CLOSE_CANNOT_DEACTIVATE_DEVICE_DRIVE 4.4 Error Code Related To The READ Command ACI_E_READ_NO_CONNECTION 4.5 Error Code Especially Related To The WRITE Command ACI_E_WRITE_NO_CONNECTION 4.6 Error Codes Related To The SERVICE Command...

  • Page 362: Error Codes Especially Related To The Ccb_Allocate Command

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 4.7 Error Codes Especially Related To The CCB_ALLOCATE Command ACI_E_ALLOCATE_ILLEGAL_NUMBER_OF_CCBS ACI_E_ALLOCATE_INSUFFICIENT_CCBS 4.8 Error Codes Especially Related To The CCB_FREE Command None...

  • Page 363: The Following Example Shows How To Communicate With The Aci

    SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE 5. The following example shows how to communicate with the ACI NOTE: This example has to run on the same board where the ACI is implemented. communication with the ACI is done in polled mode. This example is programmed to run in a PDOS environment.
  • Page 364 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS struct _ccb_sopen_status unsigned long _access_control_flags; long ( * _ME_system_call ) (); struct _ccb_t *ccb_link; long last_command; unsigned long _reserved[ 7 ]; long status; struct _ccb_t *ccb; long ccb_number; unsigned long ACI_inquiry_address; unsigned long remnant[ 49 ];...
  • Page 365 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE struct _ccb_write_command unsigned long _access_control_flags; long ( * _ME_system_call ) (); struct _ccb_t *ccb_link; long last_command; unsigned long _reserved[ 7 ]; long command; unsigned char *buffer; unsigned long count; unsigned long block_number; unsigned long write_mode;...
  • Page 366 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS call: main() in : nothing out : nothing description: 'main' first waits until the ME has written its identifier. Then, the address of the first CCB is fetched. With this CCB the ACI is asked if there is a floppy device driver task available. If yes, this task is opened.
  • Page 367 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE static void get_ccb(ccb_ptr) struct _ccb_cservice_command *ccb_ptr; { while ( XTAS((char *)&ccb_ptr->_access_control_flags) != 0 ) /* allocating the CCB with a TAS /* instruction /* end of 'get_ccb()' call: put_ccb(ccb_ptr) in : ccb_ptr -> address of CCB which is no longer used out : nothing description: put_ccb() makes the previous allocated CCB accessible to other...
  • Page 368 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS static void wait_not_busy(ccb_ptr) struct _ccb_cservice_command *ccb_ptr; { while ( ccb_ptr->_access_control_flags & (1L << BUSY) ) /* we're waiting until the ME has /* cleared the BUSY bit /* end of 'wait_not_busy()' call: do_service(ccb_ptr, service_number) in : ccb_ptr ->...
  • Page 369 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE static short check_device(ccb_ptr, device, destination) register struct _ccb_cservice_command *ccb_ptr; unsigned long device; register short *destination; { ccb_ptr->command = SERVICE; /* we do a SERVICE call ccb_ptr->service = GET_LOGICAL_DEVICE_NUMBER; /* we want to get logical device /* numbers ccb_ptr->parameter[0] = device;...
  • Page 370 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS call: set_floppy_parameter(ccb_ptr, drive) in : ccb_ptr -> CCB address drive -> floppy drive number out : STATUS as returned from the ME in the CCB description: set_floppy_parameter executes a set floppy parameter service. called subroutines: do_service() static unsigned long set_floppy_parameter(ccb_ptr, drive) register struct _ccb_cservice_command *ccb_ptr;...
  • Page 371 SECTION 9 APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE static unsigned long do_me_read(ccb_ptr, block, buffer, drive) register struct _ccb_read_command *ccb_ptr; unsigned long block; unsigned char *buffer; unsigned long drive; { ccb_ptr->command = READ; /* we do a READ call ccb_ptr->buffer = buffer; /* set read buffer ccb_ptr->count = 1;...
  • Page 372 SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS call: close_device(ccb_ptr) in : ccb_ptr -> address of CCB which is to use out : ME return value in the CCB description: close_device() simply executes a CLOSE command to the given CCB. The response mode is not of interrest because we simply poll the answer.

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