Dini Group DN8000K10 Manuals

Manuals and User Guides for Dini Group DN8000K10. We have 1 Dini Group DN8000K10 manual available for free PDF download: User Manual

Dini Group DN8000K10 User Manual (195 pages)

LOGIC Emulation Source

Brand: Dini Group | Category: Computer Hardware | Size: 4 MB

Table of Contents
3
About this Manual
10
Manual Contents
11
About this Manual
11
Quick Start Guide
11
Controller (USB) Software Guide
11
Board Hardware Description
11
Reference Design Guide
11
FPGA Design Guide
11
Ordering Information
11
Additional Resources
11
Conventions
14
Typographical
14
C Ontent
14
File Names
14
Physical Orientation and Origin
15
Part Pin Names
15
Schematic Clippings
15
Media Card Interface
15
Config FPGA
15
Terminology
15
FPGA Numbering
16
Quick Start Guide
17
Provided Materials
17
Esd Warning
18
Power-On Instructions
19
Check Power Jumper
19
Memory and Heat Sinks
20
Prepare Configuration Files
21
Connect Cables
23
Power on
23
Check Power Indicator Leds
24
Iew Configuration Feedback over RS232
24
Watch Startup Sequence over RS232
24
Interactive Configuration
26
Read Temperature Sensors
27
User Serial Port
28
Check LED Status Lights
29
Using the Usb Controller Program
30
Operating the USB Controller Program
31
Using AETEST to Run Hardware Tests
33
Aetest on Linux or Solaris
33
Use Aetest
33
Menu Option
35
Board Controls
36
Hard Reset
36
Moving on
37
Controller Software
38
Usb Controller
38
Visual Display
39
Log Window
39
Menu Options
39
Contextual Menu
39
File Menu
39
Edit Menu
40
FPGA Configuration Menu
40
FPGA Memory Menu
41
Settings Info
42
Settings/Info Menu
44
Aetest
45
Running AETEST
46
Compiling AETEST
46
Updating the Dn8000K10 Firmware
46
Updating the MCU (Flash) Firmware
47
Updating the Configuration FPGA (PROM) Firmware
48
Programmer's Guide
51
Cypress CY7C68013A
52
Configuration FPGA
52
Configuration Register Map
53
Vendor Request List
55
USB Reference Design Control
56
Main Bus Accesses
56
Configuration
57
Readback
57
Hardware
58
Overview
58
Configuration Circuit
59
Overview
59
Configuration Options
60
Compactflash
60
Jtag
64
Selectmap
66
IDE (Remote Compact Flash)
66
Usb
67
The Configuration FPGA
67
Config FPGA Configuration
67
Smart Media / Compact Flash
69
MCU Communication
70
Clock Control
70
Rs232
72
Main Bus Control
73
Leds
73
Remote Access
73
IIC
73
Signal Descriptions
73
FPGA Configuration Process
73
Mcu
76
Rs232
76
Clocks
77
Leds
78
Memory Space
78
Config FPGA Memory Space
80
Flash and SRAM Memory Space
82
Usb
82
Compactflash
85
Clocking
86
Global Clocks
88
ICS 8442 Phases
89
SS (Single Step) Clocks
91
DIV Clocks
91
User Clock
92
Reference Clock
93
Daughter Card Clocks
93
FPGA Clock Banks
95
Expansion CLPD
95
Fx Clpd
97
Reset Topology
97
Reset Configuration
97
Power
99
Switching Power Supplies
102
Secondary Power Supplies
103
DDR2 Termination Power
103
MGT Power
104
Optical Module Power
105
Vbatt
106
Power Distribution
108
Bypassing
109
Vccaux
109
Cooling
109
Fpga Interconnect
111
High Speed Serdes Support
111
Main Bus
114
Fpga Dram Memory Interface
116
Clocking
116
Signaling
117
Termination
117
Source-Synchronous Clocking
117
SODIMM Power Supply
117
Alternate Memory Modules
118
Daughter Card Interface
119
Daughter Card Physical
120
Daughter Card Locations
120
Daughter Card Mounting
121
Insertion and Removal
122
Daughter Card Electrical
123
Pin Assignments
123
CC, Vref, DCI
126
Global Clocks
126
Power and Reset
126
MGT Signals
127
VCCO Voltage
127
VCCO Bias Generation
127
Daughter Card Types
128
Types 1 and 2 Short (300Pin & 400Pin Short)
129
Type 3 (300Pin)
129
Type 0 (300 FX)
130
Connector Pin
130
Leds
130
Mgt Serial Resources
135
Rocketio
135
Rocketio Signaling
136
Rocketio Clock Resources
138
Daughter Card Input
138
Synthesizers
138
Samtec
139
Oscillators
139
Xfp Refclk
144
MGT Power Network
144
RTERM and MGTVREF
146
FX CES2 Power Supplies
146
Connections
146
Samtec Multi Gigabit Cable Connector
149
Optical Modules
151
Sfp
151
SFP Expansion CPLD
152
Xfp
154
Xfp IIC
155
XFP Expansion CLPD
155
The Daughter Card
156
The Smas
158
Fpga System Monitor/Adc
159
Mechanical
161
Overview
161
Base Plate
161
Test Points and Connectors
163
Test Points
163
Connectors
165
The Reference Design
169
Exploring the Reference Design
169
What Is the Reference Design
169
R Unning the Reference Design
171
The Precompiled Bit Files
171
Load Fpgas with the Reference Design
172
Run the Aetest Program
172
Run the Rocketio Test
172
Compiling the Reference Design (Windows)
175
Modify Source
175
Xilinx ISE
176
The Build Utility: Make.bat
177
Implementation Details
178
Main Test
178
Rocketio V4 Test
180
LVDS Test
181
Clock Summary
181
Address Maps
182
Memory Space
182
Decoder
184
Main Bus Signaling
186
Ordering Information
189
Fpga Options
189
Fpga F0, F12
189
Fpga F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F13, F14, F15
189
Configuration FPGA
190
Multi-Gigabit Serial Options
190
Serial Clock Crystals
190
Optional Equipment
190
Rack Mount Chassis
190
Daughter Cards
191
Third Party Equipment
192
Common Problems
193
Simulation Does Not Match Synthesis
193
XST Is Giving Errors Because It Cannot Find Virtex4.V or Resync.V
194
Signal Name[0] Exists in My Code, but Place and Route MAP Step Complains the Signal Name[0] from My Ucf File Does Not Exist
194
Certify Fails Because the Ports on My Virtex 4 Do Not Match the Specified Part
194
The DN8000K10 Cannot Read My Smartmedia Card. the RS232 Port Prints: Bad SM Card Format
194
There Is a Lot of Deterministic Jitter (DJ) on My Rocketio Channel
194
There Is a Lot of Deterministic Jitter (DJ) on My Rocketio Clock Signals
195
My Design Works Correctly in All the Fpgas Except for One
195
Rocketio Is Getting a High Bit Error Rate
195
Rocketio Is Not Working
195
Common Questions
195
Where Are All of the Debug Pins
195
Where Can Get the Daughter Card Connectors
195
Can I Use Two Dini Products at the same Time
195
Do You Provide a Board Description File for
195
Where Is the VHDL Reference Design
195

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