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Dini Group DN8000K10 User Manual

Logic emulation source
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THE DINI GROUP
LOGIC Emulation Source
User Guide
DN8000K10

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  • Page 1 THE DINI GROUP LOGIC Emulation Source User Guide DN8000K10...
  • Page 2 L O G I C E M U L A T I O N S O U R C E DN8000K10 User Manual Version 1 Print: February 3, 2009 © The Dini Group 7469 Draper Ave. La Jolla, CA92037 Phone 858.454.3419 • Fax 858.454.1728 support@dinigroup.com...

  • Page 3: Table Of Contents

    Table of Contents ABOUT THIS MANUAL ............9 CHAPTER 1: MANUAL CONTENTS ............................10 About this Manual ....................................10 Quick Start Guide ....................................10 Controller (USB) Software Guide ............................... 10 Board Hardware Description ................................10 Reference Design Guide ..................................10 FPGA Design Guide ....................................
  • Page 4 Edit Menu .................................... 39 1.3.4 FPGA Configuration Menu ..............................39 1.3.5 FPGA Memory Menu ................................. 40 1.3.6 Settings Info ..................................41 1.3.7 Settings/Info Menu ................................43 AETEST ................................. 44 Running AETEST ..................................45 Compiling AETEST .................................. 45 DN8000K10 User Guide www.dinigroup.com...
  • Page 5 A B O U T T H I S M A N U A L UPDATING THE DN8000K10 FIRMWARE ......................45 Updating the MCU (flash) firmware ............................46 Updating the Configuration FPGA (PROM) firmware ......................47 PROGRAMMER’S GUIDE ............................. 50 Cypress CY7C68013A ................................
  • Page 6 High speed Serdes support ..............................110 Main Bus ....................................113 FPGA DRAM MEMORY INTERFACE ......................... 115 Clocking ....................................115 ignaling ....................................116 7.2.1 Termination ..................................116 7.2.2 Source-synchronous clocking ............................116 SODIMM Power supply ................................. 116 Alternate Memory modules ..............................117 DN8000K10 User Guide www.dinigroup.com...
  • Page 7 XFP IIC ..................................154 10.5.7 XFP expansion CLPD ..............................154 10.5.8 The daughter card ................................155 10.5.9 The SMAs ..................................157 FPGA SYSTEM MONITOR/ADC ......................... 158 MECHANICAL ..............................160 12.1 Overview....................................160 12.2 Base Plate ..................................... 160 DN8000K10 User Guide www.dinigroup.com...
  • Page 8 ........188 FPGA OPTIONS ..............................188 FPGA F0, F12 ..................................188 FPGA F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F13, F14, F15: ................... 188 Configuration FPGA: ................................189 MULTI-GIGABIT SERIAL OPTIONS ........................189 DN8000K10 User Guide www.dinigroup.com...
  • Page 9 Certify fails because the ports on my Virtex 4 do not match the specified part .............. 193 5.1.5 The DN8000K10 cannot read my SmartMedia card. The RS232 port prints: Bad SM card format ....... 193 5.1.6 There is a lot of deterministic jitter (DJ) on my RocketIO channel ................. 193 5.1.7...

  • Page 10: About This Manual

    Welcome to DN8000K10 Logic Emulation Board Congratulations on your purchase of the DN8000K10 LOGIC Emulation Board. If you are unfamiliar with Dini Group products, you should read Chapter 2, Quick Start Guide to familiarize yourself with the user interfaces the DN8000K10 provides.

  • Page 11: Manual Contents

    List of available documentation and resources available. Reader’s Guide to this manual Quick Start Guide Step-by-step instructions for powering on the DN8000K10, loading and communicating with a simple provided FPGA design and using the board controls. Controller (USB) Software Guide A summary of the functionality of the provided software.
  • Page 12 Description DN8000K10 User The appendicies are distributed with the User Guide on the Guide appendicies user CD and are available from the Dini Group website: www.dinigroup.com PIN_OTHER – Pin-to-pin connection information for Daughter cards, clocks, memory modules, Multi-gigabit transceivers (MGT), LED and Main Bus PIN_DIAG –...
  • Page 13 The web page will contain the latest manual, application notes, FAQ, articles, and any device errata and manual addenda. Please visit and bookmark: http://www.dinigroup.com E-Mail technical You may direct questions and feedback to the Dini Group support using the following e-mail address: support@dinigroup.com Phone technical Call us at 858.454.3419 during the hours of 8:00am to 5:00pm...

  • Page 14: Conventions

    Signal is active low INT# is active low fpga_inta_n is active low 3.2 Content 3.2.1 File names Paths to documents included on the User CD are prefixed with “D:\”. This refers to your CD drive’s root directory. DN8000K10 User Guide www.dinigroup.com...

  • Page 15: Physical Orientation And Origin

    PWB. Z is the pin or terminal number or name, as defined in the datasheet of the part. Datasheets for all standard and optional parts used on the DN8000K10 are included in the Document library on the provided User CD.

  • Page 16: Fpga Numbering

    A B O U T T H I S M A N U A L FPGA array include all of the 16 user-programmable Virtex 4 FPGAs on the DN8000K10. These are F0-F15 3.2.8 FPGA Numbering The Virtex 4 FPGAs are named from the top left in a row major order,...

  • Page 17: Quick Start Guide

    However, due to the number of features and flexibility of the board, it will take some time to become familiar with all the control and monitor interfaces equipped on the DN8000K10. Please follow this quick start guide to become familiar with the board before starting your logic emulation project.

  • Page 18: Esd Warning

    ESD sensitive products: http://www.esda.org/basics/part1.cfm The DN8000K10 is shipped in a metal carrier case designed to protect the board from physical and electrical damage. When you handle the DN8000K10, contact the handles of the carrier to ground yourself before touching the PWB.

  • Page 19: Power-On Instructions

    Q U I C K S T A R T G U I D E 3 Power-On Instructions In the following sections, you will need to know the location of the following DN8000K10 features. CompactFlash SmartMedia DDR2 SODIMM 0 USB port...

  • Page 20: Memory And Heat Sinks

    G U I D E 3.2 Memory and heat sinks There should be an active heatsink installed on each FPGA on the DN8000K10. Virtex 4 FPGAs are capable of dissipating 15W or more, so you should always run them with heat sinks installed.

  • Page 21: Prepare Configuration Files

    The DN8000K10 reads FPGA configuration data from a CompactFlash card. To program the FPGAs on the DN8000K10, FPGA design files (with a .bit file extension) put on the root directory of the CompactFlash card file using the provided USB media card reader. The DN8000K10 ships with a 128MB CompactFlash card preloaded with the Dini Group reference design.
  • Page 22 //end Figure 4 5. Insert the CompactFlash card labeled “Reference Design” into the DN8000K10’s CompactFlash (CF) slot. If the DN8000K10 is in a chassis, there is a remote CF slot on the faceplate of the chassis. DN8000K10 User Guide www.dinigroup.com...

  • Page 23: Connect Cables

    3. Connect a USB cable (provided) to connect the DN8000K10 to a Windows XP computer. Older Windowses may work, but are not supported. Use connector J203 on the DN8000K10, or if it is installed in a chassis, you can use the remote USB power on the faceplate of the chassis.

  • Page 24: Check Power Indicator Leds

    S T A R T G U I D E chassis, the DN8000K10 is always powered on as long as a jumper is installed on P203. Use a wall switch or install a toggle switch on the power supply to control power.
  • Page 25 -- Performing Sanity Check on Bit File - The MCU is configuring FPGA F1 according to instructions in MAIN.TXT -- BIT FILE ATTRIBUTES -- FILE NAME: FPGA_F1.BIT FILE SIZE: 003A943B bytes PART: 4vlx100ff151319:42:39 DATA: 2005/11/09 TIME: 19:42:39 DN8000K10 User Guide www.dinigroup.com...

  • Page 26: Interactive Configuration

    ENTER SELECTION: Figure 5 You should see the DN8000K10 MCU main menu. If the reference design is loaded in the Virtex 4 FPGAs, then you should see the above on your terminal. Try pressing 3 to see if the configuration circuit was successful in programming the FPGAs.

  • Page 27: Read Temperature Sensors

    According to the Virtex 4 datasheet, the maximum recommended operating temperature of the die is 85°C. If the DN8000K10’s FPGA monitor circuit measures by default sets its reset threshold to 80°C. If the DN8000K10 is resetting due to temperature overload, you can use the temperature monitor menu to measure the current junction temperature of each FPGA.

  • Page 28: User Serial Port

    3.7.4 User Serial port The DN8000K10 has four serial ports (P206, P207, P208, P209) for user use. These ports can be accessed through the MB64B Bus. See Appendix PINS_OTHER for the pin locations of the MB64B signals on each FPGA.

  • Page 29: Check Led Status Lights

    FPGA. The switches are enabled by default. See Hardware: Interconnect: Main Bus. 3.8 Check LED status lights The DN8000K10 has many status LEDs to help the user confirm the status of the configuration process. Check the Reset indicator LED located near the upper, right-hand corner of the board, DS17.

  • Page 30: Using The Usb Controller Program

    LEDs and Connectors 4 Using the USB Controller program To change settings of the DN8000K10, or to communicate with the reference design (or user design), you can use the provided USB Controller program. Like the RS232 interface, the USB interfaces allow configuration of the FPGAs, changing clock and other settings.

  • Page 31: Operating The Usb Controller Program

    DN8000K10 has powered on. 2. When you connect the DN8000K10 via USB to your PC for the first time, Windows XP detects the DN8000K10 and asks for a driver. The board should identify itself as a “DiNi Prod FLASH BOOT”.
  • Page 32 USB Controller window should turn off. Figure 12 7. Now configure the FPGA using the contextual menu. Right-click on the FPGA image and select Configure FPGA. In the Open dialog box, select the DN8000K10 reference design from the User CD and click open. “D:\Programming Files\Standard_Reference_Design\LX100\fpga_a.bit”...

  • Page 33: Using Aetest To Run Hardware Tests

    USB software driver, you will be using the source code for this program as a reference. AETest is the program that you can use to verify the hardware on the DN8000K10, as well as to demonstrate the reference design function. The following instructions assume you have a PC running the Windows XP operating system.
  • Page 34 S T A R T G U I D E Figure 14 The AETest application then displays its main menu. Figure 15 Select menu option 2) to interact with the “main bus” interface of the Dini Group DN8000K10 reference design. DN8000K10 User Guide www.dinigroup.com...

  • Page 35: Menu Option

    S T A R T G U I D E Figure 16 The Main Bus menu will only work properly when the Dini Group reference design is loaded, or if your user design has implemented a compatible controller. Select Option 3) MainBus Write/Read DWORD 0x1000_0000 is address 0 of the DDR2 memory attached to FPGA F1.

  • Page 36: Board Controls

    Select a .bit file from the user CD. 5 Board Controls The DN8000K10 is designed to be operated remotely via the chassis front panel to protect your hardware investment. As a result, the DN8000K10 has very few controls located on the PWB itself.

  • Page 37: Moving On

    Soft Reset USB Port RS232 Ports If you have the DN8000K10 installed in the DN8000K10 Chassis, you can also use the front panel buttons to the same effect. 6 Moving On Congratulations! You have just configured FPGAs on the DN8000K10 and used all of the configuration control interfaces that you must know to start your emulation project.

  • Page 38: Controller Software

    Read/Write to FPGA(s) o Test DDRs/Reigsters/FPGA Interconnect/Rocket IO Before shipping a DN8000K10, the Dini Group uses this program to test all of the IO signals, memory interfaces, serial interfaces, clocks, and connectors of your board. The program is compatible with all Dini Group products in the 5000K, 6000K, 7000K and 8000K series...

  • Page 39: Visual Display

    U S B S O F T W A R E 1.1 Visual display The main window of the Dini Group USB Controller program shows the DN8000K10 Graphic. RS232 Controls Menu Bar Refresh Button Frequency Display DN8000K10 Graphic FPGA DONE Log Window 1.2 Log window...

  • Page 40: Edit Menu

    F1: ../fpga_one.bit D:\FPGA Programming\Files\Standard_Reference_Design\LX200\fpga_F15.bit d. Configure via SmartMedia/CompactFlash Card This option causes the DN8000K10 to go through its startup sequence by reading configuration instructions from the CompactFlash card. The Section Hardware: Configuration: CompactFlash contains instructions for creating a configuration CF card.

  • Page 41: Fpga Memory Menu

    1.3.5 FPGA Memory Menu This menu contains commands designed to work with the DN8000K10 reference design. All of the commands in this menu cause read and write instructions to happen over the reference design’s main bus interface. Status and control registers for the reference design are all memory- mapped over this main bus interface.

  • Page 42: Settings Info

    U S B S O F T W A R E g. Test DDR single FPGA (may be called “Test DN8000K10/PCI DDR”) This item automates a test of the memory space on the “main bus” interface but allows you to specify which FPGA(s) you would like to test.
  • Page 43 U S B S O F T W A R E Turn Fans On/Off The fans on the DN8000K10 cannot be turned off. This menu item cannot be enabled. MCU firmware version This menu item reads back the firmware version of the MCU to help the Dini Group debugging.

  • Page 44: Settings/Info Menu

    The Settings/Info Menu has the following options (1) Set FPGA RocketIO CLK Frequency When the DN8000K10 is first powered up the RocketIO Synthesizer MGTCLK inputs to the FPGAs are inactive, unless programmed using the main.txt file on a CompactFlash card. (The Epson Oscillators are active.) This menu option allows the user to specify what frequency the RocketIO Synthesizers should supply to each FPGA.

  • Page 45: Aetest

    GCLK0 (3) FPGA Stuffing Information – This option will display the type of FPGAs that are stuffed on the DN8000K10. (4) MCU Firmware Version – This option will display the MCU Firmware version in the log window.

  • Page 46: Running Aetest

    Targeting Windows XP required Microsoft Visual Studio 5. Targeting DOS requires DJGPP. Updating the DN8000K10 Firmware Dini Group may release firmware bug fixes or added features to the DN8000K10. If a firmware update is released you will need to follow the instructions in this chapter.

  • Page 47: Updating The Mcu (Flash) Firmware

    To protect against accidental erasure, the MCU firmware cannot be updated unless the board is put in firmware update mode during power-on. Find Switch block 1 (S1) on the DN8000K10. Move switch S1 #1 to the ON position. Power on the DN8000K10.

  • Page 48: Updating The Configuration Fpga (Prom) Firmware

    The USB Controller should freeze for about 10 seconds while the firmware update is taking place. When the download is complete, the Log window should print, “Update Complete” Move Switch block S1 #1 to the OFF position to put the DN8000K10 back into normal operation mode. Power cycle the board.
  • Page 49 Use a 14-pin 2mm IDC cable to connect the Parallel IV cable to the DN8000K10 connector J208. Power on the DN8000K10. When the Parallel IV cable is connected to a header, the status light turns green. Open the Xilinx program Impact.
  • Page 50 Impact will direct you to select a programming file for each. For the xcf32p device, select the Configuration FPGA Firmware update file provided by Dini Group. This file should be named prom_flp.mcs. Hit Open. Impact will then ask for a programming file to program the xc4vlx80.

  • Page 51: Programmer's Guide

    This section contains information to help the development of your own USB software for use with the DN8000K10. If you do not need to develop you own USB control software, or modify the Dini Group USB controller, you can skip this section. All of the code for AETest and USB Controller is provided on the user CD.

  • Page 52: Cypress Cy7C68013A

    Since vendor requests can contain only a limited amount of data, USB Bulk transfers are used to send configuration data to the DN8000K10. The MCU is too slow to process USB 2.0 data at full speed, and so the bulk transfer data is sent to external pins on the Cypress MCU (see Cypress datasheet) and to the configuration FPGA (next section).

  • Page 53: Configuration Register Map

    4.2.1 Configuration Register Map The DN8000K10 firmware is updated constantly to add compatibility for new products and add features. The information in this section may change after this manual is printed. The memory space of the MCU is 16 bits wide.
  • Page 54 Main Bus interface. See Reference Design. These registers must be enabled by setting the FPGA_COMMUNICATION register (above) 0x0002 REG_IDCODE This register returns a known value so the USB Controller program can identify it as the Dini Group reference design. 0x0004 REG_SCRATCH 0x 05 REG_HEADERTEST...

  • Page 55: Vendor Request List

    Loads (uploads) external ram VR_SETI2CADDR 0xa4 VR_GETI2C_TYPE 0xa5 8 or 16 byte address VR_GET_FLASH_REV 0xa6 Returns a revision code of the DN8000K10 MCU firmware VR_GET_FPGA_INFO 0xa7 VR_RENUM 0xa8 The Cypress MCU behaves as if it were removed and reconnected to USB. VR_DB_FX 0xa9...

  • Page 56: Usb Reference Design Control

    0x78, 0x56, 0x34, 0x12. To send a datum, send the code 0x01, followed by 4 bytes, LSB first. When the DN8000K10 receives a data word, it sends it onto the main bus interface to the address in the address register. It then increments the address register. Therefore, to send two...

  • Page 57: Configuration

    Virtex 4 Configuration Guide UG071 is not required. A standard .bit file from Xilinx bitgen can be transferred in binary over this USB interface to correctly configure an FPGA on the DN8000K10. Unless the HOLDDONES option has been activated, the Virtex 4 FPGA will activate, following the activation command imbedded in the .bit stream file.

  • Page 58: Hardware

    C h a p t e r 4 : The DN8000K10 was designed to be the densest emulation platform in the world. To achieve this goal, the FPGA chosen was the Virtex 4 LX200 FPGA, the largest FPGA available. Sixteen of these FPGAs were crammed onto the same PCB for ultra-high performance and maximum interconnect.

  • Page 59: Configuration Circuit

    If you need to probe, modify or design around the DN8000K10 you will need to examine the complete schematics. See Appendix Schematics. An assembly drawing has also been provided to help you find probe points on the DN8000K10.

  • Page 60: Configuration Options

    CompactFlash (or SmartMedia) card in the DN8000K10’s media card slot. When the DN8000K10 powers on, the microcontroller reads the contents of the CompactFlash card. If there is a file called “main.txt” on the root directory of the card, then the DN8000K10 will follow initialization instructions on that file.
  • Page 61 <byte> can be a two-digit hexidecimal number (8 bit). The following table describes the function of each of the available main.txt commands. Instruction Function // <comment> The MCU performs no operation and moves to the next command. DN8000K10 User Guide www.dinigroup.com...
  • Page 62 The maximum output frequency of the 8442 clock synthesizer is 800Mhz, although the DN8000K10 will limit this to 500Mhz, because the Virtex 4 global clock inputs cannot operate above this frequency. When the clock synthesizer is outputting a frequency above 401Mhz, the duty cycle is not guaranteed to be 50%.
  • Page 63 GCLK1, and PH2 feeds GCLK2. The global clock networks are only supplied with this divided clock when the clock source is set to DIV. Otherwise, this setting will have no effect. An example main.txt file: DN8000K10 User Guide www.dinigroup.com...

  • Page 64: Jtag

    2.2.2 Jtag Jtag is the only configuration method on the DN8000K10 that does not use the Virtex 4 SelectMap configuration interface. When programming the user FPGAs over a JTAG cable plugged into J13, the DN8000K10 configuration circuitry is not used.
  • Page 65 JTAG_FPGA_TDIB JTAG_FPGA_TDIB If you ordered your DN8000K10 with one or more FPGAs not installed, then a bypass jumper is installed connecting the TDI pin to the TDO pin of the uninstalled FPGA. In this way, the JTAG chain remains intact.

  • Page 66: Selectmap

    INITB3 D[7:0] The SelectMap interface on the DN8000K10 is split into four separate interfaces, for electrical reasons. FPGA F0, F1, F2, F3 are on one segment, FPGA F4, F5, F6, F7 are on the next segment. FPGA F8, F9, F10, F11 are on a segment, and FPGA F12, F13, F14, F15 are on the last segment.

  • Page 67: Usb

    H A R D W A R E 2.2.5 The USB interface on the DN8000K10 is provided by the Cypress microcontroller unit. To use USB to configure the FPGAs, see Chapter X, The USB application. USB can also be used to send information to and from your Virtex 4 user design. See Chapter X, the USB Application.
  • Page 68 CFG_CCLK_R CFG_DIN CFG_TDI CFG_INITn OE/RESET CFG_DONE CFG_PROGn R1281 BUSY HEADER 2mm 7X2 1.00K REV_SEL0 Xilinx PC4 JTAG header REV_SEL1 EN_EXT_SEL CLKOUT CFG_TMS CFG_PROM_TDO CFG_TCK CFG_TDI +1.8V VCCINT +2.5V VCCINT VCCINT VCCO VCCO VCCO VCCO VCCJ XCF32PVO48 DN8000K10 User Guide www.dinigroup.com...

  • Page 69: Smart Media / Compact Flash

    Through the Configuration FPGA, the microcontroller is able to read configuration settings in the main.txt file. When the microcontroller program determines that the user wants to program the Virtex 4 FPGAs from files in the SmartMedia or Compact Flash card, it instructs the Config DN8000K10 User Guide www.dinigroup.com...

  • Page 70: Mcu Communication

    The Config FPGA connects to all of the control signals that configure the global clocking network on the DN8000K10. All of these signals are either connected directly to an IO on the Config FPGA, or to an IO expansion CPLD that the Config FPGA controls over a 4-wire bus.
  • Page 71 DC_GCLK0_L0_DC1_DC0# Selects between DC1 and DC0 to source GCLK0 DC_GCLK1_L0_DC3_DC2# Selects between DC3 and DC4 to source GCLK1 DC_GCLK2_L0_DC6_DC5# Selects between DC5 and DC6 to source GCLK2 DC_GCLK3_L0_DC8_DC7# Selects between DC7 and DC8 to source GCLK3 DN8000K10 User Guide www.dinigroup.com...

  • Page 72: Rs232

    0.1uF MAX3388E/TSOP24 On the underside of the DN8000K10, there are two duplicate RS232 ports (P7 and P8) that can be used if an installed daughter card is covering the headers on the front. These duplicate headers are not installed by default, but can be installed on request.

  • Page 73: Main Bus Control

    PSON connected to EPS connector. 2.3.9 There is a single IIC bus on the DN8000K10 connecting all IIC enabled chips on the board. On this bus are three MAX1617A temperature sensing chips (U3, U4, U24), two DDR2 SODIMM sockets, and a serial EPROM. The IIC bus is polled constantly by the MCU for temperature information.
  • Page 74 Each Virtex 4 FPGA has a complete set of SelectMap signals connected point-to-point to the Config FPGA, except for FPGA B and C, who share signals D[0-7]. All signals are 2.5V CMOS signals except for D0-7 of FPGA A (Signals SELECTMAP_3V_D[0-7]) DN8000K10 User Guide www.dinigroup.com...
  • Page 75 H A R D W A R E After a Virtex 4 FPGA is configured, it asserts the signal DONE. On the DN8000K10, these signals have an LED attached to each DONE signal placed near the upper corner of each FPGA.

  • Page 76: Mcu

    The MCU is a standard 8051 instruction-set computer, except that all instructions are executed 4 cycles per instruction. The source code provided by the Dini Group on the user CD is supplied with a Keil microVision IDE project file suitable for creating the firmware binaries for use with the DN8000K10.

  • Page 77: Clocks

    When you connect a computer terminal to the port and power on the DN8000K10, the firmware loaded on the microcontroller unit will display a menu on the terminal. This menu will allow you to control the basic configuration options of the DN8000K10 including configuration, clock frequencies, and the Virtex 4 FPGA RS232 ports.

  • Page 78: Leds

    MCU_DATA[7:0] signals to input data into the MCU. On the DN8000K10, this signal is used to select between an FLASH, and the Config FPGA and a SRAM. XDATA is mapped to the Config FPGA and SRAM, and the instruction space is mapped to the Flash.
  • Page 79 8kB of internal memory from a serial EPROM (U13). The code in the EPROM instructs the MCU to copy the contents of the FLASH to the internal address range 0x0000 to 0x1FFF. In this way, the external flash can be reprogrammed to allow Dini Group to update the firmware of the DN8000K10.

  • Page 80: Config Fpga Memory Space

    Used when reading from SM but not configuring COMMAND DF01 Commands for the SM ROW_LADDR DF02 Holds lower 8-bits of SM address ROW_HADDR DF03 Holds upper 8-bits of SM address ROW_XADDR DF04 Holds extra bits of SM address DN8000K10 User Guide www.dinigroup.com...
  • Page 81 MCU_CNTL DF0B Address register for upper FLASH/SRAM bits FPGA_SELECT DF0C FPGA_select[5:0] = bits 5:0 PPC_RS232_ABSELECT DF0D Does nothing on the DN8000k10 PPC_RS232_CDSELECT DF0E Does nothing on the DN8000K10 FPGA_CNTRL DF0F bits[1:0] = 01 (write address), 10 (data write), 11 FPGA_BE...

  • Page 82: Flash And Sram Memory Space

    EP0 is controlled by FX2 hardware, and is not used by the DN8000K10 firmware. EP1, 4 and 8 are supported by the FX2 and defined, but are not used by the DN8000K10 firmware. EP2 is input. (USB Bulk Write). This is used to configure FPGAs and to communicate to the DN8000K10 User Guide www.dinigroup.com...
  • Page 83 EP6 is output (USB Bulk read). This is used to read from the Main Bus. A hardware buffer in the FX2 of configurable size (0 to 1024 bytes) The USB type B connector on the DN8000K10 (J203) is connected directly to the USB pins on the Cypress MCU. Some transient protection is provided.
  • Page 84 If so, firmware sends data to the external component if the ready signal(s) requirement is met and GPIF internal FIFOs are not empty, regardless of the DN8000K10 User Guide www.dinigroup.com...

  • Page 85: Compactflash

    (see CeUsb2 API or CeUsb2 generic firmware interface documentation) if this feature is implemented in the firmware. The windows WDM drivers for the DN8000K10 are general-purpose kernel-mode drivers (ezusb.sys) supplied by Cypress. The source code of the driver module is included on the user 2.5.8...

  • Page 86: Clocking

    Figure 25 CompactFlash socket 3 Clocking The clocking circuitry on the DN8000K10 is designed for high-speed operation. The flexible clock design should meet the most difficult clocking needs, allowing 7 totally asynchronous, controllable clock sources for the entire sixteen FPGA array.
  • Page 87 Figure 26 DN8000K10 clock network block diagram The primary clocks on the DN8000K10 are the three “global clocks phases” G0, G1 and G2. Each of the global clock networks can be driven by a ICS8442 frequency synthesizer, a pair of differential SMA inputs, or the configuration FPGA for special clock requirements (single- stepping…) The Configuration FPGA connection also allows the division of the outputs from...

  • Page 88: Global Clocks

    J226 J227 Single Step Clock GCLK0 PH0 (8442) 8442 PH0 Divide J228 J229 Single Step GCLK1 Clock PH1 (8442) 8442 PH0 Divide J230 J231 Single Step Clock GCLK2 PH2 (8442) 8442 PH0 Divide REFCLK PH3 (8442) DN8000K10 User Guide www.dinigroup.com...

  • Page 89: Ics 8442 Phases

    1:18 to each of the 16 Virtex 4 FPGAs, into the Configuration FPGA, and to a differential testpoint located near the center of the DN8000K10 (labeled “PH0” “PH1” and “PH2”). The arrival of the clocks at each of these destinations of synchronized.
  • Page 90 // main.txt file GCLK<global clock> Select: 8442 <global clock> must be 0,1, or 2. 3.1.2 RocketIO Clock Synthesizers The RocketIO clock synthesizers are named FX0_0, FX0_1, FX1_0, FX1_1. // main.txt file FX Clock Frequency: <clock name> <number>Mhz DN8000K10 User Guide www.dinigroup.com...

  • Page 91: Ss (Single Step) Clocks

    “DIV” as the source of the global clock network. This can be done from the USB Controller software in the clock setup control panel. // main.txt file GCLK0 SELECT: DIV // enables divide clock Figure 27 DIV Clock selection syntax example DN8000K10 User Guide www.dinigroup.com...

  • Page 92: User Clock

    H A R D W A R E 3.1.5 User Clock The DN8000K10 has an SMA pair for each of the three global clock networks G0, G1 and G2 for inputting clocks. The expected signaling standard for the input is LDVS DEFAULT CONFIG FOR LVDS SIGNALING...

  • Page 93: Reference Clock

    “DC0CLK” can be sourced from the headers DC0 or DC1, “DC1CLK” can be sourced from DC2 or DC3. “DC2CLK” can be sourced from DC5 or DC6. “DC3CLK’ can be sourced from DC7 or DC8. The headers DC4 and DC9 have no global clock sourcing capabilities. DN8000K10 User Guide www.dinigroup.com...
  • Page 94 PLL mode of each PLL must be set in order for the PLL to lock. This setting is made in the main.txt file. The PLL can also be bypassed for low-speed operation, or if synchronization is not needed or desired. DN8000K10 User Guide www.dinigroup.com...

  • Page 95: Fpga Clock Banks

    ACCESS TO A SPARE GC CLOCK INPUT. RESISTOR LOADED ON TOPSIDE OF BOARD. DCI is hooked up. Reset and BREAK are in this bank. DDR FB should be from the size of the RefClk,. 3.5 Expansion CLPD DN8000K10 User Guide www.dinigroup.com...
  • Page 96 Control of leaf-level, zero-delay buffers in daughter card global clock trees. • Monitoring of power regulator comparator outputs: +1.2V_8, +1.2V_9, +1.2V_12, +1.2V_13, +2.5V_3 CNTR (Center) • None Control of top-level, zero-delay buffers in daughter card global clock trees. DN8000K10 User Guide www.dinigroup.com...

  • Page 97: Fx Clpd

    Figure 10.2 illustrates the reset arrangement used on the Triton board. +1.2V_16 +2.5V_2 +3.3V Regulator +1.8V ARRAY FPGA DATA PROGn Config PROM Configuration FPGA INIT LOGIC PROGn RSTn SYS_RSTn CPLD_RSTn +2.5V_2 +1.2V_16 COMP COMP DC_RSTn PWR_FAULTn Supervisory Power Mon COMP COMP DN8000K10 User Guide www.dinigroup.com...
  • Page 98 Smart Media card. USB contact will be lost with the USB host, and the DN8000K10 will have to re-enumerate. There is a second button, S2 called “Soft Reset”. When this button is pressed, the signal “RESET_FPGAn”...

  • Page 99: Power

    This circuit shows the MAX1617 temperature monitor. The IIC bus is connected to the Cypress microcontroller. 5 Power The DN8000K10 gets its power from the 12V rail on 3 EPS power connectors (P200, P201, P202). A 500W EPS power supply is supplied with your board. DN8000K10 User Guide...
  • Page 100 MTH2 MTH2 EPS-CON24 +12.0V P202 TP45 EPS CON4 P201 G 12 G 12 G 12 G 12 EPS CON8 PS ON goes to P203.3 ATX_OK lights the LED DS137 The main rails of the DN8000K10 are: DN8000K10 User Guide www.dinigroup.com...
  • Page 101 2.1V switching power regulator PSU140. The following nets are derived from the +2.1V net: VCC_FX0_MGT12_0 VCC_FX0_MGT12_1 VCC_FX0_MGT12_2 VCC_FX1_MGT12_0 VCC_FX1_MGT12_1 VCC_FX1_MGT12_2 The DN8000K10 also has these secondary rails: VTT0 (0.9V) – This voltage is used to terminate the SSTL18 signaling of the DDR2 memory module. DN8000K10 User Guide www.dinigroup.com...

  • Page 102: Switching Power Supplies

    There are test points for measuring the voltage levels of each rail near the top left of the DN8000K10. Each rail is monitored by a voltage monitor circuit, and will cause a reset if any of the primary supplies drop 5% or more below their set points.

  • Page 103: Secondary Power Supplies

    Each power supply is protected with a 15A fuse on the inputs. If you need to operate the DN8000K10 with more than 15A of current for a power supply, you can change this fuse, but you need to find a heatsink solution for keeping the Virtex 4 FPGAs cool. The heatsink and fan provided are appropriate for a power consumption of about 10-15W per FPGA.

  • Page 104: Mgt Power

    VCC_MGT15_2_103 VTTXA_103 VCC_MGT15_3_103 VCC_MGT15_3_103 AA33 VTTXB_103 VCC_MGT15_4_103 VCC_MGT15_4_103 FB12 0.22uF VTRXA_103 FB14 0.22uF TXPPADB_103 FB11 AA34 0.22uF TXNPADB_103 0.22uF VCC_MGT25 AC34 RXPPADB_103 AD34 AC33 VCC_MGT25_1_103 FB16 RXNPADB_103 AVCCAUXMGT_103 VCC_MGT25_1_103 VCC_MGT25 0.22uF Virtex 4 FX - 1152 DN8000K10 User Guide www.dinigroup.com...

  • Page 105: Optical Module Power

    Optional optical modules have a variety of power supply requirements, most of which are met by the DN8000K10. Since the DN8000K10 has no negative voltage supply, it cannot generate the –5.2V required to supply ECL-based optical transceiver modules. Auxiliary power connectors, J278 (F0) and J280 (F12), is provided to connect to an external voltage supply if ECL signaling is required.

  • Page 106: Vbatt

    XFP power net to provide an alternative means to supply the XFP headers. 5.2.4 VBATT The DN8000K10 supports bit stream encryption by providing a battery socket. VBATT is connected to all 16 VBATT pins on the FPGAs. Use battery size 364, Positive side up. DN8000K10 User Guide...
  • Page 107 H A R D W A R E Battery Socket VBATT 2998 DN8000K10 User Guide www.dinigroup.com...

  • Page 108: Power Distribution

    H A R D W A R E 5.3 Power distribution The power system on the DN8000K10 is designed to minimize power loss by distributing current on the 12V net supplied by the EPS power supply connector to each FPGA, and using dedicated point-of-load power converters generate all of the FPGA power requirements.

  • Page 109: Bypassing

    5.3.1 Bypassing The power supply bypassing on the DN8000K10 on each of the 1.2V internal rails is sufficient for a fully loaded FPGA design to operate at 500Mhz. The 2.5V power rails have sufficient bypassing for all inter-FPGA and daughter card signals to be switching simultaneously using the LVDS standard at 500Mhz.
  • Page 110 Above: The FPGA temperature monitor circuit. The MAX1617’s IIC bus is connected to the Configuration FPGA. The MCU polls all 16 FPGA once every second. The SMBCLK and SMBDATA pins on the temperature monitor device are connected to the DN8000K10 IIC bus. See Hardware: IIC Each FPGA active heatsink requires 12V power to operate.

  • Page 111: Fpga Interconnect

    H A R D W A R E 6 FPGA Interconnect The DN8000K10 was designed to maximize the amount of interconnect between the two primary Virtex 4 FPGAs A and B. This interconnect was routed as tightly coupled differential was routed as tightly coupled differential...
  • Page 112 For detailed description of the required user design to achieve 1Gbs operation, see Xilinx Application note XAPP704, “High Speed SDR LVDS Transceiver”.’ Synchronous clocking and single-ended signaling are still possible on the DN8000K10; you are not required to use high-speed serial design techniques.
  • Page 113 F5-F9, F6-F10, F7-F11, F8-F9, F9-F10, F10-F11, F9-F13, F10-F14: 124 (2, 62-signal data lanes) • F0-F5, F1-F4, F1-F6, F2-F5, F2-F7, F5-F6, F8-F13, F8-F5, F9-F4, F9-F6, F9-F12, F9-F14, F10-F5, F10-F7, F10-F13, F10-F15, F11-F14: 62 (1, 62-signal data lane) DN8000K10 User Guide www.dinigroup.com...

  • Page 114: Main Bus

    MB80B[0-79] MB64B[0-63] The Dini Group reference design uses the signals MB80B[0-36]. Some options in the provided software may drive and read from these signals. Also, for the reference design to work, these signals must not be driven from a user design in another FPGA.
  • Page 115 8-bit resolution. The setting of these switches can be done through the software controller program or the configuration file on the configuration CompactFlash card. The bus switches are bi-directional. The control signals for the switches are connected to the configuration FPGA. DN8000K10 User Guide www.dinigroup.com...

  • Page 116: Fpga Dram Memory Interface

    H A R D W A R E 7 FPGA DRAM Memory Interface There are four standard 200-pin DDR2 SODIMM module sockets on the DN8000K10. These sockets are supplied with 1.8V power and keyed for use with DDR2 SDRAMs. These four sockets connect to FPGA F1, F2, F13 and F14.

  • Page 117: Signaling

    The SODIMM slots are provided with 1.8V power as required by the DDR2 SODIMM specification. This voltage can be adjusted if the customer would like to design a custom daughter card for use in the memory sockets. 20A power supply. DN8000K10 User Guide www.dinigroup.com...

  • Page 118: Alternate Memory Modules

    DS143 dimms 2 and 3 -VREF is connected to external 0.9V 7.4 Alternate Memory modules Dini Group has alternate memory modules available to provide SRAM, RLDRAM and Flash memory. These are compatible with the 1.8V SODIMM slots on the DN8000K10 DN8000K10 User Guide...

  • Page 119: Daughter Card Interface

    H A R D W A R E 8 Daughter Card Interface The expansion system of the DN8000K10 is designed to provide the highest total aggregate bandwidth possible. The connector, pin out and signaling, has been selected to achieve this. The Source-synchronous interface requirements of the Virtex 4 FPGA have been met by the daughter card expansion interface to allow use of the built-in serdes modules.

  • Page 120: Daughter Card Physical

    The “Plug” of the system is located on the DN8000K10, and the “receptacle” is located on the expansion board. This selection was made to give a greater height selection to the daughter card designer.

  • Page 121: Daughter Card Mounting

    DN8000K10 will allow it to operate FPGA side down, or on its side to allow physical access to the daughter card and the controls of the DN8000K10. With this host-plate-daughter card arrangement, there is a limited Z dimension clearance for backside components on the daughter card.

  • Page 122: Insertion And Removal

    Be absolutely certain that both the small and the large keys at the narrow ends of the Meg Array line up BEFORE applying pressure to mate the connectors! Place it down flat, then press down gently. The following two excerpts are taken from the FCI application guide for the Meg Array series of connectors. DN8000K10 User Guide www.dinigroup.com...

  • Page 123: Daughter Card Electrical

    The daughter card pin out and routing were designed to allow use of the Virtex 4’s 1 Gbps general purpose IO, and 10Gbs MGT signaling. All signals on the DN8000K10 are all routed as differential, 50-Ohm transmission lines, with means to properly terminate.
  • Page 124 This allows the signals to be used as high-speed, single-ended, or as loosely coupled differential pairs. There are two types of connectors on the DN8000K10, 300 and 400 pins. The first 300 pins on both types of connectors are identical. This should allow a 300-pin connector to be installed on a 400-pin land pattern on a daughter card to allow limited functionality in 300-pin daughter card positions.
  • Page 125 L15P L16P L13N L14N L15N L16N L17P L18P L30P L30N L19P L20P L17N L18N L19N L20N L21P L22P L31P L31N L23P L24P L21N L22N L23N L24N A B C D E F G H J K DN8000K10 User Guide www.dinigroup.com...

  • Page 126: Cc, Vref, Dci

    FPGA. These clocks can be used as global clocks from within the FPGA code of the FPGA that connects to the daughter card, but not globally to the entire DN8000K10. The GCC signal on every daughter card except DC4 and DC9 connects to the “Daughter card Global Clock”...

  • Page 127: Mgt Signals

    MEG-Array 300-Pin SOT95P280-5N The RSTn signal to the daughter card is an open-drain, buffered copy of the SYS_RSTn signal. This signal causes the entire DN8000K10 to reset, losing all FPGA configuration data and resetting the configuration circuitry. 8.2.5 MGT Signals Also see Hardware: MGT Serial Resources: The connections: Daughter cards.

  • Page 128: Daughter Card Types

    10.0K 380mA MAX AT 1.22V 8.3 Daughter card Types To avoid incompatibilities with future products, the Dini Group has defined daughter card sizes that it uses for all of its standard daughter cards using the MegArray connector system. TYPE 3B TYPE 0 8.2"...

  • Page 129: Types 1 And 2 Short (300Pin & 400Pin Short)

    1.950" 0.500" 1.950" 0.500" The mounting hole positions are standard, and the DN8000K10 has holes in its base plate to accommodate these holes. See Appendix: Assembly 8.3.2 Type 3 (300pin) The 300-pin connectors connected to FPGAs F3 and F15 have the GCLKC pins, however, these pins do not connect to the global clock network as described in the Global Clock section of the Daughter card electrical specification.

  • Page 130: Type 0 (300 Fx)

    MGT Serial Resources: Connections: Daughter card. The GCLKA-GCLKC connects as described in the Daughter card electrical section, including GCLCK’s connection to the global clock distribution network. 9 LEDs The following table lists all of the LEDs on the DN8000K10. LED conventions: GREEN GOOD RED BAD.
  • Page 131 GREEN User controlled LED from FPGA F11. DS101 F11_LED1 GREEN User controlled LED from FPGA F11. DS102 F11_LED2 GREEN User controlled LED from FPGA F11. DS103 F11_LED3 GREEN User controlled LED from FPGA F12. DS113 F12_LED0 DN8000K10 User Guide www.dinigroup.com...
  • Page 132 GREEN User controlled LED from FPGA F8 DS91 F8_LED3 GREEN User controlled LED from FPGA F9 DS92 F9_LED0 GREEN User controlled LED from FPGA F9 DS93 F9_LED1 GREEN User controlled LED from FPGA F9 DS94 F9_LED2 DN8000K10 User Guide www.dinigroup.com...
  • Page 133 Blinks when the board is in reset DS17 Q_CLED15 GREEN FPGA F0 is configured DS46 Q_F0_DONE GREEN FPGA F1 is configured DS52 Q_F1_DONE GREEN FPGA F10 is configured DS53 Q_F2_DONE GREEN FPGA F11 is configured DS51 Q_F3_DONE DN8000K10 User Guide www.dinigroup.com...
  • Page 134 Each FPGA has 4 green user LEDs. Above shows FPGA F3 and it’s three green user LEDs, F3_LED0, F3_LED1, F3_LED2 and F3_LED3 Signal FPGA NAME F0 F1,F2,F3,F8, F4,F5,F6,F7 Name ("FX0") F9,F10,F11 F13,F14,F15 ("FX1") LED[0] AE22 AK17 DN8000K10 User Guide www.dinigroup.com...

  • Page 135: Mgt Serial Resources

    FX100 FPGAs used on the DN8000K10 provide either 16 (FX60) or 20 (FX100) Multi-Gigabit Transceiver (MGT) channels on two corners of the board. The DN8000K10 allows the use of Xilinx new 11Gbs transceivers. High-speed I/O connections provided include the following: XFP socket (4) –...

  • Page 136: Rocketio Signaling

    Straight SMA connector pairs Daughter card channels 1 and 2 Samtec channels 3 and 4 Samtec channels 7 and 8 (FX100 only) Samtec channels 1 and 2 Table XXX RocketIO Tile Assignments for FPGA 12 (FX60/100) 10.2 RocketIO signaling DN8000K10 User Guide www.dinigroup.com...
  • Page 137 H A R D W A R E DN8000K10 User Guide www.dinigroup.com...

  • Page 138: Rocketio Clock Resources

    R1687 P_DIV R1673 (1.00K - DNI) TEST_CLK FX1_CLK0_XTALSEL XTAL_SEL R1679 P3.3VAFX1 FX1_CLK0_VCOSEL VCO_SEL 10.0 VDDA_FX1_CLK0 P3.3VAFX1 FX1_CLK0_SCLK S_CLOCK VCCA ALLCLK_SDATA S_DATA ALLCLK_SLOAD S_LOAD C1297 C1296 nP_LOAD 0.1uF 10uF R1689 1.00K P3.3VAFX1 ALLCLK_SRST VEE_1 VEE_2 VCCO ICS84321 DN8000K10 User Guide www.dinigroup.com...

  • Page 139: Samtec

    Since it is impossible to determine during manufacturing the clocking requirements of every possible end application, the DN8000K10 comes with a flexible clock network capable of a wide range of serial frequencies, while maintaining the tight jitter requirements of the 10 Gigabit serial transceivers.
  • Page 140 //SET “FX1” (F12) clock sources CLOCK SOURCE: FX1_0 SYNTH1 CLOCK FREQUENCY: FX1_0 300Mhz All of the Source options for FX1_0 (F12) and FX0_0 (F0) are: SYNTH0, SYNTH1, QSE0, QSE1 The available options for FX1_1 (F12) and FX0_0 (F0) are: DN8000K10 User Guide www.dinigroup.com...
  • Page 141 H A R D W A R E DC, SYNTH1, QSE1 DN8000K10 User Guide www.dinigroup.com...
  • Page 142 The ICS843020-01 synthesizer is very low jitter and should suitable for operation up to 6Gbs RocketIO operation. The frequency of the synthesizer can be adjusted through the main.txt file on the SmartMedia card, or through the USB GUI program. DN8000K10 User Guide www.dinigroup.com...
  • Page 143 84.375, 143.75-168.75, 287.5-337.5, and 575-675 MHz. For 10Gb serial transmission rates, you should use one of the low-jitter fundamental frequency SAW oscillators. These oscillators operate at 250Mhz and so cover the gaps in the frequency synthesis options given by the ICS843020-01. DN8000K10 User Guide www.dinigroup.com...

  • Page 144: Xfp Refclk

    XFP modules may require a low-jitter clock at a frequency 1/64 of the data rate. The only clock source on the DN8000K10 capable of meeting these requirements are the MGT outputs. You should use the same transmit clock as you are using for the XFP data MGT. Set the output data pattern such that it becomes a clock at 1/64 of the XFP bit rate.
  • Page 145 MGT analog and digital supply voltages and the 1.5V termination supply are isolated from the high-frequency digital noise produced by the 16 FPGAs in the DN8000K10 array section. Each MGT power supply input pin is further protected from switching noise and supply current variation by a passive power filter network.

  • Page 146: Rterm And Mgtvref

    10.4.2 FX CES2 power supplies. If your DN8000K10 came with a CES2 (engineering sample) FX part for FX0 and FX1 (F0 and F12), then a Virtex 4 erratum require the MGT analog 1.2V rail to be 1.1V. This setting may not be reflected by Appendix Schematics.
  • Page 147 AP12 DC_CH4_TXN SFP1_TXN AP14 DC_CH4_RXP SFP1_RXP AP15 DC_CH4_RXN SFP1_RXN RIGHT COLUMN CLOCKS GT11CLK_X1Y3 OSC0 (U379) EG-2101CA OSC0 (U379) EG-2101CA (113) 250Mhz 250Mhz GT11CLK_X1Y1 SYNTH1 (U395) 25.0Mhz SYNTH1 25.0Mhz (110) ("FX0_1") ("FX1_1") DC0 (P100) A29,B30 DC3 (P103) A29,B3 DN8000K10 User Guide www.dinigroup.com...
  • Page 148 AG34 J241 QSE03_RXN GT11_X0Y2 AL34 J244 QSE04_TXP AM34 J245 QSE04_TXN AP32 J246 QSE04_RXP AP31 J247 QSE04_RXN GT11_X0Y1 AP23 J250 SMA RF QSE01_TXP Samtec QSE (106) AP22 J251 Connectors QSE01_TXN Connector AP26 J248 Right-Angle QSE01_RXP AP25 J249 QSE01_RXN DN8000K10 User Guide www.dinigroup.com...

  • Page 149: Samtec Multi Gigabit Cable Connector

    For board-to-board high-density connections, two Samtec ribbon cable connectors per FX part are connected to RocketIO. The pin outs on the cable allow two DN8000K10 boards to be connected to each other for 4 bi-directional channels operating at 5Gbs or more per channel, per direction.
  • Page 150 DN8000K10s together. Note that the grounded pins 5, 11, 17, 23, 29, 35, 6, 12, 18, 24, 30, 36 are NC (no pin present) on the connector. These are grounded in the DN8000K10 for reverse- compatibility. The pins 41, 42, 43, 44 are ground blades built into the connector. Pins 45 and 46 are non-plated plastic alignment pins.

  • Page 151: Optical Modules

    Express. See Hardware: MGT Serial Resources: Clocks: QSE 10.5.2 Optical Modules The DN8000K10 comes with eight optical module connectors. If you need to interface to a specific physical standard, the easiest way is to buy an SFP or XFP module that supports that standard.

  • Page 152: Sfp Expansion Cpld

    RD_WRn low synchronously with SCLK. Serially transmit a 5-bit sequence to the CPLD using the SDATA pin. The sequences are used for the CPLD to determine which optical module to access. The 5-bit sequence can be one of the following (binary): DN8000K10 User Guide www.dinigroup.com...
  • Page 153 SFF or XFI interfaces, see the SFF and XFI specifications. CPLD registers Address XFP0_MOD_DESEL 0x001 XFP0_INTn 0x002 XFP0_TXDIS 0x003 XFP0_MOD_ABS 0x004 XFP0_MOD_NR 0x005 XFP0_RX_LOS 0x006 XFP0_PDOWN 0x007 SFP0_TXFAULT 0x001 SFP0_TXDISABLE 0x002 SFP0_MOD_DEF 0x003 SFP0_MOD_DEF 0x004 DN8000K10 User Guide www.dinigroup.com...

  • Page 154: Xfp

    (See signal REFCLK in the XFI specification). The REFCLK signal on the DN8000K10 is sourced from one pair of SMAs for each Virtex 4 FX FPGA. The REFCLK signal should be 1/64 of the data rate driven onto the XFP’s TX pins. You can generate this clock using one of the SMA outputs of the Virtex 4 FX MGT.

  • Page 155: Xfp Iic

    H A R D W A R E Most XFP modules require 1.8V power from the host. The 1.8V Voltage provided by the DN8000K10 come from the 1.8V_0 and 1.8V_1 power rails, shared by the SODIMM module sockets. Power supply filtering for each XFP module is provided, following the recommendations in the XFP specification.

  • Page 156: The Daughter Card

    The pin out of the MegArray connectors on the DN8000K10 is in a GSSG pattern, with extra ground pins surrounding the signals to bring pair-to-pair cross talk to less than 1%.
  • Page 157 B1L16P B1L16N VCCO1_1 VCCO1_2 MEG-Array 300-Pin Nothing is connected to DC0 and DC3 except for MGT signals, power, VCCO0 and VCCO1 (unused), MGTCLK, GCA, GCB, GCC. Descriptions of these signals are found in Hardware: Daughter cards DN8000K10 User Guide www.dinigroup.com...

  • Page 158: The Smas

    H A R D W A R E 10.5.9 The SMAs SMA RF connectors are the most robust connector on the DN8000K10 for very-high data rates. For MGT channels connected to the SMA interface, there is one SMA connector for each of Transmit Negative, Transmit Positive, Receive Negative, and Receive Positive.

  • Page 159: Fpga System Monitor/Adc

    Xilinx. One important function of the System Monitor, temperature sensing, has been added to the configuration circuitry. The DN8000K10 will automatically monitor and prevent thermal overload in the sixteen Virtex 4 FPGA array. No user action is required. A Maxim MAX1617A temperature monitor uses a current sensing voltage sours connected to the TDN and TDP pins of the Virtex 4 FPGA to measure changes in internal temperature.
  • Page 160 H A R D W A R E FPGA A LX 200 Reserved pins U11-18 AV19 VREFN_SM AV20 VREFP_SM VCCAUXA_2.5V AW21 AVDD_SM AW19 VN_SM AW20 VP_SM AV18 AVSS_SM VREFN_ADC VREFP_ADC VCCAUXA_2.5V AVDD_ADC VN_ADC VP_ADC AVSS_ADC DN8000K10 User Guide www.dinigroup.com...

  • Page 161: Mechanical

    12.2 Base Plate The DN8000K10 is shipped on a steel base plate to provide protection, stability and an easy way to transport the board.
  • Page 162 H A R D W A R E Optionally, the DN8000K10 can ship in a 4U rack mount chassis assembly. See Section Ordering information: Optional Equipment: Chassis. The DN8000K10 can also be operated outside of the carrier if desired. DN8000K10 User Guide...

  • Page 163: Test Points And Connectors

    H A R D W A R E 13 Test points and Connectors 13.1 Test points The following table lists all of the test points on the DN8000K10 and the corresponding net. See Appendix Schematic. Assembly Label Label Net name...
  • Page 164 +5.0VSB The EPS signal “5SB”. Unconnected on DN8000K10 TP43 Monolithic Ground TP18 Monolithic Ground TP45 +12.0V TP35 -5.0V Unconnected on DN8000K10 TP32 -12.0V Unconnected on DN8000K10 TP31 +3.3V TP33 +5.0V TP47 DDR2_CK_TEST Copy of CK0p and CK1p signal to DIMM2...

  • Page 165: Connectors

    Grounded test points are distributed to make grounding oscilliscope probes easier. GND Test Points TP18 TP43 13.2 Connectors The following table lists all of the connectors on the DN8000K10. Also see the Schematics provided on the user CD. Assy Purpose Connector Part...
  • Page 166 Feeds global clock 2 (GCLK2) LVDS (modify 142-0701-201 ICS854057 for LVPECL or CML) U408 “FX1_XFP1” AMP 1367500-1 http://www.xfpmsa.org/XFP_SFF_INF_8077i_Rev4_0.pdf U409 “FX1_XFP0” AMP 1367500-1 http://www.xfpmsa.org/XFP_SFF_INF_8077i_Rev4_0.pdf J239 “FX1_SFP0” Molex 74441-0001 SFP specification INF-8074.PDF J238 “FX1_SFP1” Molex 74441-0001 SPF specification INF-8074.PDF DN8000K10 User Guide www.dinigroup.com...
  • Page 167 CML (RocketIO) J258 FX1 SMA Johnson 142-0701-201 http://www.xilinx.com/bvdocs/userguides/ug076.pdf CML (RocketIO) J259 FX1 SMA Johnson 142-0701-201 http://www.xilinx.com/bvdocs/userguides/ug076.pdf CML (RocketIO) J256 FX1 SMA Johnson 142-0701-201 http://www.xilinx.com/bvdocs/userguides/ug076.pdf CML (RocketIO) J257 FX 1 VERT SMA Johnson 142-0701-201 http://www.xilinx.com/bvdocs/userguides/ug076.pdf CML (RocketIO) DN8000K10 User Guide www.dinigroup.com...
  • Page 168 P108 “DC8” FCI 84520-102 P107 “DC7” FCI 84520-102 P106 “DC6” FCI 84520-102 P105 “DC5” FCI 84520-102 P104 “DC4” FCI 84578-102 P100 “DC0” FCI 84578-102 P101 “DC1” FCI 84578-102 P102 “DC2” FCI 84578-102 P103 “DC3” FCI 84578-102 DN8000K10 User Guide www.dinigroup.com...

  • Page 169: The Reference Design

    The Reference Design C h a p t e r 5 : This chapter introduces the DN8000K10 Reference Design, including information on what the reference design does, how to build it from the source files, and how to modify it for...
  • Page 170 /RocketIO Contains Verilog and VHDL code for the DN8000K10 /… /… Rocket IO reference design. /… /DN8000K10 Contains Verilog and VHDL code for the DN8000K10 /… /… memory and single-ended interconnect reference design. /… /common Contains general Verilog and VHDL code used in the /…...

  • Page 171: R Unning The Reference Design

    GCLK0 Select: 8442 // possible option SMA/8442/DIV/SS GCLK1 Select: DIV // Selects DIVIDE clock GCLK2 Select: SS / Select Single Step Clock (48Mhz right now) For more information about the CompactFlash main.txt file, see Hardware: Configuration: CompactFlash. 1.2.1 The Precompiled Bit files DN8000K10 User Guide www.dinigroup.com...

  • Page 172: Load Fpgas With The Reference Design

    CD to a compact flash card, following the steps given in Quick Start Guide. Turn on the DN8000K10 and allow the configuration circuitry to load the configuration streams into all 16 FPGAs.
  • Page 173 To verify the function of each MGT tile and it’s error rate, select the Display registers COL 0 and 1 menu items in the MGT menu. This will display a dump of the IO registers controlling each MGT channel. DN8000K10 User Guide www.dinigroup.com...
  • Page 174 Appendix Pins Other, or see Hardware: MGT Serial Resources. The connectivity is different from the F0 to the F12 FPGAs. Frame Cnt: Shows a 64-bit counter clocked off the MGT tile’s USER_CLK. This counter is reset using option 9) Reset All in the MGT menu. DN8000K10 User Guide www.dinigroup.com...

  • Page 175: Compiling The Reference Design (Windows)

    FPGA you wish to compile. //`define FPGA_F0 //`define FPGA_F1 //`define FPGA_F2 … //`define FPGA_F4 You should leave the following line uncommented. This define is used by Dini Group for testing. `define BOARD_DN8000K10 DN8000K10 User Guide www.dinigroup.com...

  • Page 176: Xilinx Ise

    .ucf file has been provided for each FPGA in the directory /standard_reference_design/ucf/ The same ucf file can be used for reference design branches Main_test and LVDS. Use /RocketIOtest_v4/ucf_8k10/ for compiling the RocketIO branch reference design. DN8000K10 User Guide www.dinigroup.com...

  • Page 177: The Build Utility: Make.bat

    The reference design must support any subset of the 16 Virtex 4 FPGAs in any combination of LX100, LX160, and LX200 sizes. Compiler constants are used to include/exclude code, including sections specific to certain FPGAs, sections specific to memory controllers, or may DN8000K10 User Guide www.dinigroup.com...

  • Page 178: Implementation Details

    These registers are made accessible to the world by memory-mapping them to the “Main Bus” interface. The main bus interface uses the DN8000K10 signals “MB80B[37:0]”. These signals are common to all 16 FPGAs. Note that these signals are broken by bus switches.
  • Page 179 64 bits, adaptive clock phase alignment was added, and the clock structure was changed to fit within the clock resources on the DN8000K10. The contents of the DDR2 SODIMM memory interface is memory mapped to the main bus interface. See Address Maps for the location of the DDR2 memory interface in the Main Bus.

  • Page 180: Rocketio V4 Test

    The latencies of the DDR2 interface are hard-coded to the maximum allowable DDR2 latencies 3-3-3-8. The register REG_IDCODE returns a constant allowing the USB Controller program to recognize the board as a Dini Group reference design. The USB Controller program can then display reference design status and controls. 2.2 RocketIO V4 Test This reference design is only provided in a compiled form for FPGAs F0 and F12, the only FPGAs on the DN8000K10 with RocketIO circuits.

  • Page 181: Lvds Test

    MGT circuit to work with your particular link. It is impossible for Dini Group to predict the link conditions of all users, so the default settings are intended to work well on a very short, well-matched noise free link.

  • Page 182: Address Maps

    This map is only valid for the “MainTest” reference design. DDR registers are only meaningful in FPGAs F1, F2, F13, F14. The upper 4 bits are used by the Dini Group to distinguish FPGAs. F0 is hex ‘0’, F1 is hex ‘1’… F15 is hex ‘A’.
  • Page 183 FPGA F2 0x28100003 CLK_COUNTER Contains contents of DCLK counter FPGA F2 0x28100004 CLK_COUNTER Contains contents of SYSCLK counte FPGA F2 0x28000001 DDR2HIADDR upper address bits for DDR2 interface FPGA F2 0x28000003 HIADDRSIZE number of bits in DDR2HIADDR DN8000K10 User Guide www.dinigroup.com...

  • Page 184: Decoder

    D E S I G N FPGA F2 0x28000005 DDR2SIZEHIADDR The size of the DDR2 module. FPGA F2 0x28000007 DDR2TAPCNT0 Current IDELAY values of DDR2… FPGA F2 0x28000008 DDR2TAPCNT1 …interface 3.1.1 Decoder The following is an address decoder diagram. DN8000K10 User Guide www.dinigroup.com...
  • Page 185 FRAMCNT0 # of frames sent (32:0) 0x81 FRAMCNT1 # of frams sent (bits 47:32) 0x82 ERRCNT0 # of errors (32:0) 0x83 ERRCNT1 #of errors (47:0) 0x84 RXSTATE 3bits MGT RXSTATE 0x85 LASTDATA 32bits (Last frame’s data) DN8000K10 User Guide www.dinigroup.com...

  • Page 186: Main Bus Signaling

    The user should use the Xilinx PULLDOWN on the DONE and VALID IO buffers to prevent these signals from changing state during an idle main bus. A write command is initiated by the configuration FPGA. DN8000K10 User Guide www.dinigroup.com...
  • Page 187 FPGA (MB[36]) AD[31:0] DATA ADDRESS (MB[31:0]) Spartan (MB[32]) One cycle after presenting the address, the configuration FGPA presents a 32 bit data on the AD bus. The user FPGA then asserts DONE 1-255 clock cycles late DN8000K10 User Guide www.dinigroup.com...

  • Page 189: Ordering Information

    Chapter Ordering Information C h a p t e r 6 : Dini Group part number DN8000K10 1 FPGA Options 1.1 FPGA F0, F12 Select an FPGA part to be supplied in the F0 and F12 position. These FPGAs slots are the only available with the FX family of Virtex 4 FPGAs.

  • Page 190: Configuration Fpga

    3 Optional Equipment 3.1 Rack mount Chassis The DN8000K10 is shipped on a steel base plate “carrier” to provide protection, stability and an easy way to transport the board. Optionally, the DN8000K10 can ship inside a 4U rack mount chassis. This carrier can be used externally to the chassis, as well as mounted inside the chassis.

  • Page 191: Daughter Cards

    R E F E R E N C E D E S I G N The fans mounted on the front panel of the chassis provide cooling when the DN8000K10 is operated with the chassis lid on. A 500W EPS power supply mounts inside the chassis and exhausts out the backside of the chassis.

  • Page 192: Third Party Equipment

    • DN8000K10DC400 card – 48 signals on Mictor connector, 124 signals on .1” pitch TP headers, 4 RocketIO channels, global clock input. • SRAM module for use in the 200-pin SODIMM sockets of the DN8000K10. QDRII, 300Mhz 64x2Mb • SRAM module for use in the 200-pin SODIMM socket. 64x2Mb Standard SDR SRAM.

  • Page 193: Common Problems

    Make sure that the clock your design uses is running with an Oscilloscope or the USB Controller program. Check the pin out in your constraint file against the schematic or the Dini Group supplied USF files. Common pin assignment mistakes are with the daughter card headers.

  • Page 194: Xst Is Giving Errors Because It Cannot Find Virtex4.V Or Resync.v

    The DN8000K10 cannot read my SmartMedia card. The RS232 port prints: Bad SM card format If you formatted the SmartMedia card using Windows, the DN8000K10 will no longer be able to read the file structure on the card. Reformat the card using the program on the User CD D:/3rdParty/SMFormat 5.1.6...

  • Page 195: There Is A Lot Of Deterministic Jitter (Dj) On My Rocketio Clock Signals

    Do you provide a board description file for ____? No. Just Certify. 5.2.5 Where is the VHDL reference design? The VHDL reference design will not be available at the initial release of the DN8000K10. Email support@dinigroup.com for a schedule •...

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