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User Manuals: Cyrix MediaGX x86-compatible processor
Manuals and User Guides for Cyrix MediaGX x86-compatible processor. We have
1
Cyrix MediaGX x86-compatible processor manual available for free PDF download: Data Book
Cyrix MediaGX Data Book (304 pages)
Enhanced Processor
Brand:
Cyrix
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
5
1 Overview
17
Architecture
19
Figure 1-1 Internal Block Diagram
19
Floating Point Unit
20
Integer Unit
20
Write-Back Cache Unit
20
Internal Bus Interface Unit
21
Memory Management Unit
21
Integrated Functions
21
Graphics Accelerator
21
Display Controller
22
Xpressram™ Memory Subsystem
22
PCI Controller
22
System Designs
23
Figure 1-2 System Block Diagram
23
Figure 1-3 Cx9210 Interface System Diagram
24
2 Signal Definitions
25
Figure 2-1 Functional Block Diagram
25
Pin Assignments
26
Table 2-1 Pin Type Definitions
26
Figure 2-2 352 BGA Pin Assignment Diagram
27
Table 2-2 352 BGA Pin Assignments - Sorted by Pin Number
28
Table 2-3 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name
30
Figure 2-3 320 SPGA Pin Assignment Diagram
32
Table 2-4 320 SPGA Pin Assignments - Sorted by Pin Number
33
Table 2-5 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name
35
Signal Descriptions
37
System Interface Signals
37
PCI Interface Signals
40
Memory Controller Interface Signals
44
Video Interface Signals
46
Power, Ground, and no Connect Signals
48
Cyrix Internal Test and Measurement Signals
49
Subsystem Signal Connections
50
Figure 2-4 Subsystem Signal Connections
50
Figure 2-5 PIXEL Signal Connections
51
Power Planes
52
Figure 2-6 BGA Recommended Split Power Plane and Decoupling
52
Figure 2-7 SPGA Recommended Split Power Plane and Decoupling
53
3 Processor Programming
55
Core Processor Initialization
55
Table 3-1 Initialized Core Register Controls
56
Instruction Set Overview
57
Lock Prefix
57
Register Sets
58
Table 3-2 Application Register Set
58
Application Register Set
59
Table 3-3 Segment Register Selection Rules
60
Table 3-4 EFLAGS Register
61
System Register Set
62
Table 3-5 System Register Set
62
Table 3-6 Control Registers Map
63
Table 3-7 CR4-CR0 Bit Definitions
64
Table 3-8 Effects of Various Combinations of EM, TS, and MP Bits
65
Table 3-9 Configuration Register Summary
66
Table 3-10 Configuration Register Map
67
Table 3-11 Configuration Registers
68
Table 3-12 Debug Registers
73
Table 3-13 DR7 and DR6 Bit Definitions
74
Table 3-14 Test Registers
75
Table 3-15 TR7-TR6 Bit Definitions
76
Figure 3-1 CPU Cache Architecture
77
Table 3-16 TR5-TR3 Bit Definitions
78
Table 3-17 Cache Test Operations
79
Model Specific Register
80
Time Stamp Counter
80
Address Spaces
81
I/O Address Space
81
Figure 3-2 Memory and I/O Address Spaces
81
Memory Address Space
82
Offset, Segment, and Paging Mechanisms
82
Offset Mechanism
83
Figure 3-3 Offset Address Calculation
83
Table 3-18 Memory Addressing Modes
83
Descriptors and Segment Mechanisms
84
Real and Virtual 8086 Mode Segment Mechanisms
84
Figure 3-4 Real Mode Address Calculation
84
Segment Mechanism in Protective Mode
85
Figure 3-5 Protected Mode Address Calculation
85
Figure 3-6 Selector Mechanisms
86
Figure 3-7 Selector Mechanism Caching
87
GDTR and LDTR Registers
88
Table 3-19 GDTR, LDTR and IDTR Registers
88
Descriptor Bit Structure
89
Table 3-20 Application and System Segment Descriptors
89
Table 3-21 Application and System Segment Descriptors Bit Definitions
90
Table 3-22 Application and System Segment Descriptors TYPE Bit Definitions
91
Gate Descriptors
92
Table 3-23 Gate Descriptors
92
Table 3-24 Gate Descriptors Bit Definitions
92
Multitasking and Task State Segments
93
Table 3-25 32-Bit Task State Segment (TSS) Table
94
Table 3-26 16-Bit Task State Segment (TSS) Table
95
Paging Mechanism
96
Figure 3-8 Paging Mechanism
96
Table 3-27 Directory Table Entry (DTE) and Page Table Entry (PTE)
97
Interrupts and Exceptions
98
Interrupts
98
Exceptions
99
Interrupt Vectors
99
Table 3-28 Interrupt Vector Assignments
100
Interrupt and Exception Priorities
101
Table 3-29 Interrupt and Exception Priorities
101
Exceptions in Real Mode
102
Error Codes
102
Table 3-30 Exception Changes in Real Mode
102
Table 3-31 Error Codes
102
Table 3-32 Error Code Bit Definitions
102
System Management Mode
103
Figure 3-9 System Management Memory Address Space
103
Figure 3-10 SMM Execution Flow
104
SMM Enhancements
104
SMM Operation
104
Table 3-33 SMI# and SMINT Recognition Requirements
104
SMM Configuration Registers
105
The SMI# Pin
105
SMM Memory Space Header
106
Table 3-34 SMM Memory Space Header
106
Table 3-35 SMM Memory Space Header Description
107
SMM Instructions
108
Table 3-36 SMM Instruction Set
108
SMI Generation
109
SMM Memory Space
109
SMI Service Routine Execution
110
Figure 3-11 SMI Nesting State Machine
111
Figure 3-12 SMM and Suspend Mode State Diagram
112
Shutdown and Halt
113
Protection
113
Privilege Levels
113
I/O Privilege Levels
114
Privilege Level Transfers
114
Initialization and Transition to Protected Mode
115
Table 3-37 Descriptor Types Used for Control Transfer
115
Virtual 8086 Mode
116
Memory Addressing
116
Protection
116
Interrupt Handling
116
Entering and Leaving Virtual 8086 Mode
116
Floating Point Unit Operations
117
FPU (Floating Point Unit) Register Set
117
FPU Tag Word Register
117
FPU Status Register
117
FPU Mode Control Register
117
Table 3-38 FPU Registers
118
4 Integrated Functions
119
Figure 4-1 Internal Block Diagram
119
Integrated Functions Programming Interface
120
Graphics Control Register
120
Table 4-1 GCR Register
120
Figure 4-2 Mediagx Processor Memory Space
121
Control Registers
122
Graphics Memory
122
Table 4-2 Display Resolution Skip Counts
122
L1 Cache Controller
123
Table 4-3 L1 Cache Bitblt Register Summary
123
Table 4-4 L1 Cache Bitblt Registers
124
Table 4-5 Scratchpad Organization
125
Display Driver Instructions
126
Table 4-6 Display Driver Instructions
126
CPU_READ/CPU_WRITE Instructions
127
Table 4-7 CPU-Access Instructions
127
Table 4-8 Address Map for CPU-Access Registers
127
Internal Bus Interface Unit
128
FPU Error Support
128
A20M Support
128
SMI Generation
128
640KB to 1MB Region
128
Internal Bus Interface Unit Registers
129
Table 4-9 Internal Bus Interface Unit Register Summary
129
Table 4-10 Internal Bus Interface Unit Registers
130
Table 4-11 Region-Control-Field Bit Definitions
131
Memory Controller
132
Figure 4-3 Memory Controller Block Diagram
132
Figure 4-4 Memory Array Configuration
133
Memory Array Configuration
133
Memory Organizations
134
Table 4-12 Synchronous DRAM Configurations
134
SDRAM Commands
135
Table 4-13 Basic Command Truth Table
135
Table 4-14 Address Line Programming During MRS Cycles
135
Memory Controller Register Description
137
Table 4-15 Memory Controller Register Summary
137
Table 4-16 Memory Controller Registers
138
Address Translation
143
Table 4-17 Auto LOI -- 2 Dimms, same Size, 1 DIMM Bank
144
Table 4-18 Auto LOI -- 2 Dimms, same Size, 2 DIMM Banks
144
Table 4-19 Non-Auto LOI -- 1 or 2 Dimms, Different Sizes, 1 DIMM Bank
145
Table 4-20 Non-Auto LOI -- 1 or 2 Dimms, Different Sizes, 2 DIMM Banks
145
Figure 4-5 Basic Read Cycle with a CAS Latency of Two
146
Memory Cycles
146
Figure 4-6 Basic Write Cycle
147
Figure 4-7 Auto Refresh Cycle
148
Figure 4-8 Read/Write Command to a New Row Address
148
Figure 4-9 SDCLKIN Clocking
149
SDRAM Interface Clocking
149
Figure 4-10 Effects of SHFTSDCLK Programming Bits Example
150
Graphics Pipeline
151
Bitblt/Vector Engine
151
Figure 4-11 Graphics Pipeline Block Diagram
151
Master/Slave Registers
152
Pattern Generation
152
Table 4-21 Graphics Pipeline Registers
152
Figure 4-12 Example of Monochrome Patterns
153
Figure 4-13 Example of Dither Patterns
153
Source Expansion
154
Raster Operations
154
Table 4-22 GP_RASTER_MODE Bit Patterns
154
Table 4-23 Common Raster Operations
154
Graphics Pipeline Register Descriptions
155
Table 4-24 Graphics Pipeline Configuration Register Summary
155
Table 4-25 Graphics Pipeline Configuration Registers
157
Display Controller
161
Figure 4-14 Display Controller Block Diagram
161
Compression Technology
162
Display FIFO
162
Hardware Cursor
163
Motion Video Acceleration Support
163
Display Modes
164
Display Timing Generator
164
Dither and Frame-Rate Modulation
164
Table 4-26 TFT Panel Display Modes
165
Table 4-27 TFT Panel Data Bus Formats
166
Table 4-28 CRT RAMDAC Data Bus Formats
166
Table 4-29 CRT Display Modes
167
Figure 4-15 Pixel Arrangement Within a DWORD
168
Graphics Memory Map
168
Display Controller Registers
170
Table 4-30 Display Controller Register Summary
170
Table 4-31 Display Controller Configuration and Status Registers
173
Memory Organization Registers
180
Table 4-32 Display Controller Memory Organization Registers
181
Timing Registers
183
Table 4-33 Display Controller Timing Registers
184
Cursor Position Registers
187
Table 4-34 Display Controller Cursor Position Registers
187
Color Registers
189
Table 4-35 Display Controller Color Registers
189
Palette Access Registers
190
Table 4-36 Display Controller Palette and RAM Diagnostic Registers
190
Cx5520/Cx5530 Display Controller Interface
192
Figure 4-16 Display Controller Signal Connections
192
Figure 4-17 Video Port Data Transfer (Cx5520/Cx5530)
193
PCI Controller
194
X-Bus PCI Slave
194
X-Bus PCI Master
194
PCI Arbiter
194
Generating Configuration Cycles
194
Generating Special Cycles
194
Table 4-37 Special-Cycle Code to CONFIG_ADDRESS
194
PCI Configuration Space Control Registers
195
Table 4-38 PCI Configuration Registers
195
PCI Configuration Space Registers
196
Table 4-39 Format for Accessing the Internal PCI Configuration Registers
196
Table 4-40 PCI Configuration Space Register Summary
196
Table 4-41 PCI Configuration Registers
197
PCI Cycles
201
Figure 4-18 Basic Read Operation
201
Figure 4-19 Basic Write Operation
202
Figure 4-20 Basic Arbitration
203
5 Virtual Subsystem Architecture
205
Virtual VGA
206
Traditional VGA Hardware
206
Table 5-1 Standard VGA Modes
207
Mediagx™ Virtual VGA
209
Datapath Elements
209
Video Refresh
210
Mediagx VGA Hardware
211
Table 5-2 VGA Configuration Registers Summary
212
Table 5-3 VGA Configuration Registers
213
VGA Video BIOS
215
Virtual VGA Register Descriptions
215
Table 5-4 Virtual VGA Register Summary
215
Table 5-5 Virtual VGA Registers
216
6 Power Management
217
APM Support
217
CPU Suspend Command Registers
218
Suspend Modulation
218
3-Volt Suspend Mode
219
Suspend Mode and Bus Cycles
220
Initiating Suspend with SUSP
220
Figure 6-1 SUSP#-Initiated Suspend Mode
220
Initiating Suspend with HALT
221
Figure 6-2 HALT-Initiated Suspend Mode
221
Responding to a PCI Access During Suspend Mode
222
Figure 6-3 PCI Access During Suspend Mode
222
Stopping the Input Clock
223
Figure 6-4 Stopping SYSCLK During Suspend Mode
223
Mediagx Processor Serial Bus
224
Serial Packet Transmission
224
Power Management Registers
225
Table 6-1 Power Management Register Summary
225
Table 6-2 Power Management Control and Status Registers
226
Table 6-3 Power Management Programmable Address Region Registers
228
7 Electrical Specifications
229
Part Numbers
229
Electrical Connections
229
Power/Ground Connections and Decoupling
229
Power Sequencing the Core and I/O Voltages
229
NC-Designated Pins
229
Table 7-1 Part Numbers
229
Pull-Up and Pull-Down Resistors
230
Unused Input Pins
230
Table 7-2 Pins with 20-Kohm Internal Resistor
230
Absolute Maximum Ratings
231
Table 7-3 Absolute Maximum Ratings
231
Recommended Operating Conditions
232
Table 7-4 Recommended Operating Conditions
232
DC Characteristics
233
Table 7-5 DC Characteristics (at Recommended Operating Conditions)
233
AC Characteristics
234
Figure 7-1 Drive Level and Measurement Points for Switching Characteristics
234
Table 7-6 Drive Level and Measurement Points for Switching Characteristics
234
Figure 7-2 SYSCLK Timing and Measurement Points
235
Table 7-7 Clock Signals
235
Figure 7-3 DCLK Timing and Measurement Points
236
Figure 7-4 SDCLK, SDCLK[3:0] Timing and Measurement Points
236
Table 7-8 System Signals
236
Figure 7-5 Output Timing
237
Figure 7-6 Input Timing
237
Table 7-9 PCI Interface Signals
237
Figure 7-7 Output Valid Timing
238
Figure 7-8 Setup and Hold Timings - Read Data in
238
Table 7-10 SDRAM Interface Signals
238
Figure 7-9 Graphics Port Timing
239
Table 7-11 Video Interface Signals
239
Figure 7-10 Video Port Timing
240
Figure 7-11 DCLK Timing
240
Figure 7-12 TCK Timing and Measurement Points
241
Table 7-12 JTAG AC Specification
241
Figure 7-13 JTAG Test Timings
242
8 Package Specifications
243
Thermal Characteristics
243
Table 8-1 Case to Ambient Thermal Resistance Examples for 70°C Product
244
Table 8-2 Case to Ambient Thermal Resistance Examples for 85°C Product
244
Mechanical Package Outlines
245
Figure 8-1 352-Terminal BGA Mechanical Package Outline
245
Figure 8-2 320-Pin SPGA Mechanical Package Outline
246
Table 8-3 Mechanical Package Outline Legend
247
9 Instruction Set
249
General Instruction Set Format
250
Table 9-1 General Instruction Set Format
250
Table 9-2 Instruction Fields
250
Opcode
251
Prefix (Optional)
251
Table 9-3 Instruction Prefix Summary
251
Table 9-4 W Field Encoding
251
Table 9-5 D Field Encoding
252
Table 9-6 S Field Encoding
252
Table 9-7 Eee Field Encoding
252
Mod and R/M Byte (Memory Addressing)
253
Table 9-8 General Registers Selected by Mod R/M Fields and W Field
253
Table 9-9 Mod R/M Field Encoding
253
Reg Field
254
Table 9-10 General Registers Selected by Reg Field
254
Table 9-11 Sreg2 Field Encoding
254
Table 9-12 Sreg3 Field Encoding
254
S-I-B Byte (Scale, Indexing, Base)
255
Table 9-13 Ss Field Encoding
255
Table 9-14 Index Field Encoding
255
Table 9-15 Mod Base Field Encoding
255
CPUID Instruction
256
Table 9-16 CPUID Levels Summary
256
Standard CPUID Levels
257
Table 9-17 CPUID Data Returned When EAX = 0
257
Table 9-18 EAX, EBX, ECX CPUID Data Returned When EAX = 1
257
Table 9-19 EDX CPUID Data Returned When EAX = 1
258
Table 9-20 Standard CPUID with EAX = 0000 0002H
258
Extended CPUID Levels
259
Table 9-21 Maximum Extended CPUID Level
259
Table 9-22 EAX, EBX, ECX CPUID Data Returned When EAX = 8000 0001H
259
Table 9-23 EDX CPUID Data Returned When EAX = 8000 0001H
259
Table 9-24 Official CPU Name
260
Table 9-25 Standard CPUID with EAX = 8000 0005H
260
Processor Core Instruction Set
261
Table 9-26 Processor Core Instruction Set Table Legend
261
Table 9-27 Processor Core Instruction Set Summary
262
FPU Instruction Set
276
Table 9-28 FPU Instruction Set Table Legend
276
Table 9-29 FPU Instruction Set Summary
277
MMX™ Instruction Set
282
Table 9-30 MMX Instruction Set Table Legend
282
Table 9-31 MMX Instruction Set Summary
283
Cyrix Extended MMX™ Instruction Set
288
Table 9-32 Cyrix Extend MMX Instruction Set Table Legend
288
Table 9-33 Cyrix Extended MMX Instruction Set Summary
289
Appendix A Support Documentation
291
Order Information
291
Data Book Revision History
292
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