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Cyrix MediaGX Data Book

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Data Book
Cyrix Corporation Confidential
October 29, 1998 - Revision 2.0
Addenda and other updates for this manual can be obtained from
Cyrix Web site: www.cyrix.com.

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Summary of Contents for Cyrix MediaGX

  • Page 1 Data Book Cyrix Corporation Confidential October 29, 1998 - Revision 2.0 Addenda and other updates for this manual can be obtained from Cyrix Web site: www.cyrix.com.
  • Page 2 Cyrix patents, copyrights, or other intellectual property rights pertaining to any machine or combination of Cyrix devices is hereby granted. Cyrix products are not intended for use in any medical, life saving, or life sustaining systems. Information in this document is subject to change without notice.
  • Page 3 Memory-Read Bypassing x86 instruction set compatible and supports MMX - Six-stage integer pipeline technology. - XpressRAM™ and XpressGRAPHICS™ This processor is the latest member of the Cyrix ♦ MediaGX™ MMX™-Enhanced Processor MediaGX family, offering high performance, fully - Processor Integrated Functions:...
  • Page 4 Page iv Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 5: Table Of Contents

    ..... 32 2.2.6 Cyrix Internal Test and Measurement Signals ....33 Subsystem Signal Connections .
  • Page 6 3.12 Shutdown and Halt ........97 Cyrix Corporation Confidential...
  • Page 7 ........130 4.3.7 SDRAM Interface Clocking ......133 GXm_db_v2.0 Cyrix Corporation Confidential...
  • Page 8 Virtual VGA ........190 5.1.1 Traditional VGA Hardware ......190 viii Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 9 Table of Contents MediaGX™ Virtual VGA ....... . . 193 5.2.1 Datapath Elements...
  • Page 10 MMX™ Instruction Set ........266 Cyrix Extended MMX™ Instruction Set ......272 Appendix A Support Documentation .
  • Page 11 Internal Block Diagram ....... . . 103 Figure 4-2 MediaGX Processor Memory Space ......105 Figure 4-3 Memory Controller Block Diagram .
  • Page 12 352-Terminal BGA Mechanical Package Outline ....229 Figure 8-2 320-Pin SPGA Mechanical Package Outline ..... . 230 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 13 Table 3-30 Exception Changes in Real Mode ......86 GXm_db_v2.0 Cyrix Corporation Confidential xiii...
  • Page 14 Table 4-27 TFT Panel Data Bus Formats......150 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 15 JTAG AC Specification ....... . . 225 Table 8-1 Case to Ambient Thermal Resistance Examples for 70°C Product... 228 GXm_db_v2.0 Cyrix Corporation Confidential...
  • Page 16 ......267 Table 9-32 Cyrix Extend MMX Instruction Set Table Legend....272 Table 9-33 Cyrix Extended MMX Instruction Set Summary .

  • Page 17: Overview

    VGA and 16-bit industry standard audio emulation. with MMX™ technology. This latest generation of XpressAUDIO technology eliminates much of the the MediaGX processor enables a new class of low hardware traditionally associated with audio func- cost, premium performance notebook/desktop tions.
  • Page 18 • Supports up to 1280x1024x8 BPP and 1024x768x16 BPP Note: GUI (Graphical User Interface) graphics acceleration is pure hardware. XpressRAM™ Memory Subsystem • Provides Cyrix’s 16-bit XpressAUDIO™ • Memory control/interface directly from CPU 2D Graphics Accelerator • 64-Bit wide memory bus • Graphics pipeline performance significantly •...

  • Page 19: Architecture

    Architecture Architecture The MediaGX processor is divided into major func- tional blocks (as shown in Figure 1-1): The Cyrix MediaGX MMX-Enhanced Processor • Integer Unit represents a new generation of x86-compatible 64- • Floating Point Unit (FPU) bit microprocessors with sixth-generation features.

  • Page 20: Integer Unit

    AC1 and AC2. If the instruction refers to a memory operand, AC1 calcu- The MediaGX processor provides the ability to allo- lates a linear memory address for the instruction. cate a portion of the L1 cache as a scratchpad,...

  • Page 21: Memory Management Unit

    Internal Bus Interface Unit The internal bus interface unit provides a bridge 1.2.1 Graphics Accelerator from the MediaGX processor to the integrated system functions (i.e., memory subsystem, display The graphics accelerator is a full-featured GUI controller, graphics pipeline) and the PCI bus inter- (Graphical User Interface) accelerator.

  • Page 22: Display Controller

    1.2.2 Display Controller The memory controller handles multiple requests for memory data from the MediaGX processor, the The display port is a direct interface to the graphics accelerator and the display controller. The Cx5520/Cx5530 which drives a TFT flat panel memory controller contains extensive buffering display, LCD panel, or a CRT display.

  • Page 23: System Designs

    Cyrix Cx9210™ Dual-Scan Flat Panel Display As described in separate manuals, the Cx5520 and Controller for designs that need to interface to a Cx5530 enable the full features of the MediaGX DSTN panel (instead of TFT panel). processor with MMX support. These features...

  • Page 24: Figure 1-3 Cx9210 Interface System Diagram

    Figure 1-3 shows an example of a Cx9210 STN (DSTN) flat panel LCD. It connects to the interface in a typical MediaGX Integrated digital RGB output of a MediaGX™ processor or Subsystem. Cx55 x 0 and drives the graphics data onto a dual-...

  • Page 25: Signal Definitions

    Integrated x86 Solution with MMX™ Support Signal Definitions This section describes the external interface of the organized by their functional interface groups MediaGX processor. Figure 2-1 shows the signals (internal test and electrical pins are not shown). SYSCLK MD[63:0] CLKMODE[2:0]...

  • Page 26: Pin Assignments

    Pin Assignments Pin Assignments Table 2-1 Pin Type Definitions The MediaGX MMX-Enhanced processor is avail- Mnemonic Definition able in two packages, a 352 BGA package and a Standard input pin. 320 SPGA package. Bidirectional pin. The pin assignment for the 352 BGA is shown in Totem-pole output.

  • Page 27: Figure 2-2 352 Bga Pin Assignment Diagram

    '40 &.($ Note: Signal names have been abbreviated in this figure due to space constraints. = GND terminal = PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO) Figure 2-2 352 BGA Pin Assignment Diagram GXm_db_v2.0 Cyrix Corporation Confidential Page 11...

  • Page 28: Table 2-2 352 Bga Pin Assignments - Sorted By Pin Number

    L23 VSS T23 VSS B12 PAR C26 MD35 F24 MD38 L24 MD11 T24 DQM0 B13 AD14 D1 GNT0# F25 MD7 L25 MD43 T25 DQM4 B14 AD12 D2 TDI F26 MD39 L26 MD12 T26 DQM1 Page 12 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 29 Y4 VCC2 AC11 VSS AD16 CKEB AE21 MD17 AF26 VSS Y23 VCC2 AC12 VSS AD17 VCC2 AE22 DQM7 Y24 VCC2 AC13 VSS AD18 MD51 AE23 CS3# Y25 VCC2 AC14 VSS AD19 MD18 AE24 MA12 GXm_db_v2.0 Cyrix Corporation Confidential Page 13...

  • Page 30: Table 2-3 352 Bga Pin Assignments - Sorted Alphabetically By Signal Name

    AC26 MD42 REQ0# E3 (PU) C/BE3# MA11 AD24 MD43 REQ1# H3 (PU) CKEA AF24 MA12 AE24 MD44 REQ2# D3 (PU) CKEB AD16 MD45 RESET CLKMODE0 MD46 RW_CLK CLKMODE1 MD47 SDCLK_IN CLKMODE2 MD48 AD21 SDCLK_OUT Page 14 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 31 AD10 AF26 VCC2 VCC3 AD20 WEA# VCC2 VCC3 AE10 WEB# VCC2 VCC3 AE20 Note: PU/PD indicates pin is VCC2 VCC3 AF10 internally connected to a 20-kohm pull-up/- VCC2 VCC3 AF20 down resistor. VCC2 VID_CLK GXm_db_v2.0 Cyrix Corporation Confidential Page 15...

  • Page 32: Figure 2-3 320 Spga Pin Assignment Diagram

    Note: Signal names have been abbreviated in this figure due to space constraints. = Denotes GND terminal = Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO) Figure 2-3 320 SPGA Pin Assignment Diagram Page 16 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 33: Table 2-4 320 Spga Pin Assignments - Sorted By Pin Number

    U1 VSS AC1 VCC2 C3 AD31 E9 VCC2 L3 VCC2 U3 VCC3 AC3 VCC2 C5 AD26 E11 VCC2 L5 VCC2 U5 VSS AC5 VCC2 C7 AD23 E13 VSS L33 VCC2 U33 VSS AC33 VCC2 GXm_db_v2.0 Cyrix Corporation Confidential Page 17...
  • Page 34 AN13 VCC3 AH32 MA10 AK14 MD29 AL33 CKEA AN15 MD28 AH34 MA8 AK16 MD27 AL35 MA11 AN17 MD26 AH36 MA6 AK18 MD56 AL37 VCC3 AN19 VSS AJ1 PCLK AK20 MD55 AM2 VID_DATA7 AN21 MD54 Page 18 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 35: Table 2-5 320 Spga Pin Assignments - Sorted Alphabetically By Signal Name

    PIXEL17 C/BE3# MA11 AL35 MD43 RASA# AB36 CKEA AL33 MA12 AM34 MD44 RASB# AB34 CKEB AN23 MD45 REQ0# E1 (PU) CLKMODE0 MD46 REQ1# K2 (PU) CLKMODE1 MD47 REQ2# E3 (PU) CLKMODE2 MD48 AM28 RESET GXm_db_v2.0 Cyrix Corporation Confidential Page 19...
  • Page 36 AE35 VCC2 VID_CLK VCC2 VID_DATA0 VCC2 VID_DATA1 AG33 VCC2 VID_DATA2 AG37 VCC2 VID_DATA3 VCC2 VID_DATA4 AJ13 VCC2 VID_DATA5 AJ19 VCC2 VID_DATA6 AJ25 VCC2 VID_DATA7 AJ31 VCC2 VID_RDY VCC2 VID_VAL AK34 VCC2 VOLDET AM36 AL15 Page 20 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 37: Signal Descriptions

    CLKMOD[2:0] inputs. The SYSCLK input is a fixed frequency which can only be stopped or varied when the MediaGX processor is in a full 3V Suspend. (Section 6.4 “3-Volt Suspend Mode” on page 203 for details regarding this mode.)
  • Page 38 This input is typically generated during the Power- On-Reset sequence. Note: Warm Reset does not require an input on the MediaGX processor since the function is virtualized using SMM. INTR...
  • Page 39 Suspend Request (PU) (PU) This signal is used to request that the MediaGX processor enter Suspend mode. After recognition of an active SUSP# input, the processor completes execution of the current instruc- tion, any pending decoded instructions and associated bus cycles.

  • Page 40: Pci Interface Signals

    1000 = Reserved 1001 = Reserved 1010 = Configuration Read 1011 = Configuration Write 1100 = Memory Read Multiple 1101 = Dual Address Cycle (Reserved) 1110 = Memory Read Line 1111 = Memory Write and Invalidate Page 24 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 41 AD[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. This pin is internally connected to a 20-kohm pull-up resistor. GXm_db_v2.0 Cyrix Corporation Confidential Page 25...
  • Page 42 DEVSEL# is detected within and up to the subtrac- tive decode clock, a master abort cycle will result expect for special cycles which do not expect a DEVSEL# returned. This pin is internally connected to a 20-kohm pull-up resistor. Page 26 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 43 Each master has its own GNT# line. GNT# can be pulled away at any time a higher REQ# is received or if the master does not begin a cycle within a mini- mum period of time (16 SYSCLKs). GXm_db_v2.0 Cyrix Corporation Confidential Page 27...

  • Page 44: Memory Controller Interface Signals

    CS[3:2]#. WEA#, R25, W33, Write Enable WEB# RAS#, CAS#, WE# and CKE are encoded to support the differ- ent SDRAM commands. WEA# is used with CS[1:0]#. WEB# is used with CS[3:2]#. Page 28 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 45 SDCLK[3:0] should be used with CS[3:0]#, respectively, for the Suspend mode to function correctly. SDCLK_IN AK12 SDRAM Clock Input The MediaGX processor samples the memory read data on this clock. Works in conjunction with the SDCLK_OUT signal. SDCLK_OUT AL13 SDRAM Clock Output This output is routed back to SDCLK_IN.

  • Page 46: Video Interface Signals

    PCLK Pixel Port Clock Pixel Port Clock represents the pixel dotclock or a 2x multiple of the dotclock for some 16-bit-per-pixel modes. It determines the data transfer rate from the MediaGX processor to the Cx5520/Cx5530. VID_CLK Video Clock Video Clock represents the video port clock to the Cx5520/Cx5530.
  • Page 47 When the Video Port is enabled, this bus drives Video (Y-U-V) data synchronous to the VID_CLK output. PIXEL[17:0] Refer Refer Graphics Pixel Data Bus to Table to Table This bus drives graphics pixel data synchronous to the PCLK output. GXm_db_v2.0 Cyrix Corporation Confidential Page 31...

  • Page 48: Power, Ground, And No Connect Signals

    Table (Total of (Total of VCC3 Refer Refer 3.3V (nominal) I/O Power Connection to Table to Table (Total of (Total of Q5, X2, No Connection A line designated as NC should be left disconnected. Page 32 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 49: Cyrix Internal Test And Measurement Signals

    Pin No. Type Description FLT# Float Float Outputs forces the MediaGX processor to float all outputs in the high-impedance state and to enter a power-down state. RW_CLK AL11 Raw Clock This output is the MediaGX processor clock. This debug signal can be used to verify clock operation.

  • Page 50: Subsystem Signal Connections

    Subsystem Signal Connections Subsystem Signal Connections As previously stated, the MediaGX Integrated Chip. Figure 2-4 shows the signal connections Subsystem with MMX support consists of two between the processor and the I/O companion chips. The MediaGX MMX-Enhanced Processor chip. and either the Cx5520 or Cx5530 I/O Companion...

  • Page 51: Figure 2-5 Pixel Signal Connections

    PIXEL16 PIXEL11 PIXEL15 PIXEL10 PIXEL14 PIXEL9 PIXEL13 PIXEL8 PIXEL12 PIXEL7 PIXEL11 PIXEL6 PIXEL10 PIXEL9 PIXEL8 PIXEL5 PIXEL7 PIXEL4 PIXEL6 PIXEL3 PIXEL5 PIXEL2 PIXEL4 PIXEL1 PIXEL3 PIXEL0 PIXEL2 PIXEL1 PIXEL0 Figure 2-5 PIXEL Signal Connections GXm_db_v2.0 Cyrix Corporation Confidential Page 35...

  • Page 52: Power Planes

    352 BGA - Top View 2.9V Plane (VCC2) Legend 3.3V Plane = High frequency capacitor (VCC3) = 220µF, low ESR capacitor = 3.3V connection = 2.9V connection Figure 2-6 BGA Recommended Split Power Plane and Decoupling Page 36 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 53: Figure 2-7 Spga Recommended Split Power Plane And Decoupling

    = 220µF, low ESR capacitor = 3.3V connection Note: Where signals cross plane splits, it is recommended to include AC decoupling between planes with 47pF capacitors. = 2.9V connection Figure 2-7 SPGA Recommended Split Power Plane and Decoupling GXm_db_v2.0 Cyrix Corporation Confidential Page 37...
  • Page 54 Power Planes Page 38 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 55: Processor Programming

    MediaGX™ MMX™-Enhanced Processor Integrated x86 Solution with MMX™ Support Processor Programming Core Processor Initialization The MediaGX processor is initialized when the This section describes the internal operations of RESET signal is asserted. The processor is placed the MediaGX MMX-Enhanced processor from a in real mode and the registers listed in Table 3-1 programmer’s point of view.

  • Page 56: Table 3-1 Initialized Core Register Controls

    Device Identification 1 Stepping and Revision ID (RO). See Table 3-11 on page 56 for bit definitions. Debug Register 7 0000 0400h See Table 3-13 on page 58 for bit definitions. Note: x = Undefined value Page 40 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 57: Instruction Set Overview

    Operand lengths of 8, 16, 32 or 48 bits are supported as well as 64 or 80 bits associated with The MediaGX processor instruction set can be floating-point instructions. Operand lengths of 8 or divided into nine types of operations: 32 bits are generally used when executing code •...

  • Page 58: Register Sets

    Each of these register sets are discussed in detail in the subsections that follow. Additional registers 2) The System Register Set contains the regis- to support integrated MediaGX processor ters typically reserved for operating-systems subsystems are described in Section 4.1 “Inte- programmers: control registers, system grated Functions Programming Interface”...

  • Page 59: Application Register Set

    This register also contains control bits that The MediaGX processor implements a stack using affect the operation of some instructions. the ESP register. This stack is accessed during the...

  • Page 60: Table 3-3 Segment Register Selection Rules

    Destination of STOS, MOVS, REP STOS, REP MOVS instructions None Other data references with effective address using base registers of: CS, ES, FS, GS, SS EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP CS, DS, ES, FS, GS Page 44 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 61: Table 3-4 Eflags Register

    The Flags Register contains status information and referred to as the Flags register that is used when controls certain operations on the MediaGX executing 8086 or 80286 code. Table 3-4 gives the processor. The lower 16 bits of this register are bit formats for the EFLAGS Register.

  • Page 62: System Register Set

    SMM registers. Debug Linear Breakpoint Registers Address 0 The Debug Registers provide debugging facilities Linear Breakpoint for the MediaGX processor and enable the use of Address 1 data access breakpoints and code execution Linear Breakpoint breakpoints. Address 2 Linear Breakpoint...

  • Page 63: Table 3-6 Control Registers Map

    31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CR4 Register RSVD RSVD CR3 Register PDBR (Page Directory Base Register) RSVD RSVD CR2 Register PFLA (Page Fault Linear Address) CR1 Register RSVD CR0 Register RSVD RSVD Machine Status Word (MSW) GXm_db_v2.0 Cyrix Corporation Confidential Page 47...

  • Page 64: Table 3-7 Cr4-Cr0 Bit Definitions

    Protected Mode Enable: Enables the segment based protection mechanism. If PE = 1, protected mode is enabled. If PE = 0, the CPU operates in real mode and addresses are formed as in an 8086-style CPU. Refer to Section 3.13 “Protection” on page 97. Page 48 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 65: Table 3-8 Effects Of Various Combinations Of Em, Ts, And Mp Bits

    Effects of Various Combinations of EM, TS, and MP Bits CR0[3:1] Instruction Type WAIT Execute Execute Execute Execute Execute Fault 7 Fault 7 Fault 7 Execute Fault 7 Execute Fault 7 Execute Fault 7 Fault 7 Fault 7 GXm_db_v2.0 Cyrix Corporation Confidential Page 49...

  • Page 66: Table 3-9 Configuration Register Summary

    Table 3-11 on page 55 DIR0 — Device ID 0 Table 3-11 on page 56 DIR1 — Device ID 1 Table 3-11 on page 56 *Note: MAPEN = Index C3h[4] (CCR3) and SMI_LOCK = Index C3h[0] (CCR3). Page 50 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 67: Table 3-10 Configuration Register Map

    B0000h to A0000h to BFFFFh B7FFFh AFFFFh VGAM0 (BAh) VGA Mask Register Bits [7:0] VGAM1 (BBh) VGA Mask Register Bits [15:8] VGAM2 (BCh) VGA Mask Register Bits [23:16] VGAM3 (BDh) VGA Mask Register Bits [31:24] GXm_db_v2.0 Cyrix Corporation Confidential Page 51...

  • Page 68: Table 3-11 Configuration Registers

    If = 1: Prohibits changing the state of the NW bit (CR0[29]) (refer to Table 3-7 on page 48). Set to 1 after setting NW. RSVD Reserved: Set to 0. Note: All bits are cleared to zero at reset. Page 52 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 69 If = 1: SMM Address Region Register (SMAR[31:0]), SMAC (CCR1[2]), USE_SMI (CCR1[1]) cannot be modified unless in SMM routine. Once set, SMI_LOCK can only be cleared by asserting the RESET pin. Note: All bits are cleared to zero at reset. GXm_db_v2.0 Cyrix Corporation Confidential Page 53...
  • Page 70 If = 1: Non-maskable Interrupts (NMIs) are acknowledged. RSVD Reserved: Set to 0. EMMX Cyrix Extended MMX Instructions Enable: If = 1: Cyrix extended MMX instructions are enabled Index 20h PCR — Performance Control Register (R/W) Default Value = 07h LSSER Load/Store Serialize Enable (Reorder Disable): LSSER should be set to ensure that memory- mapped I/O devices operating outside of the address range 640K to 1M will operate correctly.
  • Page 71 1110 = 32MB 0011 = 16KB 0111 = 256KB 1011 = 4MB 1111 = 4KB (same as 0001) Note: SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write these registers/bits. GXm_db_v2.0 Cyrix Corporation Confidential Page 55...
  • Page 72 DIR1 If DIR1 is 30h-33h = MediaGX MMX-Enhanced processor revision 1.0-2.3 If DIR1 is 34h-4Fh = MediaGX MMX-Enhanced processor revision 2.4-3.x If DIR1 is 50h or greater = MediaGX MMX-Enhanced processor revision 4.0 and up. Page 56 Cyrix Corporation Confidential...

  • Page 73: Table 3-12 Debug Registers

    Six debug registers (DR0-DR3, DR6 and DR7) breakpoints. Each breakpoint is further specified by support debugging on the MediaGX processor. bits in the Debug Control Register (DR7). For each Memory addresses loaded in the debug registers, breakpoint address in DR0-DR3, there are corre- referred to as “breakpoints,”...

  • Page 74: Table 3-13 Dr7 And Dr6 Bit Definitions

    T bit in the TSS set. BS is set by the processor if the debug exception was triggered by the single-step execution mode (TF flag, bit 8, in EFLAGS set). Note: n = 0, 1, 2, and 3 Page 58 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 75: Table 3-14 Test Registers

    0 PL TR6 Register Linear Address D D# U U# R R# 0 TR5 Register RSVD Line Selection Set/ Dword TR4 Register Cache Tag Address Cache Dirty Bits LRU Bits TR3 Register Cache Data GXm_db_v2.0 Cyrix Corporation Confidential Page 59...

  • Page 76: Table 3-15 Tr7-Tr6 Bit Definitions

    11 = Match if D, U, or R bit is either a 1 or 0 Undefined RSVD Reserved: Set to 0. Command Bit: If C = 1: TLB lookup. If C = 0: TLB write. Page 60 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 77: Figure 3-1 Cpu Cache Architecture

    152 --- 0 152 --- 0 2 --- 0 = Cache Entry (153 bits) Tag Address (20 bits) Data (128 bits) Valid Status (1 bit) Dirty Status (4 bits) Figure 3-1 CPU Cache Architecture GXm_db_v2.0 Cyrix Corporation Confidential Page 61...

  • Page 78: Table 3-16 Tr5-Tr3 Bit Definitions

    RSVD Reserved: Set to 0. TR3 Register 31:0 Cache Data Cache Data: Flush buffer read: Data accessed from the cache flush buffer. Fill buffer write: Data to be written into the cache fill buffer. Page 62 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 79: Table 3-17 Cache Test Operations

    Cache line (127:0) --> flush buffer (127:0). MOV dest, TR4 Cache line tag address, valid/LRU/dirty bits --> dest. Cache Flush MOV TR5, 3h Control = 11 = cache flush, all cache valid bits = 0. GXm_db_v2.0 Cyrix Corporation Confidential Page 63...

  • Page 80: Model Specific Register

    The RDMSR and WRMSR instructions are privi- During a TSC write, the contents of EX:EAX are leged instructions. loaded into the TSC. The MediaGX MMX-Enhanced processor contains The RDMSR and WRMSR instructions are privi- one 64-bit model specific register (MSR10) the leged instructions.

  • Page 81: Address Spaces

    Address Spaces Address Spaces The MediaGX processor can directly address addresses 22h and 23h and are accessed using either memory or I/O space. Figure 3-2 illustrates the standard IN and OUT instructions. the range of addresses available for memory The configuration registers are modified by writing address space and I/O address space.

  • Page 82: Memory Address Space

    Virtual memory is often imple- mented using paging. Either or both of these mechanisms can be used for management of the MediaGX processor memory address space. Page 66 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 83: Offset Mechanism

    Based Scaled Index OA = [BASE] + ([INDEX] * SF) Based Index with OA = [BASE] + [INDEX] + DP Displacement Based Scaled Index OA = [BASE] + ([INDEX] * SF) + DP with Displacement GXm_db_v2.0 Cyrix Corporation Confidential Page 67...

  • Page 84: Descriptors And Segment Mechanisms

    1MB of memory. In this mode a selector 12 High Order Address Bits 000h Offset Address Offset Mechanism Linear Address (Physical Address) Selected Segment X 16 Register Base Address Figure 3-4 Real Mode Address Calculation Page 68 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 85: Segment Mechanism In Protective Mode

    The segment registers are used to store segment selectors. In protective mode, the segment Offset Address Offset Mechanism Linear Physical Optional Memory Address Address Paging Mechanism Segment Base Address Selector Mechanism Figure 3-5 Protected Mode Address Calculation GXm_db_v2.0 Cyrix Corporation Confidential Page 69...

  • Page 86: Figure 3-6 Selector Mechanisms

    3 2 1 INDEX INSTRUCTION OFFSET Segment Descriptor Segment B a se Linear Physical Address Address Address p = Paging Mechanism GDT or LDT Descriptor Table Main Memory Protective Mode Figure 3-6 Selector Mechanisms Page 70 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 87: Figure 3-7 Selector Mechanism Caching

    Caching Cached Segment and Descriptor Segment Descriptor TI = 0 Cached Selector Segment Global Descriptor Used If Base Table Available Address TI = 1 Segment Descriptor Local Descriptor Table Figure 3-7 Selector Mechanism Caching GXm_db_v2.0 Cyrix Corporation Confidential Page 71...

  • Page 88: Gdtr And Ldtr Registers

    SELECTOR field. Table 3-19 GDTR, LDTR and IDTR Registers 16 15 14 13 12 11 10 9 GDTR Register BASE LIMIT IDTR Register BASE LIMIT LDTR Register SELECTOR Page 72 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 89: Descriptor Bit Structure

    31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Memory Offset +4 BASE[31:24] LIMIT[19:16] TYPE BASE[23:16] Memory Offset +0 BASE[15:0] LIMIT[15:0] GXm_db_v2.0 Cyrix Corporation Confidential Page 73...

  • Page 90: Table 3-21 Application And System Segment Descriptors Bit Definitions

    Bit 10 = Conforming if bit 12 = 1 Bit 10 = Expand Down if bit 12 = 0 Bit 9 = Readable, if Bit 12 = 1 Bit 9 = Writable, if Bit 12 = 0 Bit 8 = Accessed Page 74 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 91: Table 3-22 Application And System Segment Descriptors Type Bit Definitions

    32-Bit Trap Gate Code Execute/Read-Only, conforming accessed S = Code Segment (not Data Segment) A = Accessed E = Expand Down C = Conforming Code Segment W = Write Enable R = Read Enable GXm_db_v2.0 Cyrix Corporation Confidential Page 75...

  • Page 92: Gate Descriptors

    1110 = 32-bit interrupt gate 0110 = 16-bit interrupt gate 1111 = 32-bit trap gate 0111 = 16-bit trap gate PARAMETERS Parameters: Number of parameters to copy from the caller’s stack to the called proce- dure’s stack. Page 76 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 93: Multitasking And Task State Segments

    The I/O Map Base Address field in the 32-bit TSS loaded, the TR selector field indexes a TSS points to an I/O permission bit map that often descriptor that must reside in the Global Descriptor follows the TSS at location +68h. Table (GDT). GXm_db_v2.0 Cyrix Corporation Confidential Page 77...

  • Page 94: Table 3-25 32-Bit Task State Segment (Tss) Table

    ESP for CPL = 2 +14h SS for CPL = 1 +10h ESP for CPL = 1 SS for CPL = 0 ESP for CPL = 0 Back Link (Old TSS Selector) Note: 0 = Reserved Page 78 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 95: Table 3-26 16-Bit Task State Segment (Tss) Table

    SS for Privilege Level 0 SP for Privilege Level 1 SS for Privilege Level 1 SP for Privilege Level 1 SS for Privilege Level 0 SP for Privilege Level 0 Back Link (Old TSS Selector) GXm_db_v2.0 Cyrix Corporation Confidential Page 79...

  • Page 96: Paging Mechanism

    Page Table Index Page Frame Offset (DTI) (PTI) (PFO) Main TLB DTE Cache 32-Entry 2-Entry 4-Way Set Fully Associative Associative -4KB Physical Page Control Directory Table Page Table Memory Register External Memory Figure 3-8 Paging Mechanism Page 80 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 97: Table 3-27 Directory Table Entry (Dte) And Page Table Entry (Pte)

    If = 1: The page is present in RAM and the remaining DTE/PTE bits are validated If = 0: The page is not present in RAM and the remaining DTE/PTE bits are available for use by the programmer. GXm_db_v2.0 Cyrix Corporation Confidential Page 81...

  • Page 98: Interrupts And Exceptions

    TLB hits. The on the MediaGX processor: TLB is a four-way set associative 32-entry page • Non-maskable Interrupt (NMI pin) table cache that automatically keeps the most •...

  • Page 99: Exceptions

    2. Illegal opcodes including faulty specified by loading the debug registers (DR0- FPU instructions will cause an illegal opcode DR7) with the appropriate values. exception, interrupt vector 6. NMI interrupts are GXm_db_v2.0 Cyrix Corporation Confidential Page 83...

  • Page 100: Table 3-28 Interrupt Vector Assignments

    Table 3-28 Interrupt Vector Assignments Interrupt Exception Vector Function Type Divide error Fault Debug exception Trap/Fault* NMI interrupt Breakpoint Trap Interrupt on overflow Trap BOUND range exceeded Fault Invalid opcode Fault Page 84 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 101: Interrupt And Exception Priorities

    INTR interrupts are both detected at a task whose task state segment (TSS) is partially the same instruction boundary, the MediaGX not present. A TSS can be partially not present if processor services the NMI interrupt first.

  • Page 102: Exceptions In Real Mode

    Fault selector. trying to invoke exception or hardware interrupt handler. Segment Index of faulty TI bit of faulty selector If =1, exception occurred while Fault selector. trying to invoke exception or hardware interrupt handler. Page 86 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 103: System Management Mode

    SMM address space (Figure 3-9). System Management Mode (SMM) is usually employed for system power management or soft- The MediaGX processor extends System Manage- ware-transparent emulation of I/O peripherals. ment Mode (SMM) to support the virtualization of SMM mode is entered through a hardware signal many devices, including VGA video.

  • Page 104: Smm Enhancements

    Address Space Base Address (The configuration registers are discussed in detail in Section 3.3.2.2 “Configuration Registers” on page 50.) RSM Instruction Restores CPU State Using Header Information Normal Execution Resumes Figure 3-10 SMM Execution Flow Page 88 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 105: The Smi# Pin

    SMM memory space SMM code region and its size limit. This SMAR header located at the top of SMM memory space. register is identical to many of the Cyrix proces- After saving the header, the CPU enters real mode sors.

  • Page 106: Smm Memory Space Header

    The Next IP points to the instruction that will be (offset -40h) of the header for the MediaGX executed after exiting SMM. The contents of processor. Memory data will be stored overlapping...

  • Page 107: Table 3-35 Smm Memory Space Header Description

    I/O cycles caused an SMI# trap. Memory Address Physical address of the write operation that caused the SMI. 4 Bytes Note: INSx = INS, INSB, INSW or INSD instruction. OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction. GXm_db_v2.0 Cyrix Corporation Confidential Page 91...

  • Page 108: Smm Instructions

    SMM Instructions The SMM instructions, listed in Table 3-36, can be executed only if all the conditions listed below are The MediaGX processor core automatically saves the met. minimal amount of CPU state information when entering an SMM cycle that allows fast SMM 1) USE_SMI = 1.

  • Page 109: Smm Memory Space

    4) SMAC = 1 SMI. If SMI# is asserted to the CPU during a software Memory reads are not trapped by the MediaGX SMI, the hardware SMI# is serviced after the soft- processor. The MediaGX processor traps I/O ware SMI has been exited by execution of the RSM addresses for VGA in the following regions: 3B0h instruction.

  • Page 110: Smi Service Routine Execution

    IRET, is executed. The (CS) register is loaded with the base, as defined by RSM instruction causes the MediaGX processor the SMAR register, and a limit of 4 GBytes. The core to restore the CPU state using the SMM...

  • Page 111: Figure 3-11 Smi Nesting State Machine

    D. A second-level (nested) SMI interrupt is received by the processor. This SMI is taken even though the processor is in SMM because the SMI_NEST bit is set high. The SMI_NEST Nested SMI Status Figure 3-11 SMI Nesting State Machine GXm_db_v2.0 Cyrix Corporation Confidential Page 95...

  • Page 112: Figure 3-12 Smm And Suspend Mode State Diagram

    Suspend mode. While in the SMI service routine, tion from the operating system or application soft- the MediaGX processor core can enter Suspend ware, the reception of an SMI# interrupt causes the mode either by (1) executing a halt (HLT) instruc- CPU to exit Suspend mode and enter SMM.

  • Page 113: Shutdown And Halt

    The and generates a special Halt bus cycle. The ability of a task to access a segment depends on MediaGX processor core then drives out a special the: Stop Grant bus cycle and enters a low-power Suspend mode if the SUSP_HLT bit in CCR2 •...

  • Page 114: I/O Privilege Levels

    SS and ESP are loaded with the new stack pointer and the previous stack pointer is saved on the new stack. When returning to the original privilege level, the RET or IRET instruction restores the SS and ESP of the less-privileged stack. Page 98 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 115: Initialization And Transition To Protected Mode

    Protected Mode Gate descriptors described in Section 3.7.5 “Gate Descriptors” on page 76, provide protection for The MediaGX processor core switches to real privilege transfers among executable segments. mode immediately after RESET. While operating in Gates are used to transition to routines of the same real mode, the system tables and registers should or a more privileged level.

  • Page 116: Virtual 8086 Mode

    Following completion of the interrupt use protected mode addressing for each task. service routine, an IRET instruction restores the The MediaGX processor also permits the use of EFLAGS register (restores VM = 1) and segment paging when operating in V86 mode. Using paging,...

  • Page 117: Floating Point Unit Operations

    The FPU Mode Control Register (MCR) shown in data registers accessed in a stack-like manner, a Table 3-38 is used by the MediaGX processor to control register, and a status register. The CPU specify the operating mode of the FPU. The MCR...

  • Page 118: Table 3-38 Fpu Registers

    10 = 53-bit mantissa 11 = 64-bit mantissa Reserved: Set to 0. RSVD Precision error exception bit FPU Mode Control Register Overflow error exception bit Divide-by-zero exception bit Denormalized-operand error exception bit Invalid-operation exception bit Page 102 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 119: Integrated Functions

    This section details how the integrated functions designs. Performance degradation in traditional and Internal Bus Interface Unit operate and their UMA systems is reduced through the use of Cyrix’s respective registers. Display Compression Technology™ (DCT™). Integer...

  • Page 120: Integrated Functions Programming Interface

    01 = 2KB 10 = 3KB 11 = 4KB MediaGX Base Address: Specifies the physical address for the base (GX_BASE) of the scratchpad RAM, the graphics memory (frame buffer, compression buffer, etc.) and the other memory mapped regis- ters. 00 = Scratchpad RAM, Graphics Subsystem, and memory-mapped configuration registers are disabled.

  • Page 121: Figure 4-2 Mediagx Processor Memory Space

    SMM System Code (Soft VGA and/or PCA/ISA) A0000h (640KB) A0000h (640KB) Conventional Memory Conventional Memory * See BC_DRAM_TOP Table 4-10 on page 114 or MC_GBASE_ADD Table 4-16 on page 122. Figure 4-2 MediaGX Processor Memory Space GXm_db_v2.0 Cyrix Corporation Confidential Page 105...

  • Page 122: Control Registers

    Control Registers and the start of another can cause display prob- lems . The skip count for all supported resolutions is The control registers for the MediaGX processor shown in Table 4-2. use 32KB of the memory map, starting at GX_BASE+8000h (see Figure 4-2).

  • Page 123: L1 Cache Controller

    16KB unified data/instruction L1 cache. It operates in write-back mode. Since the memory controller is The cache of the MediaGX processor provides the also on-board, the L1 cache requires no external ability to redefine 2KB, 3KB, or 4KB of the L1 logic to maintain coherency.

  • Page 124: Table 4-4 L1 Cache Bitblt Registers

    L1_BB1_POINTER Register (R/W) Default Value = None 15:12 RSVD Reserved: Set to 0. BitBLT 1 Pointer Index: The index to the current line of BLT Buffer 1. 11:4 INDEX RSVD Reserved: Set to 0. Page 108 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 125: Table 4-5 Scratchpad Organization

    128 bytes GX_BASE + 0E60h 128 bytes Driver scratchpad GX_BASE + 0B30h 816 bytes GX_BASE + 0930h 1328 bytes BLT Buffer 0 GX_BASE + 0800h 816 bytes GX_BASE + 0400h 1328 bytes BLT Buffer 1 GXm_db_v2.0 Cyrix Corporation Confidential Page 109...

  • Page 126: Display Driver Instructions

    (bits [3:2] in GCR, Index B8h) to enable or disable all of the graphics instructions. The MediaGX processor has four instructions to If the scratchpad size bits are zero, meaning that access processor core registers. Table 4-6 shows none of the cache is defined as scratchpad, then these instructions.

  • Page 127: Cpu_Read/Cpu_Write Instructions

    Both instructions always transfer 32 Instructions bits of data. The MediaGX processor has several internal regis- ters that control the BLT buffer and power manage- These instructions work by initiating a special I/O ment circuitry in the dedicated cache subsystem.

  • Page 128: Internal Bus Interface Unit

    Internal Bus Interface Unit 4.2.2 A20M Support The MediaGX processor’s Internal Bus Interface The MediaGX processor provides an A20M bit in Unit provides control and interface functions to the the BC_XMAP_1 Register (GX_BASE+ 8004h[21]) internal C-Bus (processor core, FPU, graphics...

  • Page 129: Internal Bus Interface Unit Registers

    C0h through DCh. 800Ch-800Fh BC_XMAP_3 00000000h Memory X-Bus Map Register 3 (E and F Region Control) — Contains the region control fields for memory regions in the address range E0h through FCh. GXm_db_v2.0 Cyrix Corporation Confidential Page 113...

  • Page 130: Table 4-10 Internal Bus Interface Unit Registers

    Graphics Enable for A Region: Memory R/W operations for address range A0000h-AFFFFh are directed to the graphics pipeline: 0 = Disable; 1 = Enable. (Used for VGA emulation.) A0 Region: Region control field for address range A0000h-AFFFFh. Note: Refer to Table 4-11 for decode. Page 114 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 131: Table 4-11 Region-Control-Field Bit Definitions

    Read Enable: Read operations to this region of memory are allowed if this bit is set high. If this bit is cleared then read operations in this region are directed to the PCI master. GXm_db_v2.0 Cyrix Corporation Confidential Page 115...

  • Page 132: Memory Controller

    Graphics Pipeline Interface, and the SDRAM Inter- the SDRAM clock. face. A basic block diagram of the memory controller is The MediaGX processor supports LVTTL (low shown in Figure 4-3. voltage TTL) technology. LVTTL technology allows the SDRAM interface of the memory controller to run at frequencies up to 125MHz.

  • Page 133: Memory Array Configuration

    A[12:0] BA[1:0] BA[1:0] MD[63:0] MD[63:0] DQM[7:0] DQM[7:0] RASB# RAS# RAS# CASB# CAS# CAS# WEB# CS2# S0#, S2# CS3# S1#, S3# CKEB CKE0 CKE1 SDCLK2 CK0, CK2 SDCLK3 CK1, CK3 Figure 4-4 Memory Array Configuration GXm_db_v2.0 Cyrix Corporation Confidential Page 117...

  • Page 134: Memory Organizations

    8Mx8 A12-A0 A8-A0 8Mx32 A11-A0 A8-A0 BA1-BA0 8Mx32 A12-A0 A7-A0 BA1-BA0 16Mx4 A11-A0 A9-A0 BA1-BA0 16Mx4 A12-A0 A9-A0 16Mx16 A12-A0 A8-A0 BA1-BA0 16Mx16 A11-A0 A9-A0 BA1-BA0 32Mx8 A12-A0 A9-A0 BA1-BA0 64Mx4 A12-A0 A9-A0,A11 BA1-BA0 Page 118 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 135: Sdram Commands

    000000 CAS Latency: 000 = Reserved 010 = 2 CLK 100 = 4 CLK 110 = 6 CLK 001 = 1 CLK 011 = 3 CLK 101 = 5 CLK 111 = 7 CLK GXm_db_v2.0 Cyrix Corporation Confidential Page 119...
  • Page 136 If the DQM signal is registered low, the corresponding data will be written to memory. If the DQM is driven high, the corresponding data will be ignored, and a write will not be executed to that location. Page 120 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 137: Memory Controller Register Description

    Memory Controller Dirty RAM Access Register — This register is used to access the Dirty RAM. A read/write to this register will access the Dirty RAM at the address specified in the MC_DR_ADD register. GXm_db_v2.0 Cyrix Corporation Confidential Page 121...

  • Page 138: Table 4-16 Memory Controller Registers

    0 = Disable; 1 = Enable. This can be used to compensate for address setup at high frequencies. RFSHTST Test Refresh: This bit, when set high, generates a refresh request. This bit is only used for testing purposes. Page 122 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 139 Read Data Phase: Selects if read data is latched one or two core clock after the rising edge of SDCLK: 0 = 1 core clock; 1 = 2 core clocks. FSTRDMSK Fast Read Mask: Do not allow core reads to bypass the request FIFO: 0 = Disable; 1 = Enable. GXm_db_v2.0 Cyrix Corporation Confidential Page 123...
  • Page 140 010 = 4KB 1xx = 16KB 001 = 2KB 011 = 8KB 111 = DIMM0 not installed When DIMM0 is not installed, program all other DIMM0 fields to 0. RSVD Reserved: Set to 0. Page 124 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 141 010 = 2 CLK 100 = 4 CLK 110 = 6 CLK 001 = 1 CLK 011 = 3 CLK 101 = 5 CLK 111 = 7 CLK RSVD Reserved: Set to 0 or leave unchanged. GXm_db_v2.0 Cyrix Corporation Confidential Page 125...
  • Page 142 MC_DR_ACC register. This field does not auto increment. GX_BASE+841Ch-841Fh MC_DR_ACC (R/W) Default Value = 0000000xh 31:2 RSVD Reserved: Set to 0. Dirty Bit: This bit is read/write accessible. Valid Bit: This bit is read/write accessible. Page 126 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 143: Address Translation

    DIMM and the next two banks ical address starting from A3. would be on the second DIMM, but they would be linear in address space. For an eight bank system GXm_db_v2.0 Cyrix Corporation Confidential Page 127...

  • Page 144: Table 4-17 Auto Loi -- 2 Dimms, Same Size, 1 Dimm Bank

    1K Page Size 2K Page Size 4K Page Size 1K Page Size 2K Page Size 4K Page Size Address 2 Component Banks 4 Component Banks MA12 MA11 MA10 CS0/CS1 CS2/CS3 BA0/BA1 A11/A10 A12/A11 A13/A12 Page 128 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 145: Table 4-19 Non-Auto Loi -- 1 Or 2 Dimms, Different Sizes, 1 Dimm Bank

    1K Page Size 2K Page Size 4K Page Size 1K Page Size 2K Page Size 4K Page Size Address 2 Component Banks 4 Component Banks MA12 MA11 MA10 CS0/CS1 CS2/CS3 BA0/BA1 A11/A10 A12/A11 A13/A12 GXm_db_v2.0 Cyrix Corporation Confidential Page 129...

  • Page 146: Memory Cycles

    Note that the burst length for the READ command supported cycles. is always two. SDCLK RAS# CAS# COL n Figure 4-5 Basic Read Cycle with a CAS Latency of Two Page 130 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 147: Figure 4-6 Basic Write Cycle

    Memory Controller SDRAM Write Cycle Figure 4-6 shows a SDRAM write cycle. The burst length for the WRITE command is 2. SDCLK RAS# CAS# COL n Figure 4-6 Basic Write Cycle GXm_db_v2.0 Cyrix Corporation Confidential Page 131...

  • Page 148: Figure 4-7 Auto Refresh Cycle

    Precharge command must be issued banks. followed by an Activate command. SDCLK RAS# CAS# MA[10] Figure 4-7 Auto Refresh Cycle SDCLK COMMAND tRCD ADDRESS Figure 4-8 Read/Write Command to a New Row Address Page 132 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 149: Sdram Interface Clocking

    The delay for SDCLKIN must be designed so that it lags the SDCLKs at the DRAM by approximately The MediaGX processor drives the SDCLK to the 2ns. The delay should also include the SDCLK SDRAMs; one for each DIMM bank. All the control, transmission line delay.

  • Page 150: Figure 4-10 Effects Of Shftsdclk Programming Bits Example

    DCLK bits setting effects SDCLK. The PCI clock is shift value of two or three could be used so that the input clock to the MediaGX processor. The core SDCLK at the SDRAM is centered around when clock is the internal processor clock that is multi- the control signals change.

  • Page 151: Graphics Pipeline

    Graphics Pipeline Graphics Pipeline 4.4.1 BitBLT/Vector Engine The graphics pipeline of the MediaGX MMX- BLTs are initiated by writing to the GP_BLT_MODE Enhanced processor includes a BitBLT/vector register, which specifies the type of source data ® engine which has been optimized for Microsoft (none, frame buffer, or BLT buffer), the type of the ®...

  • Page 152: Master/Slave Registers

    A second loaded into the MediaGX processor’s registers. For BitBLT or vector operation can then be loaded into solid primitives, the pattern hardware is disabled...

  • Page 153: Figure 4-12 Example Of Monochrome Patterns

    GP_PAT_DATA_1 = 0x115500AA GP_PAT_DATA_2 = 0x441100AA GP_PAT_DATA_3 = 0x115500AA GP_PAT_DATA_0 = 0x80412214 GP_PAT_DATA_1 = 0x08142241 00AA 4411 00AA 1155 00AA 4411 00AA 1155 Figure 4-13 Example of Dither Patterns Figure 4-12 Example of Monochrome Patterns GXm_db_v2.0 Cyrix Corporation Confidential Page 137...

  • Page 154: Source Expansion

    The definition of the ROP value matches that of the ® ® Microsoft API. This allows Windows display drivers to load the raster operation directly into hardware. Table 4-22 illustrates this definition. Page 138 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 155: Graphics Pipeline Register Descriptions

    Note: The registers at GX_BASE+8140, 8144h, 8210h, and 8217h are located in the area designated for the graphics pipeline but are used for VGA emulation purposes. Refer to Table 5-5 on page 200 for these register’s bit formats. GXm_db_v2.0 Cyrix Corporation Confidential Page 139...
  • Page 156 Note: The registers at GX_BASE+8140, 8144h, 8210h, and 8217h are located in the area designated for the graphics pipeline but are used for VGA emulation purposes. Refer to Table 5-5 on page 200 for these register’s bit formats. Page 140 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 157: Table 4-25 Graphics Pipeline Configuration Registers

    8-BPP mode or the 16-BPP mode. Those pixels corresponding to clear bits (0) in the source data are rendered using GP_SRC_COLOR_0 and those pixels corresponding to set bits (1) in the source data are rendered using GP_SRC_COLOR_1. GXm_db_v2.0 Cyrix Corporation Confidential Page 141...
  • Page 158 GP Pattern Data Register 3: The Graphics Pipeline Pattern Data Registers 0 through 3 together contain 128 bits of pat- 31:0 tern data. The GP_PAT_DATA_3 register corresponds to bits [127:96] of the pattern data. Page 142 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 159 11 = Source is a text glyph (use source color expansion). This differs from a monochrome bitmap in that the X position is adjusted by the width of the BLT and the Y position remains the same. GXm_db_v2.0 Cyrix Corporation Confidential Page 143...
  • Page 160 Note that the registers at GX_BASE+8210h and 8214h are located in the area designated for the graphics pipeline but are used for VGA emulation purposes. Refer to Table 5-5 on page 200 for these register’s bit formats. Page 144 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 161: Display Controller

    TFT panels, and flexible output formatting logic. A output on a variety of display devices. The diagram of the display controller subsystem is MediaGX processor can directly connect to an shown in Figure 4-14. active matrix TFT LCD flat panel or to an external RAMDAC for CRT display or both.

  • Page 162: Display Fifo

    FIFO also queues up cursor patterns. second, since the panel could not display changes beyond that rate. Page 146 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 163: Motion Video Acceleration Support

    Display Controller The compression algorithm used in the MediaGX 4.5.4 Hardware Cursor processor commonly achieves compression ratios The display controller contains hardware cursor between 10:1 and 20:1, depending on the nature of logic to allow overlay of the cursor image onto the the display data.

  • Page 164: Display Timing Generator

    Display Timing Generator 4.5.7 Display Modes The display controller features a fully program- The MediaGX processor has two graphics output mable timing generator for generating all timing ports: one primarily designed for interfacing to control signals for the display. The timing control...

  • Page 165: Table 4-26 Tft Panel Display Modes

    Display Controller The MediaGX processor supports both 8- and 16- port. RAMDACS with 8-bit pixel ports will be able to bit RAMDAC configurations, and a direct connec- support 16 BPP displays only up to 800x600 reso- tion to a TFT. For systems that utilize a direct lution.

  • Page 166: Table 4-27 Tft Panel Data Bus Formats

    RAMDAC, RAMDAC, Data 8 BPP 1280x1024x8 BPP, First Second Lower Half Indexed Output First Pixel Transfer Transfer Of Pixel Video* Note: *Refer to the Cx5520 or Cx5530 Data Book for details on YUV ordering. Page 150 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 167: Table 4-29 Crt Display Modes

    256 78.5 78.5 16 BPP 65.0 65.0 64 K colors 75.0 75.0 RGB 5-6-5 78.5 78.5 1280x1024 8 BPP 108.0 108.0 256 colors out of a 54.0 palette of 256 135.0 67.5 GXm_db_v2.0 Cyrix Corporation Confidential Page 151...

  • Page 168: Graphics Memory Map

    Graphics Memory Map 4.5.8.1 DC Memory Organization Registers The MediaGX processor supports a maximum of 4MB of graphics memory and will map it to an The display controller contains a number of regis- address space (see Figure 4-2 on page 105)
  • Page 169 XOR masks for 16 the data in the VGA buffer to an 8 BPP frame buffer pixels in the lower word. DWORDs are arranged that can be displayed by the MediaGX processor’s with the leftmost pixel block being least significant hardware.

  • Page 170: Display Controller Registers

    Display Controller Line Delta — Stores line delta for the graphics display buffers. 8328h-832Bh DC_BUF_SIZE xxxxxxxxh Display Controller Buffer Size — Specifies the number of bytes to transfer for a line of frame buffer data and the size of the compressed line buffer. 832Ch-832Fh Reserved 00000000h Page 154 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 171 Display Controller Cursor Color — Contains the 8-bit indices for the cursor colors. Reserved 8364h-8367h 00000000h 8368h-836Bh DC_BORDER_COLOR xxxxxxxxh Display Controller Border Color — Contains the 8-bit index for the border or overscan color. 836Ch-836Fh Reserved 00000000h GXm_db_v2.0 Cyrix Corporation Confidential Page 155...
  • Page 172 Display Controller Display FIFO Diagnostic — This register is provided to enable testabil- ity of the Display FIFO RAM. DC_CFIFO_DIAG 837Ch-837Fh xxxxxxxxh Display Controller Compression FIFO Diagnostic — This register is provided to enable testability of the Compressed Line Buffer (FIFO) RAM. Page 156 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 173: Table 4-31 Display Controller Configuration And Status Registers

    FIFO Diagnostic Mode: This bit allows testability of the on-chip Display FIFO and Compressed Line Buffer via the diagnostic access registers. A low-to-high transition will reset the Display FIFO’s R/W pointers and the Compressed Line Buffer’s read pointer. 0 = Normal operation; 1 = Enable. GXm_db_v2.0 Cyrix Corporation Confidential Page 157...
  • Page 174 RTPM Real-Time Performance Monitoring: Allows real-time monitoring of a variety of internal MediaGX processor signals by multiplexing the signals onto the CLKWR and DACRS[2:0] pins: 0 = Disable (Normal operation); 1 = Enable.
  • Page 175 Power Sequence Delay: This 3-bit field sets the delay between edges for the power sequencing control DELAY logic. The actual delay is this value multiplied by one frame period (typically 16ms). Note that a value of zero will result in a delay of only one DOTCLK period. GXm_db_v2.0 Cyrix Corporation Confidential Page 159...
  • Page 176 Timing Generator Enable: Allow timing generator to generate the timing control signals for the display. 0 = Disable, the Timing Registers may be reprogrammed, and all circuitry operating on the DOTCLK will be reset. 1 = Enable, no write operations are permitted to the Timing Registers. Page 160 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 177 CRTVSYNC pin, but in order for it to have an effect, the VSYE bit must be set low to dis- able the normal vertical sync. Software should then pulse this bit high and low to clock data into the MediaGX processor. This feature is provided to allow support for the VESA Display Data Channel standard level DDC1.
  • Page 178 0 = The modified codes are sent to the RAMDAC and the external palette should uses the modified mapping. 1 = Bits [8:1] of the palette output register are routed to the RAMDAC data bus. The MediaGX processor internal palette RAM may be loaded with 8-bit VGA indices to translate the modified codes stored in dis- play memory so that the RAMDAC data bus will contain the expected indices.
  • Page 179 0 = 16-bit per pixel display mode is selected. (Bit 1 of OUTPUT_CONFIG will indicate the format of the 16 bit data.) 1 = 8-bit-per-pixel display mode is selected. This is the also the mode used in VGA emulation. GXm_db_v2.0 Cyrix Corporation Confidential Page 163...

  • Page 180: Memory Organization Registers

    • Display Controller Frame Buffer Start Address (DC_FB_ST_OFFSET) Registers - Specifies the offset at which the frame buffer The MediaGX processor utilizes a graphics starts. memory aperture that is up to 4MB in size. The base address of the graphics memory aperture is •...

  • Page 181: Table 4-32 Display Controller Memory Organization Registers

    Video Buffer Start Offset Value: This is the value for the Video Buffer Start Offset. It represents the _OFFSET starting location for Video Buffer. Bits [3:0] should always be programmed as zero so that the start off- set is aligned to a 16 byte boundary. GXm_db_v2.0 Cyrix Corporation Confidential Page 165...
  • Page 182 + 2 so that enough data is transferred to handle any possible alignment. Extra pixel data in the FIFO at the end of a line will automatically be discarded. GX_BASE+832Ch-832Fh Reserved Default Value = 00000000h Page 166 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 183: Timing Registers

    4.5.11 Timing Registers • Display Controller CRT Sync Timing (DC_H_TIMING_3) The MediaGX processor timing registers control - Contains CRT horizontal sync timing informa- the generation of sync, blanking, and active display tion. Note, however, that this register should regions. They provide complete flexibility in inter- also be programmed appropriately for flat facing to both CRT and flat panel displays.

  • Page 184: Table 4-33 Display Controller Timing Registers

    Reserved: These bits are readable and writable but have no effect. Note: A minimum of four character clocks is required for the horizontal blanking portion of a line in order for the timing generator to function correctly. Page 168 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 185 V_ADJUST = (V_PANEL - V_ACTIVE) / 2 If the display is interlaced, the number of active lines should be even, so this value should be an odd number. Note: All values are specified in lines. GXm_db_v2.0 Cyrix Corporation Confidential Page 169...
  • Page 186 2. Note that the internal flat panel vertical sync is latched by the flat panel horizontal sync prior to being output to the panel. Note: All values are specified in lines. Page 170 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 187: Cursor Position Registers

    Note: The value in this register is driven directly off of the DOTCLK, and consequently it is not synchronized with the CPU clock. Software should read this register twice and compare the result to ensure that the value is not transitioning. GXm_db_v2.0 Cyrix Corporation Confidential Page 171...
  • Page 188 Split-Screen Line Compare: This is the line count at which the lower screen begins in a VGA split- screen mode. Note: When the internal line counter hits this value, the frame buffer address is reset to 0. This function is enabled with the SSLC bit in the DC_GENERAL_CFG register. Page 172 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 189: Color Registers

    Reserved: Set to 0. BORDER_CLR Border Color: This is the 8-bit index to the external palette for the border color. It should point to a reserved or static color. GX_BASE+836Ch-836Fh Reserved Default Value = 00000000h GXm_db_v2.0 Cyrix Corporation Confidential Page 173...

  • Page 190: Palette Access Registers

    • Display Controller Display FIFO Diagnostic standard 256 entries for 8 BPP color translation, (DC_DFIFO_DIAG) the MediaGX processor palette has extensions for - This register is provided to enable testability cursor colors and overscan (border) color. of the Display FIFO RAM.
  • Page 191 FIFO and a single read of don't care data should be performed to load data into the output latch. Each subsequent read will contain the appropriate data which was previously written. After each read, the FIFO read pointer will auto- matically increment. GXm_db_v2.0 Cyrix Corporation Confidential Page 175...

  • Page 192: Cx5520/Cx5530 Display Controller Interface

    Figure 4-16 shows the signal connections specifics on signal connections between the two for both types of systems. devices with regards to the display controller. When the MediaGX processor is used in a system with the Cx5520/Cx5530, the need for an external Portable Power...

  • Page 193: Figure 4-17 Video Port Data Transfer (Cx5520/Cx5530)

    VID_DATA[7:0] is advanced when both VID_VAL and VID_RDY are asserted. VID_RDY is driven Data Transfer one clock early to the MediaGX processor while VID_VAL indicates that the MediaGX processor VID_VAL is driven coincident with VID_DATA[7:0]. has placed valid data on VID_DATA[7:0]. VID_RDY...

  • Page 194: Pci Controller

    • Resource or total system lock support encoded special cycle. Type 0 or Type 1 conver- sion will be based on the Bus Bridge number matching the MediaGX processor’s bus number of 00h. Table 4-37 Special-Cycle Code to CONFIG_ADDRESS 30 24...

  • Page 195: Pci Configuration Space Control Registers

    15:11 DEVICE Device: Selects a device on a specified bus. A device value of 00h will select the MediaGX pro- cessor if the bus number is also 00h. DEVICE values of 01h to 15h will be mapped to AD[31:11], so only 21 of the 32 possible devices are supported. A DEVICE value of 00001b will map to AD[11] while a device of 10101b will map to AD[31].

  • Page 196: Pci Configuration Space Registers

    To access the internal PCI configuration registers cant bits must be 00b. of the MediaGX processor, the Configuration Address Register (CONFIG_ADDRESS) must be Table 4-40 summarizes the registers located within written as a DWORD using the format shown in the Configuration Space.

  • Page 197: Table 4-41 Pci Configuration Registers

    VID (RO) Vendor Identification Register (Read Only): The combination of this value and the device ID uniquely identifies any PCI device. The Vendor ID is the ID given to Cyrix Corporation by the PCI SIG. Index 02h-03h Device Identification Register (RO)
  • Page 198 Description Signaled Target Abort: This bit is set whenever the MediaGX processor signals a target abort. A tar- get abort is signaled when an address parity occurs for an address that hits in the MediaGX proces- sor’s address space. This bit can be cleared to 0 by writing a 1 to it.
  • Page 199 PCI Slave Write Buffer Enable: PCI slave write buffers: 0 = Disable; 1 = Enable. CLRE PCI Cache Line Read Enable: Read operations from the PCI into the MediaGX processor: 0 = Single cycle unless a read multiple or memory read line command is used.
  • Page 200 Rotating Arbitration Controls: These bits control the priority under Rotating arbitration. 000 = Fixed arbitration will occur. 111 = Full rotating arbitration will occur. When these bits are set to other values, hybrid arbitration will occur. Page 184 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 201: Pci Cycles

    AD[31:0] contains a valid address and C/BE[3:0]# FRAME# ADDR DATA-2 DATA-3 DATA-1 BUS CMD BE#s C/BE# IRDY# TRDY# DEVSEL# DATA ADDR DATA DATA PHASE PHASE PHASE PHASE BUS TRANSACTION Figure 4-18 Basic Read Operation GXm_db_v2.0 Cyrix Corporation Confidential Page 185...

  • Page 202: Figure 4-19 Basic Write Operation

    Figure 4-19 illustrates a write transac- tion, Revision 2.1. tion. FRAME# DATA-3 DATA-2 DATA-1 ADDR BE#’s-3 BE#’s-2 BUS CMD BE#’s-1 C/BE# IRDY# TRDY# DEVSEL# DATA DATA DATA ADDR PHASE PHASE PHASE PHASE BUS TRANSACTION Figure 4-19 Basic Write Operation Page 186 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 203: Figure 4-20 Basic Arbitration

    It completes the GNT#. Figure 4-20 illustrates basic arbitration. transaction, then deasserts FRAME# and REQ#-b REQ#-a is asserted at clock 1. The PCI MediaGX on clock 6. The MediaGX processor’s PCI arbiter processor arbiter grants access to Agent A by can then grant access to agent A, and does so on asserting GNT#-a on clock 2.
  • Page 204 During the address phase of the Halt Special cycle, C/BE[3:0]# = 0001 and AD[31:0] are driven to random values. During the data phase, C/BE[3:0]# = 1100 indicating bytes 1 and 0 are valid and AD[15:0] = 0001h. Page 188 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 205: Virtual Subsystem Architecture

    Hardware to be virtualized is merely replaced with simple access detection circuitry which asserts the Several functions can be virtualized in a MediaGX processor’s SMI# (System Management Interrupt) processor based design using the VSA environ- pin when hardware accesses are detected. The ment.

  • Page 206: Virtual Vga

    The predefined interface) based operating systems are provided modes are translated into specific VGA control by Cyrix which enable a full featured 2D hardware register setups by the BIOS. The standard modes accelerator to be used instead of the emulated supported by VGA cards are shown in Table 5-1.

  • Page 207: Table 5-1 Standard Vga Modes

    • The CRT controller provides video timing signals and address generation for video refresh. It also provides a text cursor. • The attribute controller contains the video refresh datapath, including text rasterization and palette lookup. GXm_db_v2.0 Cyrix Corporation Confidential Page 191...
  • Page 208 VGA read and write hardware of the are set to zero. In each of these modes, the MediaGX processor. An important axiom of the MapMask enables are logically ANDed into the VGA is that the front end and back end are enables that result from the address.

  • Page 209: Mediagx™ Virtual Vga

    • Write Mode 2: - Bit n of byte b comes from bit b of the host The MediaGX processor provides VGA compati- data; that is, the four LSBs of the host data bility through a mixture of hardware and software.

  • Page 210: Video Refresh

    Within the context of a single scan line, the refresh address increments by one on every character The VGA hardware of the MediaGX processor clock. Before being presented to the frame buffer, does not implement Write Mode 1 directly, but it...

  • Page 211: Mediagx Vga Hardware

    VGA memory. The and mask SMI interrupts in the VGA memory VGA memory on the MediaGX processor is parti- space. tioned from system memory. The MediaGX processor has the following hardware components to assist the VGA emulation software.

  • Page 212: Table 5-2 Vga Configuration Registers Summary

    MediaGX™ Virtual VGA 5.2.3.2 VGA Memory Addresses 5.2.3.4 VGA Control Register SMI generation can be configured to trap VGA The VGA control register (VGACTL) provides memory accesses in one of the following ranges: control for SMI generation through an enable bit for memory address ranges A0000h to BFFFFh.

  • Page 213: Table 5-3 Vga Configuration Registers

    MediaGX™ Virtual VGA Table 5-3 VGA Configuration Registers Description Index B9h VGACTL Register (R/W) Default Value = 00h Reserved: Set to 0. SMI generation for VGA memory range B8000h to BFFFFh: 0 = Disable; 1 = Enable SMI generation for VGA memory range B0000h to B7FFFh: 0 = Disable; 1 = Enable.
  • Page 214 5.2.3.7 VGA Sequencer the VGA access (A0000h to BFFFFh), the base of the VGA memory on the MediaGX processor, and The VGA sequencer is located at the front end of various control bits. The control bits are necessary the graphics pipeline. The purpose of the VGA...

  • Page 215: Vga Video Bios

    MediaGX™ Virtual VGA 5.2.4 VGA Video BIOS 5.2.5 Virtual VGA Register Descriptions The video BIOS supports the VESA BIOS Exten- sions (VBE) Version 1.2 and 2.0, as well as all This section describes the registers contained in standard VGA BIOS calls. It interacts with Virtual the graphics pipeline used for VGA emulation.

  • Page 216: Table 5-5 Virtual Vga Registers

    MediaGX™ Virtual VGA Table 5-5 Virtual VGA Registers Name Description GX_BASE+8210h-8213h GP_VGA_BASE (R/W) Default Value = xxxxxxxxh 31:14 RSVD Reserved: Set to 0. 13:8 VGA_BASE Base Address (Read Only): The VGA base address is added to the graphics memory base to (RO) specify where VGA memory starts.

  • Page 217: Power Management

    The MediaGX processor and Cx5520/Cx5530 I/O The components for APM support are: Companion chip contain the most advanced power • Software CPU Suspend control via the...

  • Page 218: Cpu Suspend Command Registers

    MediaGX processor. When a condition that ends This is called Suspend Modulation. the “Suspend” state exists, SMI# is re-asserted. At this point, if the PLL in the MediaGX processor has Suspend Modulation acts as backup for cases not been stopped, then SUSP# is deasserted.

  • Page 219: 3-Volt Suspend Mode

    SUSP_3V pin, starting the system clocks. The clock synthesizer or buffer chip so that the clocks Cx5520/Cx5530 holds SUSP# active for a pre- to the MediaGX processor (SYSCLK), the programmed period that varies from 0 to 16 ms, Cx5520/Cx5530 (PCI_CLK), and other system which allows the clocks to settle.

  • Page 220: Suspend Mode And Bus Cycles

    The CPU also allows PCI accesses during a SUSP#-initiated Suspend mode (see Figure 6-1). The MediaGX processor enters the Suspend mode If the CPU is in the middle of a PCI access when in response to SUSP# input assertion only when SUSP# is asserted, the assertion of SUSPA# will certain conditions are met.

  • Page 221: Initiating Suspend With Halt

    SYSCLKS from the detection until the PCI access is completed. of an active interrupt. However, the deactivation of HALT SYSCLK FRAME# C/BE[3:0]# AD[15:0] IRDY# INTR, NMI, SMI# SUSPA# Figure 6-2 HALT-Initiated Suspend Mode GXm_db_v2.0 Cyrix Corporation Confidential Page 205...

  • Page 222: Responding To A Pci Access During Suspend Mode

    Suspend Mode and Bus Cycles 6.5.3 Responding to a PCI Access asserted when the PCI access is completed, the MediaGX processor will assert SUSPA# and return During Suspend Mode to a SUSP#-initiated Suspend mode. If it was a The MediaGX processor can temporarily exit HALT-initiated Suspend mode and no active inter- Suspend mode to handle PCI accesses.

  • Page 223: Stopping The Input Clock

    Stopping the Input Clock The CPU remains suspended until SYSCLK is restarted and the Suspend mode is exited as Because the MediaGX processor is a static device, described earlier. While SYSCLK is stopped, the the input clock (SYSCLK) can be stopped and processor can no longer sample and respond to restarted without any loss of internal CPU data.

  • Page 224: Mediagx Processor Serial Bus

    “PM Serial Packet Register” on the SERIALP mation regarding the MediaGX processor produc- output pin to the PSERIAL input pin of the tivity. If the MediaGX processor is determined to be Cx5520/Cx5530. The MediaGX processor holds relatively inactive, the MediaGX processor power...

  • Page 225: Power Management Registers

    111 for more information regarding these instruc- memory mapped (GX_BASE+8500h-8FFFh) in the tions. address space of the MediaGX processor and are Table 6-1 summarizes the above mentioned regis- described in the following sections. Refer to ters. Tables 6-2 and 6-3 give these register’s bit Section 4.1.2 “Control Registers”...

  • Page 226: Table 6-2 Power Management Control And Status Registers

    1 = 3-Volt Suspend Mode. All internal clocks are stopped. Note: When this register is set high and the Suspend input pin (SUSP#) is asserted, the MediaGX processor stops all it’s internal clocks, and asserts the Suspend Acknowledge output pin (SUSPA#). Once SUSPA# is asserted the MediaGX processor’s SYSCLK input can be stopped.
  • Page 227 PM_CNTRL_TEN. Note: The MediaGX processor transmits the contents of the serial packet only when a bit in the packet register is set and the interval counter has elapsed. The Cx5520/Cx5530 decodes the serial packet after each transmission. Once a bit in the packet is set, it will remain set until the completion of the next packet transmission.

  • Page 228: Table 6-3 Power Management Programmable Address Region Registers

    Write Enable — Compare memory write cycles with BASE_ADDR and ADR_MASK: 0 = Disable; 1 = Enable. Read Enable — Compare memory read cycles with BASE_ADDR and ADR_MASK: 0 = Disable; 1 = Enable Page 212 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 229: Electrical Specifications

    7.2.2 Power Sequencing the Core and I/O Voltages Table 7-1 Part Numbers With two voltages connected to the MediaGX processor, it is important that the voltages come up Bus Speed (MHz) Speed & Multiplier Part Number in the correct order. V...

  • Page 230: Pull-Up And Pull-Down Resistors

    SUSP* Pull-up FRAME# Pull-up IRDY# Pull-up TRDY# Pull-up STOP# Pull-up LOCK# Pull-up DEVSEL# Pull-up PERR# Pull-up SERR# Pull-up REQ[2:0]# Pull-up TCLK Pull-up Pull-up Pull-up TEST Pull-down Note: *SUSP# is pulled up when not active. Page 214 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 231: Absolute Maximum Ratings

    Table 7-3 lists absolute maximum ratings for the are stress ratings only and do not imply that opera- MediaGX processor. Stresses beyond the listed tion under any conditions other than those listed ratings may cause permanent damage to the device.

  • Page 232: Recommended Operating Conditions

    Recommended Operating Conditions Recommended Operating Conditions Table 7-4 lists the recommended operating conditions for the MediaGX processor. Table 7-4 Recommended Operating Conditions Symbol Parameter Units Notes Operating Case Temperature °C For Desktop Applications Operating Case Temperature °C For Notebook Applications Supply Voltage (2.9V nominal)

  • Page 233: Dc Characteristics

    (static I = 0 mA). 4. All inputs are at 0.2 V or V – 0.2 (CMOS levels). All inputs except clock are held static and all outputs are unloaded (static I = 0 mA). GXm_db_v2.0 Cyrix Corporation Confidential Page 217...

  • Page 234: Ac Characteristics

    Legend: A = Maximum Output Delay Specification B = Minimum Output Delay Specification C = Minimum Input Setup Specification D = Minimum Input Hold Specification Figure 7-1 Drive Level and Measurement Points for Switching Characteristics Page 218 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 235: Figure 7-2 Sysclk Timing And Measurement Points

    Note: SDCLK timings (t9-t13) assume an SDCLK that is a "divide by 3" from the internal core clock. Hence: 200MHz (6x) = 66.7MHz SDCLK 233MHz (7x) = 77.7MHz SDCLK 266MHz (8x) = 88.7MHz SDCLK 300MHz (9x) = 100MHz SDCLK IH (Min) 1.5V IL (Max) SYSCLK Figure 7-2 SYSCLK Timing and Measurement Points GXm_db_v2.0 Cyrix Corporation Confidential Page 219...

  • Page 236: Figure 7-3 Dclk Timing And Measurement Points

    Setup Time for SMI#, SUSP#, FLT# Hold Time for SMI#, SUSP#, FLT# Valid Delay for IRQ13, SUSPA# Valid Delay for SERIALP Note: The system signals may be asynchronous. The setup/hold times are required for determining static behavior. Page 220 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 237: Figure 7-5 Output Timing

    GNT# and REQ# are point-to-point signals. All other PCI interface signals are bused. Refer to Chapter 4 of PCI Local Bus Specification, Revision 2.1, for more detailed information. SYSCLK VAL1,2 OUTPUT TRISTATE OUTPUT Figure 7-5 Output Timing SYSCLK SU1,2 INPUT Figure 7-6 Input Timing GXm_db_v2.0 Cyrix Corporation Confidential Page 221...

  • Page 238: Figure 7-7 Output Valid Timing

    Note that SHFTSDCLK field = GX_BASE+8404h[5:3], see page 123. Equation Example: A 200MHz MediaGX processor running a 66MHz SDRAM bus, with a shift value of 2: t1 Min = –1.5 + (2 * (5 ÷ 2)) = 3.5 ns t1 Max = –1.0 + (2 * (5 ÷ 2)) = 4.0 ns...

  • Page 239: Figure 7-9 Graphics Port Timing

    VID_RDY Hold to VID_CLK Rising Edge VID_VAL, VID_DATA[7:0] Valid Delay from VID_CLK Rising Edge DCLK Period DCLK Rise/Fall Time tcyc DCLK Duty Cycle PCLK PIXEL[17:0], CRT_HSYNC, CRT_VSYNC, FP_HSYNC, FP_VSYNC, ENA_DISP Figure 7-9 Graphics Port Timing GXm_db_v2.0 Cyrix Corporation Confidential Page 223...

  • Page 240: Figure 7-10 Video Port Timing

    AC Characteristics VID_CLK VID_VAL VID_RDY VID_DATA[7:0] Figure 7-10 Video Port Timing DCLK Figure 7-11 DCLK Timing Page 224 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 241: Figure 7-12 Tck Timing And Measurement Points

    TDO Float Delay Non-test Outputs Float Delay TDI, TMS Setup Time Non-test Inputs Setup Time TDI, TMS Hold Time Non-test Inputs Hold Time IH(Min) 1.5 V IL(Max) Figure 7-12 TCK Timing and Measurement Points GXm_db_v2.0 Cyrix Corporation Confidential Page 225...

  • Page 242: Figure 7-13 Jtag Test Timings

    AC Characteristics 1.5 V TDI, Output Signals Input Signals Figure 7-13 JTAG Test Timings Page 226 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 243: Package Specifications

    (°C/W) θ = Junction-to-ambient thermal resistance Thermal Characteristics (°C/W). The MediaGX processor is designed to operate θ = Case-to-ambient thermal resistance when the case temperature at the top center of the (°C/W). package is between 0°C and 70 or 85°C. The...

  • Page 244: Table 8-1 Case To Ambient Thermal Resistance Examples For 70°C Product

    35°C 40°C Case Temperature = 85°C GM200 8.95 7.26 6.70 6.15 5.59 5.03 GM233 9.87 6.59 6.08 5.57 5.07 4.56 GM266 10.70 6.08 5.61 5.14 4.67 4.21 GM300 11.27 5.77 5.32 4.88 4.44 3.99 Page 228 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 245: Mechanical Package Outlines

    1.242 1.258 32.80 35.20 1.291 1.386 1.12 1.42 0.044 0.056 0.35 0.014 A01 Index Chamfer 1.42 1.82 0.056 0.072 1.5 mm on a side 45 Degree Angle Figure 8-1 352-Terminal BGA Mechanical Package Outline GXm_db_v2.0 Cyrix Corporation Confidential Page 229...

  • Page 246: Figure 8-2 320-Pin Spga Mechanical Package Outline

    .060" filled circle to form donut 2.41 2.67 0.095 0.105 1.14 1.40 0.045 0.055 0.127 0.005 Diag Diag 2.97 3.38 0.117 0.133 1.65 2.16 0.065 0.085 Figure 8-2 320-Pin SPGA Mechanical Package Outline Page 230 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 247: Table 8-3 Mechanical Package Outline Legend

    BGA: Solder ball pitch SPGA: Linear spacing between true pin position centerlines Diagonal spacing between true pin position centerlines Flatness Distance from seating plane to tip of pin Length from outer pin/ball center to edge of laminate GXm_db_v2.0 Cyrix Corporation Confidential Page 231...
  • Page 248 Mechanical Package Outlines Page 232 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 249: Instruction Set

    • MMX™ Instruction Set - listed in Table 9-31 on register components, add one clock to the page 267 clock count shown. • Cyrix Extended MMX Instruction Set - listed in 7. All clock counts assume aligned 32-bit Table 9-33 on page 273 memory/IO operands.

  • Page 250: General Instruction Set Format

    An instruction can be as short as one byte and as long Depending on the instruction, the MediaGX as 15 bytes. If there are more than 15 bytes in the processor core instructions follow the general instruction, a general protection fault (error code 0) instruction format shown in Table 9-1.

  • Page 251: Prefix (Optional)

    32-Bit Data a register or memory operand. The reg field may Field Operations Operations appear in the second opcode byte or in the mod r/m byte. 8 bits 8 bits 16 bits 32 bits GXm_db_v2.0 Cyrix Corporation Confidential Page 235...

  • Page 252: Table 9-5 D Field Encoding

    Register Type Base Register Control Register Control Register Control Register Control Register Debug Register Debug Register Debug Register Debug Register Debug Register Debug Register Test Register Test Register Test Register Test Register Test Register Page 236 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 253: Mod And R/M Byte (Memory Addressing)

    SS:[BP+DI+d16] DS:[EBX+d32] DS:[SI+d16] s-i-b is present (See Table 9-15) DS:[DI+d16] SS:[EBP+d32] SS:[BP+d16] DS:[ESI+d32] DS:[BX+d16] DS:[EDI+d32] See Table 9-8. See Table 9-8 Note: Note: d8 refers to 8-bit displacement, and d16 refers to 16-bit displacement. GXm_db_v2.0 Cyrix Corporation Confidential Page 237...

  • Page 254: Reg Field

    The sreg3 field (Table 9-12) is 3-bit field that is sreg2 Field Segment Register Selected similar to the sreg2 field, but allows use of the FS and GS segment registers. Table 9-12 sreg3 Field Encoding sreg3 Field Segment Register Selected Undefined Undefined Page 238 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 255: S-I-B Byte (Scale, Indexing, Base)

    SS:[ESP+(scaled index)+d8] SS:[EBP+(scaled index)+d8] Table 9-14 index Field Encoding DS:[ESI+(scaled index)+d8] Index Field Index Register DS:[EDI+(scaled index)+d8] DS:[EAX+(scaled index)+d32] DS:[ECX+(scaled index)+d32] DS:[EDX+(scaled index)+d32] none DS:[EBX+(scaled index)+d32] SS:[ESP+(scaled index)+d32] SS:[EBP+(scaled index)+d32] DS:[ESI+(scaled index)+d32] DS:[EDI+(scaled index)+d32] GXm_db_v2.0 Cyrix Corporation Confidential Page 239...

  • Page 256: Cpuid Instruction

    CPUID Returned Data in EAX, EBX, Type Register ECX, EDX Registers vendor, family, model, stepping, features and also provides cache information. The MediaGX with Standard 0000 0000h Maximum standard levels, CPU vendor string MMX supports both the standard and Cyrix extended CPUID levels.

  • Page 257: Standard Cpuid Levels

    Attempting to execute an unavailable feature Note: The register column is intentionally out of order. can cause exceptions and unexpected behavior. For example, software must check bit 4 before attempting to use the Time Stamp Counter instruc- tion. GXm_db_v2.0 Cyrix Corporation Confidential Page 241...

  • Page 258: Table 9-19 Edx Cpuid Data Returned When Eax = 1

    Standard function 02h (EAX = 02h) of the CPUID Contents* Feature Flag instruction returns information that is specific to the Cyrix family of processors. Information about the EDX[0] FPU On-Chip TLB is returned in EAX as shown in Table 9-20.

  • Page 259: Extended Cpuid Levels

    EDX[3] Page Size Extension 8000 0005h Maximum Extended CPUID (4MB) Level (six levels) EDX[4] Time Stamp Counter Reserved EDX[5] Cyrix Model-Specific Reg- Reserved isters (via RDMSR / Reserved WRMSR Instructions) EDX[6] Reserved EDX[7] Machine Check Exception 9.2.2.2 CPUID Instruction with...

  • Page 260: Table 9-24 Official Cpu Name

    80h L1 cache is 16 KBytes, 4-way set associated, and has 16 bytes per line. Name 2 Name 6 Name 10 Reserved Name 3 Name 7 Name 11 Name 4 Name 8 Name 12 Page 244 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 261: Processor Core Instruction Set

    Processor Core Instruction Set Processor Core Instruction Set Table 9-26 Processor Core Instruction Set Table Legend The instruction set for the MediaGX processor core is summarized in Table 9-27. The table uses Symbol or several symbols and abbreviations that are...

  • Page 262: Table 9-27 Processor Core Instruction Set Summary

    BSR Scan Bit Reverse Register, Register/Memory 0F BD [mod reg r/m] 4/11+n 4/11+n BSWAP Byte Swap 0F C[1 reg] BT Test Bit Register/Memory, Immediate 0F BA [mod 100 r/m]# Register/Memory, Register 0F A3 [mod reg r/m] Page 246 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 263 0F 47 [mod reg r/m] CMOVBE/CMOVNA Move if Below or Equal/Not Above Register, Register/Memory 0F 46 [mod reg r/m] CMOVAE/CMOVNB/CMOVNC Move if Above or Equal/Not Below/Not Carry Register, Register/Memory 0F 43 [mod reg r/m] GXm_db_v2.0 Cyrix Corporation Confidential Page 247...
  • Page 264 0F B [000w] [mod reg r/m] CMPXCHG8B Compare and Exchange 8 Bytes 0F C7 [mod 001 r/m] CPUID CPU Identification 0F A2 CPU_READ Read Special CPU Register 0F 3C CPU_WRITE Write Special CPU Register 0F 3D Page 248 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 265 E [010w] # 8/22 Variable Port E [110w] 8/22 INS Input String from I/O Port 6 [110w] 11/25 INC Increment by 1 Register/Memory F [111w] [mod 000 r/m] Register (short form) 4 [0 reg] GXm_db_v2.0 Cyrix Corporation Confidential Page 249...
  • Page 266 0F 84 +++ JL/JNGE Jump on Less/Not Greater or Equal 8-bit Displacement 7C + Full Displacement 0F 8C +++ JLE/JNG Jump on Less or Equal/Not Greater 8-bit Displacement 7E + Full Displacement 0F 8E +++ Page 250 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 267 7B + Full Displacement 0F 8B +++ JNS Jump on Not Sign 8-bit Displacement 79 + Full Displacement 0F 89 +++ JO Jump on Overflow 8-bit Displacement 70 + Full Displacement 0F 80 +++ GXm_db_v2.0 Cyrix Corporation Confidential Page 251...
  • Page 268 0F B2 [mod reg r/m] h,i,j LTR Load Task Register From Register/Memory 0F 00 [mod 011 r/m] g,h,j,l LEAVE Leave Current Stack Frame LOOP Offset Loop/No Loop E2 + LOOPNZ/LOOPNE Offset E0 + LOOPZ/LOOPE Offset E1 + Page 252 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 269 F [011w] [mod 100 r/m] u u x Multiplier: Byte Word Doubleword NEG Negate Integer F [011w] [mod 011 r/m] NOP No Operation NOT Boolean Complement F [011w] [mod 010 r/m] OIO Official Invalid Opcode 0F FF 8-125 GXm_db_v2.0 Cyrix Corporation Confidential Page 253...
  • Page 270 PUSHF Push FLAGS Register RCL Rotate Through Carry Left Register/Memory by 1 D [000w] [mod 010 r/m] Register/Memory by CL D [001w] [mod 010 r/m] Register/Memory by Immediate C [000w] [mod 010 r/m] # Page 254 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 271 C[000w] [mod 001 r/m] # RSDC Restore Segment Register and Descripto r 0F 79 [mod sreg3 r/m] RSLDT Restore LDTR and Descriptor 0F 7B [mod 000 r/m] RSTS Restore TSR and Descriptor 0F 7D [mod 000 r/m] GXm_db_v2.0 Cyrix Corporation Confidential Page 255...
  • Page 272 To Register/Memory 0F 9D [mod 000 r/m] SETNLE/SETG Set Byte on Not Less or Equal/Greater To Register/Memory 0F 9F [mod 000 r/m] SETNO Set Byte on Not Overflow To Register/Memory 0F 91 [mod 000 r/m] Page 256 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 273 Register/Memory by Immediate 0F AC [mod reg r/m] # Register/Memory by CL 0F AD [mod reg r/m] SMINT Software SMM Entry 0F 38 STC Set Carry Flag STD Set Direction Flag STI Set Interrupt Flag GXm_db_v2.0 Cyrix Corporation Confidential Page 257...
  • Page 274 3 [00dw] [11 reg r/m] Register to Memory 3 [000w] [mod reg r/m] Memory to Register 3 [001w] [mod reg r/m] Immediate to Register/Memory 8 [00sw] [mod 110 r/m] ### Immediate to Accumulator (short form) 3 [010w] ### Page 258 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 275 Notes e through g apply to Real Address Mode and Protect- ed Virtual Address Mode: Note s applies to Cyrix-specific SMM instructions: e. An exception may occur, depending on the value of the s. All memory accesses to SMM space are non-cacheable. An operand.

  • Page 276: Fpu Instruction Set

    Env Regs Status, Mode Control and Tag Registers, recovery. Instruction Pointer and Operand Pointer The instruction set for the FPU is summarized in Table 9-29. The table uses abbreviations that are described Table 9-28. Page 260 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 277: Table 9-29 Fpu Instruction Set Summary

    D8 [mod 011 r/m] CC set by TOS - M.SR; then pop TOS FCOMPP Floating Point Compare, Pop DE D9 CC set by TOS - ST(1); then pop TOS and Two Stack Elements ST(1) GXm_db_v2.0 Cyrix Corporation Confidential Page 261...
  • Page 278 FFREE Free Floating Point Register DD [1100 0 n] TAG(n) <--- Empty FINCSTP Increment Stack Pointer D9 F7 Increment top-of-stack pointer FINIT Initialize FPU (9B)DB E3 Wait, then initialize FNINIT Initialize FPU DB E3 Initialize Page 262 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 279 DD [mod 110 r/m] Save state 55 - 65 TOS <--- TOS × 2 (ST(1)) FSCALE Floating Multiply by 2 D9 FD 7 - 14 FSIN Function Evaluation: Sin(x) D9 FE TOS <--- SIN(TOS) 76 - 140 GXm_db_v2.0 Cyrix Corporation Confidential Page 263...
  • Page 280 ST(n) <--- TOS - ST(n) 4 - 9 64-bit Real DC [mod 101 r/m] TOS <--- M.DR - TOS 4 - 9 32-bit Real D8 [mod 101 r/m] TOS <--- M.SR - TOS 4 - 9 Page 264 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 281 FYL2X is called. A pop from the stack increments the top of stack pointer. 5. The following opcodes are reserved by Cyrix: A push to the stack decrements the top of stack pointer. D9D7, D9E2, D9E7, DDFC, DED8, DEDA, DEDC, DEDD, Notes: DEDE, DFFC.

  • Page 282: Mmx™ Instruction Set

    Pack two double words from source and two double words from destination into four words in destination register. packwb Pack four words from source and four words from destination into eight bytes in destination register. Page 266 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 283: Table 9-31 Mmx Instruction Set Summary

    0FDC [11 mm1 mm2] MMX reg 1 [byte] <--sat-- MMX reg 1 [byte] + MMX reg 2 [byte] Memory to Register 0FDC [mod mm r/m] MMX reg [byte] <--sat-- memory [byte] + MMX reg [byte] GXm_db_v2.0 Cyrix Corporation Confidential Page 267...
  • Page 284 MMX reg 1 [dword]<--0000 0000h--if MMX reg 1 [dword]NOT > MMX reg 2 [dword] Memory with MMX Register 0F66 [mod mm r/m] MMX reg [dword] <--FFFF FFFFh-- if memory[dword] > MMX reg [dword] MMX reg [dword] <--0000 0000h-- if memory[dword] NOT > MMX reg [dword] Page 268 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 285 0FE2 [mod mm r/m] MMX reg [dword] <--arith shift right, shifting in zeroes by memory[dword]-- MMX Register by Immediate 0F72 [11 100 mm] # MMX reg [dword] <--arith shift right, shifting in zeroes by [im byte]-- GXm_db_v2.0 Cyrix Corporation Confidential Page 269...
  • Page 286 0FD9 [11 mm1 mm2] MMX reg 1 [word] <--sat-- MMX reg 1 [word] subtract MMX reg 2 [word] Memory to MMX Register 0FD9 [11 mm reg] MMX reg [word] <--sat-- MMX reg [word] subtract memory [word] Page 270 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 287 0FEF [11 mm1 mm2] MMX reg 1 [qword] <--logic exclusive OR-- MMX reg 1 [qword], MMX reg 2 [qword] Memory to MMX Register 0FEF [11 mm reg] MMX reg [qword] <--logic exclusive OR-- memory[qword], MMX reg [qword] GXm_db_v2.0 Cyrix Corporation Confidential Page 271...

  • Page 288: Cyrix Extended Mmx™ Instruction Set

    Configuration control register CCR7(0) at location mm1, mm2 MMX Register 1, MMX Register 2 EBh must be set to allow the execution of the Cyrix mod r/m Mod and r/m byte encoding (page 6-6 of Extended MMX instructions.

  • Page 289: Table 9-33 Cyrix Extended Mmx Instruction Set Summary

    Cyrix Extended MMX™ Instruction Set Table 9-33 Cyrix Extended MMX Instruction Set Summary MMX Instructions Opcode Operation and Clock Count PADDSIW Packed Add Signed Word with Saturation Using Implied Destination MMX Register plus MMX Register to Implied Register 0F51 [11 mm1 mm2] Sum signed packed word from MMX register/memory --->...
  • Page 290 Cyrix Extended MMX™ Instruction Set Page 274 Cyrix Corporation Confidential GXm_db_v2.0...

  • Page 291: Appendix A Support Documentation

    MediaGX™ MMX™-Enhanced Processor Integrated x86 Solution with MMX™ Support Appendix A Support Documentation Order Information Cyrix National Part Core Temperature Part Number Number (NSID) Frequency (MHz) (Degree C) Package GM200P 30040-23 GM200P-85 30041-23 GM200B-85 30141-23 GM233P 30050-33 GM233P-85 30054-33 GM233B-85...

  • Page 292: Data Book Revision History

    • Corrected all SMI_LOCK and MAPEN index/register cross-references in Table 3-11 "Configu- ration Registers". • Changed GXm references in Table 3-11 "Configuration Registers" to MediaGX MMX- Enhanced processor. • In Table 3-16 "TR5-TR3 Bit Definitions", TR4 Register was not showing RSVD bits [2:0].
  • Page 293 • New 352 BGA - modified dimensions and callouts in Figure 8-1 "352-Terminal BGA Mechan- Specifications ical Package Outline". Now also includes coplanarity value. • Removed legend from inside Figure 8-2 "320-Pin SPGA Mechanical Package Outline" and created new table - Table 8-3 "Mechanical Package Outline Legend". GXm_db_v2.0 Cyrix Corporation Confidential Page 277...
  • Page 294 Page 278 Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 295 Memory Addressing Modes CCR4 Configuration Control Register 4 Index E8h Offset Mechanism CCR7 Page Frame Offset (PFO) Cyrix Extended MMX Instructions Enable Page Table Entry (PTE) NMI Enabl Paging Mechanism CCR7 Configuration Control Register 7 Index EBh Translation Look-Aside Buffer...
  • Page 296 TFT Panel Display Modes EBP register VESA-compatible EFLAGS Register VGA Display Support Alignment Check Enable (AM) Display Controller Block Diagram Auxiliary Carry Flag Display Controller Registers Carry Flag Configuration and Status Registers CPUID instruction DC_BORDER_COLOR (8368h-836Bh) Direction Flag (DF) Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 297 GP_DST_XCOOR Fields - mod and r/m GP_DST_YCOOR Fields - sreg3 GP_INIT_ERROR Fields - ss GP_PAT_COLOR_0 register floating point error GP_PAT_COLOR_1 (GX_BASE+8112h) GP_PAT_COLOR_A (8110h) Mode Control Register GP_PAT_COLOR_B (8114h) Register Set GP_PAT_DATA (8120h-812Fh) Status Register GP_RASTER_MODE (8200h-8203h) GXm_db_v2.0 Cyrix Corporation Confidential...
  • Page 298 Bit Test Instructions Local Descriptor Table Register (LDTR) Exchange Instructions LOCK One-operand Arithmetic and Logical Lock Prefix Two-operand Arithmetic and Logical Low Order Interleaving Instuction Prefix Summary Integrated Functions Integrated Functions Programming Interface MediaGX™ Virtual VGA Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 299 PCI Configuration Registers 0CF8h-0CFBh MC_BANK_CFG (8408h-840Bh) PCI Controller MC_DR_ACC (841Ch-841Fh) CONFIG_ADDRESS MC_DR_ADD (8418h-841Bh) Configuration Cycles MC_GBASE_ADD (8414h-8417h) PCI Arbiter MC_MEM_CNTRL1 (8400h-8403h) Space Control Registers MC_MEM_CNTRL2 (8404h-8407h) Special Cycles MC_SYNC_TIM1 (840Ch-840Fh) X-Bus PCI Master Memory Data Bus GXm_db_v2.0 Cyrix Corporation Confidential...
  • Page 300 – Power Planes Power, Ground, No Connect Ground (VSS) Scratchpad Power, Ground, No Connect Signals 2KB configurations Ground (VSS) 3KB configurations No Connect (NC) SMM information Power Connect (VCC2) Scratchpad RAM Power Connect (VCC3) SDRAM Clocks Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 301 Shutdown and Halt System Clock – Signal Definitions System Management Interrupt Signal Descriptions System Management Interrupt (SMI#) Cyrix Internal Test and Measurement Signals System Register Set – Memory Controller Interface Signals System Register Sets – PCI Interface Signals Cache Test Registers...
  • Page 302 VGA Write/Read Path Video Data Bus VID_CLK Video Interface Signals CRT Horizontal Sync CRT Vertical Sync Display Enable Dotclock Flat Panel Horizontal Sync Flat Panel Vertical Sync Graphics Pixel Data Bus Pixel Port Clock Video Clock Cyrix Corporation Confidential GXm_db_v2.0...
  • Page 304 Richardson, TX 75085-0118 www.cyrix.com MediaGX™ MMX™-Enhanced Processor Data Book, Rev 2.0, Oct. 1998 © Cyrix Corporation. Cyrix is a registered trademark of Cyrix Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders. Cyrix is a wholly-owned subsidiary of National Semiconductor®...

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