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CY7C68013
Cypress CY7C68013 Manuals
Manuals and User Guides for Cypress CY7C68013. We have
1
Cypress CY7C68013 manual available for free PDF download: Manual
Cypress CY7C68013 Manual (48 pages)
EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller
Brand:
Cypress
| Category:
Controller
| Size: 0 MB
Table of Contents
Table of Contents
2
1 Ez-Usb® Fx2™ Features
5
Figure 1-1. Block Diagram
5
2 Applications
6
3 Functional Overview
6
USB Signaling Speed
6
8051 Microprocessor
6
I 2 C-Compatible Bus
7
Buses
7
USB Boot Methods
8
Renumeration
8
Interrupt System
8
Table 3-1. Default ID Values for FX2
8
Table 3-2. INT2 USB Interrupts
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Reset and Wakeup
10
Program/Data RAM
10
Table 3-3. Individual FIFO/GPIF Interrupt Sources
10
Figure 3-1. Internal Code Memory, EA = 0
11
Figure 3-2. External Code Memory, EA = 1
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Register Addresses
13
Endpoint RAM
13
Figure 3-3. Endpoint Configuration
14
Table 3-4. Default Full-Speed Alternate Settings [1, 2]
14
External FIFO Interface
15
Gpif
15
Table 3-5. Default High-Speed Alternate Settings [1, 2]
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USB Uploads and Downloads
16
Autopointer Access
16
I 2 C-Compatible Controller
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4 Pin Assignments
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Table 3-6. Strap Boot EEPROM Address Lines to These Values
17
Figure 4-1. Signals
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Figure 4-2. CY7C68013 128-Pin TQFP Pin Assignment
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Figure 4-3. CY7C68013 100-Pin TQFP Pin Assignment
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Figure 4-4. CY7C68013 56-Pin SSOP Pin Assignment
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CY7C68013 Pin Descriptions
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Table 4-1. FX2 Pin Descriptions [5]
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5 Register Summary
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Table 5-1. FX2 Register Summary
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6 Absolute Maximum Ratings
35
7 Operating Conditions
35
600 DC Characteristics
35
Table 8-1. DC Characteristics
35
Table 8-2. USB Transceiver
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9 Ac Electrical Characteristics
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USB Transceiver
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Program Memory Read
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Figure 9-1. Program Memory Read Timing Diagram
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Table 9-1. Program Memory Read Parameters
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Data Memory Read
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Figure 9-2. Data Memory Read Timing Diagram
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Table 9-2. Data Memory Read Parameters
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Data Memory Write
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Figure 9-3. Data Memory Write Timing Diagram
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Table 9-3. Data Memory Write Parameters
38
GPIF Synchronous Signals
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Figure 9-4. GPIF Synchronous Signals Timing Diagram [12]
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Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK [13, 14]
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Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced
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Slave FIFO Synchronous Read
40
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram [12]
40
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
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Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
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Slave FIFO Asynchronous Read
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Slave FIFO Synchronous Write
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Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram [12]
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Figure 9-7. Slave FIFO Synchronous Write Timing Diagram [12]
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Table 9-8. Slave FIFO Asynchronous Read Parameters [15]
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Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
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Slave FIFO Asynchronous Write
42
Slave FIFO Synchronous Packet End Strobe
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Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram [12]
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Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram [12]
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Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK
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Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
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Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters
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Slave FIFO Asynchronous Packet End Strobe
43
Slave FIFO Output Enable
43
Slave FIFO Address to Flags/Data
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Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram [12]
43
Figure 9-11. Slave FIFO Output Enable Timing Diagram [12]
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Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram [12]
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Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters
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Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters [15]
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Table 9-15. Slave FIFO Output Enable Parameters
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Slave FIFO Synchronous Address
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Slave FIFO Asynchronous Address
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10 Ordering Information
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Figure 9-13. Slave FIFO Synchronous Address Timing Diagram
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Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram [12]
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Table 9-16. Slave FIFO Address to Flags/Data Parameters
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Table 9-17. Slave FIFO Synchronous Address Parameters [14]
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Table 9-18. Slave FIFO Asynchronous Address Parameters [15]
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Table 10-1. Ordering Information
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11 Package Diagrams
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Figure 11-1. 56-Lead Shrunk Small Outline Package O56
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Figure 11-2. 100-Pin Thin Plastic Quad Flatpack (14 X 20 X 1.4 MM) A101
46
Figure 11-3. 128-Lead Thin Plastic Quad Flatpack (14 X 20 X 1.4 MM) A128
47
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