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Coreco PCVisionplus Manuals
Manuals and User Guides for Coreco PCVisionplus. We have
1
Coreco PCVisionplus manual available for free PDF download: Hardware Reference Manual
Coreco PCVisionplus Hardware Reference Manual (206 pages)
Brand:
Coreco
| Category:
PCI Card
| Size: 3 MB
Table of Contents
Table of Contents
16
Figure 1-1. Line and Frame Timing
22
Table 1-1. Variable Scan Timing Parameters
22
Figure 1-2. Set up and Hold Timing
22
Figure 1-3. Set up and Hold Timing, Clock Inverted
23
Figure 1-4. Pcvisionplus Connectors and Jumper
26
Figure 2-1. Pcvisionplus Block Diagram
29
Figure 2-2. Non-Interlaced Acquire
32
Figure 2-3. Interlaced Acquire
33
Figure 2-4. Triggered Acquire
33
Figure 2-5. Bus Master Zoom, 8-Bit Mode
36
Figure 2-6. Bus Master Zoom 2, 12-Bit Mode
36
Figure 2-8. Bus Master Decimate, 8-Bit Mode
37
Figure 2-9. Bus Master Decimate, 12-Bit Mode
38
Figure 2-10. Padding 8-Bit Data
39
Figure 2-11. 12-Bit Padding
39
Figure 2-12. Bus Master Data Shift
40
Figure 2-13. Input Gain Stage
41
Figure 2-14. Input Voltage
42
Figure 2-15. Low-Pass Filtering
42
Figure 2-16. DC Restore with Sync Stripper Sample Pulse
43
Figure 2-17. DC Restore with Programmable Clamp Pulse
44
Figure 2-18. Input LUT 12-Bit Mode
46
Figure 2-19. Input LUT Oversample Mode
46
Figure 2-20. PLL Mode with Composite Sync
47
Figure 2-21. PLL Mode with Separate Syncs
48
Figure 2-22. Internal Timing Mode (XTAL Mode)
49
Figure 2-23. Variable Scan Mode
50
Figure 2-24. Timing Control
52
Figure 2-25. Sync Stripper Line Rate
53
Figure 2-26. PLL and Clock Synthesizer
54
Figure 2-27. Timing Generator Horizontal Sync Output
55
Figure 2-28. PWG Horizontal Window Timing
57
Figure 2-29. PWG Horizontal Timing with Cropping
57
Figure 2-30. PWG Horizontal Timing, Internal Timing Mode
58
Figure 2-31. PWG Horizontal Timing, Variable Scan Mode
59
Figure 2-32. PWG Vertical Window Timing
60
Figure 2-33. Strobe Light Effect
62
Figure 2-34. Coincident Strobe Effect
62
Figure 2-35. Triggered Acquire Cycle in Slow Strobe
64
Figure 2-36. Triggered Acquire in Fast Strobe
65
Figure 2-37. Triggered Acquire in Frame Reset
66
Figure 3-1. PCI Configuration Register Map
69
Figure 3-2. PCI Interface Control Register Map
70
Figure 3-3. Board ID Registers
70
Figure 3-4. Acquisition Control Registers
71
Figure 3-5. Frame Buffer Control Registers
81
Figure 3-6. Board ID Registers
90
Figure 3-7. am Control Register Map
93
Figure 3-8. PTG Vertical Gate Generation
100
Figure 3-9. Trigger Polarity
106
Figure 3-10. Input LUT 12-Bit Mode
129
Figure 3-11. Input LUT Oversample Mode
129
Figure 3-12. Frame Buffer Control Register Map
130
Figure 3-13. Bus Master Data Shift
136
Figure 3-14. Add-On Register Map
149
Figure 4-1. PLL Serial Programming Timing
156
Figure A-1. Pcvisionplus Board, Connectors and Jumper
176
Table A-1. 15-Pin Connector
177
Table A-2. 26-Pin Connector
178
Table A-4. Break-Out Cables for Pcvisionplus
180
Table A-5. Breakout Cable 509-00066-00 Pin-Out
181
Figure A-2. Pcvisionplus Breakout Cable
182
Figure A-3. Pcvisionplus Miscellaneous Cable
182
Table A-6. Miscellaneous Cable 509-00065-00 Pin-Out
183
Figure B-1. Basic Opto-Isolator
190
Figure B-2. Opto-Coupled Input Circuit
191
Figure B-3. Input to Opto-Coupled Circuit
192
Figure B-4. Opto-Coupled Output Circuit
193
Figure B-5. Output Using Opto-Coupled Circuit
193
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