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Coreco PCVisionplus Hardware Reference Manual

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  • Page 1 (217) 352-9330 | Click HERE Find the Teledyne Dalsa / Coreco Imaging PCVisionPlus at our website:...
  • Page 2 Coreco Imaging, Inc. PCVisionplus[ Hardware Reference Manual 402-00005-00 Revision 02 February 8, 2002 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 3 All copyrights in this manual, and the hardware and software described in it, are the exclusive property of Coreco Imaging, Inc and its licensors. Claim of copyright does not imply waiver of Coreco Imaging, Inc.’s or its licensor’s other rights in the work. See the following Notice of Propri- etary Rights.
  • Page 4 PCVisionplus Hardware Reference PREFACE The PCVisionplus frame grabber captures images from analog monochrome cameras at frequencies up to 53 MHz. The PCVisionplus provides interface to a host computer through the PCI-bus. • Chapter 1, “Overview” introduces the PCVisionplus and provides operating specifications.
  • Page 5 Preface 402-00005-00 DOCUMENTATION CONVENTIONS The following conventions are used throughout this manual: Example Description CAUTION A caution calls attention to a hazard to the equipment or software; a condition, practice, or procedure that must be observed to avoid damage to or destruction of equipment. NOTE A note calls attention to essential information of special importance, interest, or assistance in operation.
  • Page 6 ..........1–2 1.2.2 PCVisionplus Timing Inputs (Standard Video) ....... .
  • Page 7 Preface 402-00005-00 2.3.1.3 Multiple Frame Acquire Mode ........2–6 2.4 Bus Master Operation .
  • Page 8 Preface PCVisionplus Hardware Reference 2.7.6 Field Shift Mode ............
  • Page 9 Preface 402-00005-00 3.1.15 Base Address Four (BADR4) R-O ......... 3–14 3.1.16 Base Address Five (BADR5) .
  • Page 10 Preface PCVisionplus Hardware Reference 3.4.1.3 Horizontal Sync Output Polarity (HSYNCPOL) R/W ..... . 3–28 3.4.1.4 Internal Timing Horizontal Sync Polarity (XTALMDHPOL) R/W .
  • Page 11 Preface 402-00005-00 3.4.6.14 Frame Reset On Vertical Sync Output Enable (FRSTONV) R/W ... . 3–42 3.4.6.15 Frame Reset Offset Duration (FROFF) R/W ......3–42 3.4.6.16 Trigger Mode (TRIGMD) R/W .
  • Page 12 Preface PCVisionplus Hardware Reference 3.4.9.7 Vertical Blank Odd Field Interrupt Enable (VBODDINTEN) R/W ... 3–52 3.4.10 Software Trigger (SOFTTRIG) W-O ........
  • Page 13 Preface 402-00005-00 3.5.1.11 Input Data Format (INMODE) R/W ........3–67 3.5.2 Bus Master Control (BMCTLX) R/W .
  • Page 14 Preface PCVisionplus Hardware Reference 4.1.1 DAC Interface ............
  • Page 15 Preface 402-00005-00 4.2.10.5 Output 4 Select (OMUX4) R/W ........4–13 4.2.10.6 DAC Reset (DACRST) .

  • Page 16: Table Of Contents

    1–4 Figure 1–4. PCVisionplus Connectors and Jumper .........
  • Page 17 4–5 Figure A–1. PCVisionplus Board, Connectors and Jumper ........
  • Page 18 A–4 Table A–4. Break-out Cables for PCVisionplus ......... . .
  • Page 19 Preface 402-00005-00 xviii Rev 02; February 8, 2002 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 20 CHAPTER 1 INTRODUCTION The PCVisionplus frame grabber digitizes monochrome analog video to 8 or 12 bits, at sample frequencies up to 53 MHz. The PCVisionplus supports broadcast standard timing (RS170, CCIR), progressive scan and non-standard (variable scan) timing. The PCVisionplus can support two monochrome cameras.
  • Page 21 402-00005-00 1.2 PCVisionplus SPECIFICATIONS • The PCVisionplus video connectors are pin-compatible with the previous PCVision PCI-bus frame grabber and camera cables. New cables support new camera features. • A hardware jumper selects the power-up state of the OPTO-22 compatible I/O port. All parallel port outputs have an initial setting of either all 0 or all 1 based on the jumper setting.

  • Page 22: Figure 1-1. Line And Frame Timing

    PCVisionplus Hardware Reference Introduction • CLK, Pixel Clock Input: single-ended TTL, programmable polarity, Frequency 10 KHz to 53 MHz. • LEN, Line Enable Input: single-ended TTL, programmable polarity. Minimum de-asserted or inactive (reset) pulse duration is one CLK period. • FEN, Frame Enable Input: single-ended TTL, programmable polarity. minimum de-asserted or inactive (reset) pulse duration is one CLK period.

  • Page 23: Figure 1-3. Set Up And Hold Timing, Clock Inverted

    T su LEN, FEN Figure 1–3. Set Up and Hold Timing, Clock Inverted 1.2.4 PCVisionplus Trigger Inputs • Trigger – 250 ns minimum pulse width, programmable edge-triggered. • Two Opto-isolator Trigger Inputs: HP HPCL-0631 dual-channel isolator (maximum ratings in Appendix B)
  • Page 24 PCVisionplus Hardware Reference Introduction • Frame Reset – two simultaneous pulse outputs; programmable delay, programmable pulse length, programmable polarity. (optionally may be used as clock inputs). FRST (Frame Reset) Vh min Minimum high-level voltage output Vl max 0.55 V Maximum low-level voltage output Ih max –32 mA...
  • Page 25 Introduction 402-00005-00 1.2.9 Host Access • Registers, LUT and Image Memory are mapped into PCI-bus 32-bit memory address space. • Registers, LUT and Image Memory support target access. 1.2.10 Bus Master Transfer • Transfer rates up to 133MB/s theoretical limit of PCI-bus; limited by bus traffic, block size, and capability of destination device.

  • Page 26: Figure 1-4. Pcvisionplus Connectors And Jumper

    • Relative Humidity – 0-90% non-condensing. • Power Requirements (typical) - 1 Ampere at +5 Volts, 5 Volt to 3.3 Volt conversion performed on the PCVisionplus board. 1.2.13 Camera Power • +12 Volts at 500 mA to cameras CAM0 and CAM1 from the PCI-bus chassis.
  • Page 27 Introduction 402-00005-00 1–8 Rev 02; February 8, 2002 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 28 The 8-bit or 12-bit data is input to a 16-by-16-bit LUT (Look-Up Table) for simple point transformation (or oversam- pling in 8-bit mode). The LUT data is output to image memory. Figure 2–1 is a block diagram of the PCVisionplus frame grabber.

  • Page 29: Figure 2-1. Pcvisionplus Block Diagram

    The PCI Configuration Registers are required for compliance with the PCI Specification. These registers are loaded by a boot PROM with information about the PCVisionplus, (memory size, register size, type of device) which the PCI-bus host uses, in conjunction with information from all other PCI-bus devices in the system, to determine an optimum configuration.
  • Page 30 Common to all interrupts are two registers found in the PCI Configuration register set: Interrupt Line (INTLN) and Interrupt Pin (INTPIN). INTPIN is initialized on power up to define the PCI-bus interrupt pin used by PCVisionplus as #INTA (this is required for PCVisionplus). The INTLN register is initialized to select the system interrupt line.
  • Page 31 PCVisionplus attempts to transfer data to a non-existent or disabled Target. Target Abort occurs when the PCVisionplus, in the process of a bus master transfer, encounters a target abort response from the destina- tion of the transfer operation (typically indicating some sort of error in the transfer). These two interrupt sources are always enabled if INTEN is set, and can be monitored or cleared by two bits (MAINT and TAINT) in the INTCTL_32 register.

  • Page 32: Figure 2-2. Non-Interlaced Acquire

    2.3 IMAGE MEMORY The PCVisionplus image memory is mapped as a 4MB region in the host system memory region. During power-up, a base address to this region is assigned by the PCI-bus host system and stored in the Base Address Four (BADR4) configuration register.

  • Page 33: Figure 2-3. Interlaced Acquire

    2.3.1.3 Multiple Frame Acquire Mode PCVisionplus has the ability to acquire and store up to eight images sequentially into image memory, with the execu- tion of one snap command. Program the Frame Count bits (FCNT) to the desired number of frames (1 to 8). For non-interlaced or interlaced acquisitions the multiple acquire mode count (FCNT) always refers to full frames.
  • Page 34 Before any type of bus master transfer can begin, the the destination address (in the host) and the transfer count (num- ber of bytes or pixels to transfer) as well as the source address (in PCVisionplus memory frame) must be programmed into PCVisionplus registers, and several other registers and bits controlling and enabling the transfer mode must be set.
  • Page 35 PCI interface circuitry. The addresses and count values are loaded into the bus master control- ler to indicate the source data for bus master operations. During bus master transfer, the PCVisionplus reads the table entries sequentially and transfers image data to the PCI-bus interface as directed. The OCT provides a very high level of control and flexibility for bus master transfers.

  • Page 36: Figure 2-5. Bus Master Zoom, 8-Bit Mode

    PCVisionplus Hardware Reference Theory of Operation In 12-bit mode and zoom by 2, each WORD read from the image buffer memory is replicated twice in the BMC before output to the PCI-bus, as shown in Figure 2–6. The transfer count must be doubled for zoom by 2. The data output is twice the data read from the image memory.

  • Page 37: Figure 2-8. Bus Master Decimate, 8-Bit Mode

    Theory of Operation 402-00005-00 In 8-bit mode and Decimate by 2, the BMC transfers every other byte (pixel) read from the image memory buffer. The byte select bit (BYTESEL) selects the even or odd bytes for transfer, as shown in Figure 2–7. The transfer count must be divided by 2;...

  • Page 38: Figure 2-9. Bus Master Decimate, 12-Bit Mode

    2.4.4.3 Padding The PCVisionplus has the capability to pad 8-bit or 12-bit image data to 16-bit values during the bus master transfer. With pad mode enabled, a value of 0x80 is added to each 8-bit pixel value in the bus master FIFO. The 0x80 is the neutral or zero value of luminosity, the color component of the YCrCb data.

  • Page 39: Figure 2-10. Padding 8-Bit Data

    2.4.4.4 Clipping The PCVisionplus provides an 8-bit data clipping feature that forces pixels with values between 0x0 and 0xF to the value 0x10, and forces pixels with values between 0xF0 and 0xFF to the value 0xEF. This clipping feature allows 8-bit image data to be bus mastered directly to a VGA target (primary surface) without seeing “color dots”...

  • Page 40: Figure 2-12. Bus Master Data Shift

    Transfer speed is mainly dependent on the host system and the target’s capabilities. Bus traffic (other bus masters arbitrating for and gaining bus ownership) and target capabilities (PCVisionplus can only transfer data as fast as the target can receive it) have implications on overall transfer speed. Within the configuration register set are several registers which define the amount of time the PCVisionplus requires for bus master operations.

  • Page 41: Figure 2-13. Input Gain Stage

    CAM0 and CAM1 connectors. The input is selected by software control. The timing is common to both inputs. Inde- pendent timing is not available. Asynchronous inputs are not supported by the PCVisionplus. The timing and syn- chronization settings apply to both inputs synchronously. Multiple monochrome cameras must be externally gen- locked or driven by the PCVisionplus programmable timing.

  • Page 42: Figure 2-14. Input Voltage

    PCVisionplus Hardware Reference Theory of Operation Video Input Gain Video Signal 0.714 V 1.428Vpeak CCIR/RS–170 75 ohm cable 75 ohm termination Figure 2–14. Input Voltage 2.5.3 Low-Pass Filters Following the gain stage, the video passes through a selectable low-pass filter, optimized for standard video frequen- cies.

  • Page 43: Figure 2-16. Dc Restore With Sync Stripper Sample Pulse

    Theory of Operation 402-00005-00 The different signal response of the two low-pass filters creates a difference in the signal delay, of approximately 35 ns, between the two filter paths. This difference must be compensated for when switching between the low-pass filters.

  • Page 44: Figure 2-17. Dc Restore With Programmable Clamp Pulse

    2.5.5 Programmable Clamp Voltage DAC The PCVisionplus DC restore circuit uses a DAC (digital to analog converter) to set the back porch clamp voltage used to establish the sampling black-level. The voltage of this DAC should be set to match the negative reference voltage of the ADC.
  • Page 45 (0 to 4096). You should calibrate the PREF and NREF for the dynamic range of the video signal you are using, without exceeding the 0.4 to 1.6 Volt range of the ADC. All reference DACs of the PCVisionplus are programmed through a serial interface. Refer to the DAC registers and programming information in Chapter 4.

  • Page 46: Figure 2-18. Input Lut 12-Bit Mode

    PCVisionplus Hardware Reference Theory of Operation OVRSM=0 INMODE=1 data Image Input Buffer Memory ILUTSADR0 Static ILUTSADR1 Page ILUTSADR2 Select ILUTSADR3 Figure 2–18. Input LUT 12-bit Mode With oversample enabled (OVRSM=1), the Input LUT provides one page for 16-bit input addressing, and there are no page select bits available, as shown in Figure 2–19.

  • Page 47: Figure 2-20. Pll Mode With Composite Sync

    402-00005-00 2.6 TIMING AND SYNCHRONIZATION The PCVisionplus has three major timing modes: PLL (Phase-Locked Loop), Internal timing (XTAL), or Variable Scan (Vscan). There are two PLL modes; stripping sync from composite video, or locking to separate horizontal and vertical sync inputs.

  • Page 48: Figure 2-21. Pll Mode With Separate Syncs

    2.6.2 Separate Sync PLL mode The PCVisionplus also supports PLL mode with separate horizontal and vertical sync inputs from cameras CAM0 or CAM1. The sync stripper is not used and the separate incoming timing signals drive the PLL and PWG directly as shown in Figure 2–21.

  • Page 49: Figure 2-22. Internal Timing Mode (Xtal Mode)

    Theory of Operation 402-00005-00 2.6.3 Internal Clock Mode (XTAL Mode) In internal clock (XTAL) mode, a frequency synthesizer and the PTG are programmed to generate the desired pixel clock and time base signals. The PTG generates separate Horizontal and Vertical sync signals that match the desired video format.

  • Page 50: Figure 2-23. Variable Scan Mode

    These inputs drive the programmable window generator (PWG) and the ADC directly. The PTG and PLL are by- passed in variable scan mode. The PCVisionplus supports area-scan format only, line-scan formats are not sup- ported. The timing inputs used in variable scan mode are single-ended TTL only. The incoming signals must be ref- erenced to ground.
  • Page 51 Theory of Operation 402-00005-00 2.7 TIMING CONTROL Figure 2–24 is a block diagram of the timing control on the PCVisionplus. Timing control is accomplished by the following circuits: • Variable Scan Input • Sync Stripper • Phase-Locked Loop • Programmable Timing Generator (PTG) •...

  • Page 52: Figure 2-24. Timing Control

    PCVisionplus Hardware Reference Theory of Operation Sync CAM0 CAM1 Composite Input Sync Clock Sync XTAL Stripper XTAL Clock Clock Pixel Clock Separate Clock RGB PLL Sync Inputs Synthesiser Variable Scan Clock Programmable Variable Scan Variable Scan Timing Timing Inputs Timing Control...

  • Page 53: Figure 2-25. Sync Stripper Line Rate

    Theory of Operation 402-00005-00 programmable timing generator (PTG) and programmable window generator (PWG) use the sync stripper output for locking to and framing incoming video. The sync stripper can be bypassed by selecting separate sync as the input to the PLL. In bypass mode, sync signals are input separately from CAM0 or CAM1 and are used by the programmable timing generator (PTG) and program- mable window generator (PWG) for locking to and framing incoming video.

  • Page 54: Figure 2-26. Pll And Clock Synthesizer

    The PTG is used in internal timebase (XTAL) mode to generate horizontal and vertical sync for gen-locking camer- as. The PTG uses a clock derived from a reference oscillator and the PCVisionplus frequency synthesizer to generate horizontal and vertical sync and Vertical reset (VRESET) to output to a camera. The PTG horizontal and vertical syncs are output to CAM0 and CAM1.

  • Page 55: Figure 2-27. Timing Generator Horizontal Sync Output

    Theory of Operation 402-00005-00 The PTG must be programmed to match the camera in use. The PTG has a vertical and horizontal counter and several registers to determine the size of the sync pulses in pixel clocks or lines. The horizontal sync is derived from two register settings HTOTAL and HESYNC. The HTOTAL value determines the number of pixel clocks in half of a horizontal sync line (up to 1024 clocks).
  • Page 56 PCVisionplus Hardware Reference Theory of Operation PTG active = (2K – Hsync low ) x (2K – Vsync low) The maximum Vsync low time is 16 lines and maximum Vsync high time is (1024 – Vsync low) lines. The C/Hsync line is always driven in XTAL mode. Make sure there is nothing driving the HSYNC inputs on CAM0 or CAM1 prior to enabling XTAL mode (TIMEMD bits).

  • Page 57: Figure 2-28. Pwg Horizontal Window Timing

    Theory of Operation 402-00005-00 HBLANK Video Stripped HSYNC HACT HOFF Offset Active memory write enable (valid video window) Figure 2–28. PWG Horizontal Window Timing In Figure 2–28, HACT and HOFF are programmed to load the entire video region. The falling edge of stripped Hsync starts the horizontal counter.

  • Page 58: Figure 2-30. Pwg Horizontal Timing, Internal Timing Mode

    PCVisionplus Hardware Reference Theory of Operation In Figure 2–29, HACT and HOFF are programmed to crop the active video region. HOFF is increased to contain part of the active video. HACT is decreased, shortening the active time and the memory load region. The region of active video that falls within the H-Active time is loaded into memory.

  • Page 59: Figure 2-31. Pwg Horizontal Timing, Variable Scan Mode

    Theory of Operation 402-00005-00 HBLANK Video HACT HOFF H Offset H Active memory write enable (valid video window) Figure 2–31. PWG Horizontal Timing, Variable Scan Mode In Figure 2–31, HACT and HOFF are programmed to crop the active video region. The selected edge of LEN starts the horizontal counter;...

  • Page 60: Figure 2-32. Pwg Vertical Window Timing

    PCVisionplus Hardware Reference Theory of Operation VBLANK Vertical Active Region VSYNC HSYNC VACTIVE VOFF V Active Vertical valid video window Figure 2–32. PWG Vertical Window Timing In Figure 2–32, VACT and VOFF are programmed to crop the active video region. The PTG Vsync, stripped Vsync, or FEN input starts the vertical counter, depending on the acquisition and timing mode selection.
  • Page 61 2.7.7 External Trigger and Strobe The PCVisionplus can acquire images based on an external event (external trigger input signal) and it can output a synchronous strobe signal coincident with the trigger cycle. The PCVisionplus also supports a synchronous strobe and asynchronous frame reset outputs.

  • Page 62: Figure 2-33. Strobe Light Effect

    PCVisionplus Hardware Reference Theory of Operation Video VBLANK Vsync Trigger Input memory write enable Figure 2–33. Strobe Light Effect As shown in Figure 2–33, the strobe may partially illuminate the current field in which the trigger and flash occur, and must continue to illuminate the full frame (two fields for interlaced video) following after the field in which the strobe light fires.
  • Page 63 Another feature of the trigger circuit is stored trigger events. By setting the TRIGMD bit, the trigger event inputs can be latched if a trigger cycle is currently in progress. Normally, PCVisionplus ignores trigger inputs if a trigger cycle is in progress. By setting TRIGMD, trigger events that occur during a trigger cycle will be latched and execute anoth- er trigger cycle immediately following the cycle in progress.

  • Page 64: Figure 2-35. Triggered Acquire Cycle In Slow Strobe

    PCVisionplus Hardware Reference Theory of Operation RGB Video VBLANK Vsync HBLANK Trigger Input TRGCYC0 FIFO Load TRGEN0 STROBE STRBDLY Figure 2–35. Triggered Acquire Cycle in Slow Strobe 2.7.7.6 Trigger on Frame-Fast Strobe Mode Fast strobe mode outputs a strobe pulse immediately after an external trigger input, unless the trigger occurs in the “no-strobe region”.

  • Page 65: Figure 2-36. Triggered Acquire In Fast Strobe

    Theory of Operation 402-00005-00 RGB Video VBLANK Vsync HBLANK Trigger Input TRGCYC0 FIFO Load TRGEN0 Strobe No-strobe Region STRBDLY Figure 2–36. Triggered Acquire in Fast Strobe 2.7.7.7 Frame Reset Mode In frame reset mode, the PWG is halted in vertical blank, waiting for an external trigger input. When the external trigger occurs, the frame reset counter is loaded and counts off the number of lines programmed in the FROFF regis- ter before starting the PWG counters.

  • Page 66: Figure 2-37. Triggered Acquire In Frame Reset

    PCVisionplus Hardware Reference Theory of Operation instead require the frame reset to occur by simply pulling the vertical sync input to the reset state, which is accom- plished by this PTG feature. Some cameras require no vertical sync when in frame reset mode, which can be accom- modated using the VSYNCEN bit to disable the PTG vertical sync output when in frame rest mode.
  • Page 67 Theory of Operation 402-00005-00 2–40 Rev 02; February 8, 2002 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 68 CHAPTER 3 REGISTERS This chapter provides a detailed description of all PCVisionplus registers and bits. The PCVisionplus contains five separate register groups: PCI Configuration Registers, PCI Interface Control Registers, Board ID Registers, Ac- quisition Control Registers, and Frame Buffer Registers. All registers support 32-bit access only.

  • Page 69: Figure 3-1. Pci Configuration Register Map

    PCI Configuration Registers These registers are loaded by a boot PROM with information about the PCVisionplus, (memory size, register size, type of device, etc.) which the PCI-bus host uses in conjunction with information from all other PCI devices in the system to determine an optimum configuration.

  • Page 70: Figure 3-2. Pci Interface Control Register Map

    Figure 3–2. PCI Interface Control Register Map Board ID Registers Address Space The PCVisionplus requires 16 DWORDs or 64 bytes of address space to map the Board ID Registers. The Board ID registers are defined as 32-bit (DWORD) access only.

  • Page 71: Figure 3-4. Acquisition Control Registers

    Registers 402-00005-00 Acquisition Control Registers Address Space The PCVisionplus requires 256K DWORDs or 1MB of address space to map the Acquisition Control Registers. Access to this space is DWORD only. BADR2 + Page # 0x00 PTG Horizontal 1 (PTGH1) 3–27...
  • Page 72 PCVisionplus Hardware Reference Registers Frame Buffer Control Registers The PCVisionplus requires 64K DWORDs or 1MB of address space to map the Frame Buffer Control Registers. Access to this space is DWORD only. BADR3 + Page # 0x00 Acquisition Control (ACQREG) 3–64...
  • Page 73 This register contains the Imaging Technology Incorporated (Coreco Imaging, Inc.) vendor identification number assigned by the PCI SIG (Special Interest Group). This register value 0x112F (4399 Decimal) identifies the PCVi- sionplus as manufactured by Coreco Imaging, Inc.. This register is boot-loaded at power-up and is read only. 3.1.2 Device Identification (DID) R-O...
  • Page 74 3.1.3.1 I/O Space Enable (IOEN) R/W This bit allows the PCVisionplus to decode and respond as a target to I/O cycles which are to regions defined as I/O space in the base address registers. This bit is initialized to zero at power-up. This bit should be written to one as part of the initialization routine.
  • Page 75 3.1.3.3 Bus Master Enable (PCIBMEN) R/W This bit allows the PCVisionplus to function as a bus master in the PCI system. This bit is initialized to zero at power- up. This bit should be written to one as part of the initialization routine.
  • Page 76 No data parity reported Data parity reported 3.1.4.2 Signaled Target Abort (STABT) R/W1C This bit is set whenever the PCVisionplus aborts a cycle when addressed as a target. This bit is cleared by writing it to one (1). STABT Function...
  • Page 77 No master abort Master abort occurred 3.1.4.5 Signaled System Error (SSERR) R/W1C This bit is set whenever the PCVisionplus asserts the #SERR signal due to a system error. This bit is cleared by writ- ing it to one (1). SSERR...
  • Page 78 This register defines the number of PCI clocks a bus master cycle will be guaranteed. Setting this register will guar- antee the PCVisionplus will be granted the bus during bus master operations for the set amount of time. The value set by LAT(4–0) = # of clocks x 8.
  • Page 79 This register is used to define the configuration header layout for bytes at address 0x10 thru 0x3F. It also defines the PCVisionplus as a single function PCI device. This register is boot-loaded at power-up to a value of zero and is read only.
  • Page 80 PCVisionplus Hardware Reference Registers 3.1.12 Base Address One (BADR1) R-O Address offset 0x14 BADR1 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 ADR15 ADR14 ADR13 ADR12 ADR11 ADR10 ADR9 ADR8 ADR23 ADR22 ADR21 ADR20 ADR19 ADR18 ADR17 ADR16 ADR31 ADR30...

  • Page 81: Figure 3-5. Frame Buffer Control Registers

    This register is boot-loaded at power-up with a value that indicates the amount of address space required for the PCVisionplus Image memory (4MB required). During power-up the PCI host system reads this register to determine the size of the address region and assigns a base address in the memory address region (always memory mapped).
  • Page 82 ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 This address register is not used by the PCVisionplus and returns all zeros if read. This register is read only. 3.1.17 Expansion ROM Base Address (XROM) R-O Address offset 0x30 XROM ADR7 ADR6 ADR5...
  • Page 83 This register indicates the PCI interrupt pin used by the PCVisionplus. This register is boot-loaded at power-up with a value of 0x1 indicating PCI interrupt pin #INTA is connected to the PCVisionplus. This register is read only. 3.1.20 Minimum Grant (MINGNT) R-O...
  • Page 84 3.2 PCI INTERFACE CONTROL REGISTERS The PCVisionplus requires 16 DWORDs of address space to map several registers used to control the PCI host inter- face circuitry. This section describes each of the registers function, address offset, and initial power-up values. The Interface Control Registers are mapped into system 32-bit address space specified by the Base Address Zero (BADR0) register.
  • Page 85 ADR0 must be zero). The two lsbs (least significant bits) will be zero during the address phase of a bus master write transfer indicating to the target that the data from the PCVisionplus is in linear format and that the PCVision- plus is burst capable (therefore the target should not arbitrarily disconnect after the first data transfer).
  • Page 86 (removing) the interrupt’s assertion. This register must be used in conjunction with the many other interrupt enable and clear registers and bits on the PCVisionplus. The following conditions could produce a PCI-bus interrupt: Bus Master Transfer Count reaches zero, Target Abort, Master Abort, or a PCVisionplus interrupt defined in the INTENREG or AMINTEN registers.
  • Page 87 This bit indicates that a PCI-bus interrupt was generated by the PCVisionplus encountering a Target Abort during a PCI Bus cycle in which the PCVisionplus was bus master. This interrupt source is always enabled. This bit operates as read/write-one-clear. Writing one to this bit resets it to zero. Writing zero has no effect.
  • Page 88 3.2.5.1 FIFO Full (FIFOFL) R-O This bit is set to one when the FIFO becomes full during a bus master transfer from the PCVisionplus to the PCI-bus. FIFO Full indicates 8 DWORDs of the bus master transfer are in the FIFO waiting to be written to the destination address of the transfer.
  • Page 89 3.2.5.5 Software Reset (RST) R/W This bit can be used by software to reset the PCVisionplus internal hardware. Writing a one to this bit causes a reset to the PCVisionplus. This bit must be set to zero to remove the reset for proper operation of the PCVisionplus.

  • Page 90: Figure 3-6. Board Id Registers

    3.3 BOARD ID REGISTERS These registers are used to check the build status and revision of the PCVisionplus, and to load the FPGAs during board initialization. The 64 DWORDs are mapped into system address space starting at the address in the BADR1 register.
  • Page 91 No module installed Expansion module installed 3.3.1.6 Revision (REV) R-O The two REV bits reflect the revision of the PCVisionplus hardware. These bits allow software to identify function- ality changes to the PCVisionplus hardware. 3–24 Rev 02; February 8, 2002...
  • Page 92 PCVisionplus Hardware Reference Registers 3.3.2 FPGA Programming (ORCAPRGM) R/W BADR1 + 0x04 PCP_ORCAPRGM_32 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...

  • Page 93: Figure 3-7. Am Control Register Map

    3.4 ACQUISITION MODULE CONTROL REGISTERS These registers control the analog input section of the PCVisionplus. This 1MB group of addresses is organized into two 64K DWORD areas: AM Control, and Input LUT DWORD access. The AM Control registers are mapped into system address space starting at the address in the BADR2 register.
  • Page 94 PCVisionplus Hardware Reference Registers 3.4.1 PTG Horizontal 1 (PTGH1) R/W BADR2 + 0x00 PCP_PTGH1_32 HTOTAL7 HTOTAL6 HTOTAL5 HTOTAL4 HTOTAL3 HTOTAL2 HTOTAL1 HTOTAL0 HESYNC5 HESYNC4 HESYNC3 HESYNC2 HESYNC1 HESYNC0 HTOTAL9 HTOTAL8 XTALMD Reserved Reserved Reserved Reserved HSYNCPOL HESYNC7 HESYNC6 HPOL Reserved...
  • Page 95 This bit only affects the PTG Hsync input to the PWG, and does not affect the signals output to the camera interface, or any other timing circuits. This bit gives additional flexibility to programming the PWG with cameras that respond slowly to the Hsync from the PCVisionplus. XTALMDHPOL Function...
  • Page 96 PCVisionplus Hardware Reference Registers 3.4.2 PTG Vertical 1 (PTGV1) R/W BADR2 + 0x08 PCP_PTGV1_32 VTOTAL7 VTOTAL6 VTOTAL5 VTOTAL4 VTOTAL3 VTOTAL2 VTOTAL1 VTOTAL0 VSEND3 VSEND2 VSEND1 VSEND0 VTOTAL11 VTOTAL10 VTOTAL9 VTOTAL8 Reserved Reserved Reserved Reserved VERROR EDONP VSYNCPOL VSEND4 Reserved Reserved...
  • Page 97 FRSTONV bit must enable Frame Reset output on the VSYSNC connection. The PCVisionplus frame reset line must be connected to the camera’s external trigger input. Following an external trigger input to the PCVisionplus, the Frame Reset pulse drives the camera trigger. The length of the Frame Reset 3–30 Rev 02;...
  • Page 98 PCVisionplus Hardware Reference Registers Pulse determines the camera’s shutter speed. At the end of the Frame Reset pulse, the camera’s VD (vertical drive) is driven after a fixed four-line period (integration) after which the camera outputs its frame image. EDONP Function Normal operation (disable E–Donpisha)
  • Page 99 Registers 402-00005-00 The front porch region is the number of lines from the end of active video to the start of Vsync low. The RS170 front porch is 3 lines, and VGSTRT = 262.5 – 3 = 259.5. The CCIR front porch is 2.5 lines, and VGSTRT = 312.4 – 2.5 = 310.

  • Page 100: Figure 3-8. Ptg Vertical Gate Generation

    PCVisionplus Hardware Reference Registers Vsync VGATE Start pulse End pulse VGSTRT VGEND Figure 3–8. PTG Vertical Gate Generation VGSTRT defines the start of the vertical gate region, and VGEND defines the end of the vertical gate region. This area is defined to prevent a frame reset from occurring within the vertical sync.
  • Page 101 Hsync. HACT determines the number of pixel clocks to stop loading the memory. When the counter stops, the EOL (end of line) is loaded. PCVisionplus uses the EOL to determine the end of a horizontal line. The horizontal active region (HACT – HOFF) must be a whole multiple of 8.
  • Page 102 PCVisionplus Hardware Reference Registers boundary. If the number of active pixels is not divisible by 8, the memory controller will acquire undesired pixels up to the next 8-pixel boundary. 3.4.5 PWG Vertical (PWGV) R/W BADR2 + 0x14 PCP_PWGV_32 VOFF7 VOFF6...
  • Page 103 Registers 402-00005-00 Use the following formula to calculate VOFF: VOFF = number of lines from FEN to the start of active video – 1 VOFF Function Start loading memory 1 line after FEN edge Start loading memory 2 lines after FEN edge Start loading memory 3 lines after FEN edge Start loading memory 4 lines after FEN edge .
  • Page 104 PCVisionplus Hardware Reference Registers 3.4.5.5 15-Pin TTL Trigger 0 Status (EXTRIGSTAT0_15) R-O This read only bit reflects the status of the TTL Trigger 0 input on the 26-pin video connector. EXTRIGSTAT0_26 Status Trigger input is 0 Trigger input is 1 3.4.5.6 Opto-Isolator Trigger 0 Status (OPTOSTAT0) R-O...
  • Page 105 Registers 402-00005-00 3.4.6 Input Control 1 (INCON1) R/W BADR2 + 0x18 PCP_INCON1_32 WENMD SKPFLDMD TRIGCYC TRIGPOL TRIGSEL2 TRIGSEL1 TRIGSEL0 TRIGEN Reserved STRBDLY3 STRBDLY2 STRBDLY1 STRBDLY0 STRBEN STRBPOL STRBMD FROFF1 FROFF0 FRSTONV FRSTSZ FRSTPOL FRSTMD STBDLY5 STRBDLY4 Reserved TRIGMD FROFF7 FROFF6 FROFF5 FROFF4 FROFF3...

  • Page 106: Figure 3-9. Trigger Polarity

    Trigger cycle enabled 3.4.6.2 Trigger Source Select (TRIGSEL) R/W The three TRIGSEL bits define which of seven trigger signals begins a trigger cycle. PCVisionplus has one software trigger, three TTL-level Schmidt Trigger inputs, two Opto-coupled trigger inputs, and one RS-422 differential trig- ger input.
  • Page 107 Registers 402-00005-00 3.4.6.4 Trigger Cycle Status (TRIGCYC) R-O This bit reflects the status of the trigger cycle. TRGCYC Function No trigger cycle in progress Trigger cycle in progress 3.4.6.5 Skip Field Mode (SKPFLDMD) R/W This bit forces a triggered acquisition to skip one field after an external trigger cycle. The Programmable Window Generator (PWG) waits for one field before acquiring the number of fields indicated by the SMODE bit.
  • Page 108 PCVisionplus Hardware Reference Registers 3.4.6.9 Strobe Output Enable (STRBEN) R/W This bit enables the strobe output during trigger cycles. The signal driver is always on; this bit disables the pulse generation internally. If the pulse output is disabled, the driver takes the “inactive” state defined by the STRBPOL bit (STROBEx pins are low if STRBEN is 1 and STRBPOL is 0).
  • Page 109 Registers 402-00005-00 3.4.6.12 Frame Reset Polarity Select (FRSTPOL) R/W This bit selects the polarity of the frame reset pulse output on the camera connector during a frame reset cycle. Pro- gram this bit to match the pulse polarity required by the camera in use. The length of the Frame Reset pulse is selected by the FRSTSZ bit.
  • Page 110 PCVisionplus Hardware Reference Registers 3.4.6.16 Trigger Mode (TRIGMD) R/W The TRIGMD bit enables a trigger latch. With the latch disabled, additional triggers that occur during a triggered acquisition are ignored. With the latch enabled, triggers that occur during a triggered acquisition are latched, and another triggered acquire begins immediately following completion of the current triggered acquire cycle.
  • Page 111 Registers 402-00005-00 3.4.7 Input Control 2 (INCON2) R/W BADR2 + 0x1C PCP_INCON2_32 VSCLK VIDEO LPFSEL TIMEMD2 TIMEMD1 TIMEMD0 DACCS PLLCS INSEL VSYNCEN FLDSHFT FLDSEL FLDPOL FENPOL LENPOL VCLKPOL OVRSM MISCIN0 MISCOUT2 MISCOUT1 MISCOUT0 VSCANTST SMODE MISCIN2 MISCIN1 ILUT ILUT ILUT ILUT Reserved Reserved...
  • Page 112 PCVisionplus Hardware Reference Registers 3.4.7.2 DAC Chip Select (DACCS) R/W This bit enables programming the DAC registers. Refer to “DAC Programming” in Chapter 4 for details. DACCS Function DAC in program mode DAC in normal operation mode 3.4.7.3 Timing Mode Select (TIMEMD) R/W These three bits define the timing mode to be external timing (PLL), Internal (XTAL), or Variable Scan (VSCAN).
  • Page 113 3.4.7.8 Variable Scan Clock Input Polarity Select (VCLKPOL) R/W The VCLKPOL bit can invert the incoming variable scan clock when PCVisionplus is in variable scan mode. Inter- nal circuits sample the video signal on the rising edge of the clock. If your camera uses a falling edge clock, enable the invert.
  • Page 114 PCVisionplus Hardware Reference Registers 3.4.7.11 Field Polarity Input Select (FLDPOL) R/W The FLDPOL bit defines the polarity of the selected field output from the PWG (for interlaced images only) in VSCAN mode and separate sync input PLL mode. The convention used here is, Field=0 is an Even field, and Field=1 is an Odd field.
  • Page 115 Registers 402-00005-00 3.4.7.16 VSCAN Test Mode (VSCANTST) R/W This bit enables a diagnostic test mode. Applications should not enable this bit. VSCANTST Function Normal mode VSCAN Test mode 3.4.7.17 Misc Output (MISCOUT2, MISCOUT1, MISCOUT0) R/W These three bits control output drivers for the external outputs (MISC_IO_OUT2, MISC_IO_OUT1, MISC_IO_OUT0) on the video connectors.
  • Page 116 PCVisionplus Hardware Reference Registers 3.4.8 AM Interrupt Status (AMINTCLR) R/W1C BADR2 + 0x20 PCP_AM_INTCLR_32 VBODD VBEVEN VBLANK TCNTINT PIOINT EOTINT SOTINT Reserved INTSTAT INTSTAT INTSTAT STAT STAT STAT STAT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
  • Page 117 Registers 402-00005-00 3.4.8.3 Programmable I/O Interrupt Status (PIOINTSTAT) R/W1C This bit reflects the status of the Parallel Port interrupt input. This interrupt is enabled by the PIOIEN bit in the AM Interrupt Control register (AMINTEN). Writing one to this status bit clears the interrupt request. PIOINTSTAT Status No interrupt request pending...
  • Page 118 PCVisionplus Hardware Reference Registers 3.4.9 AM Interrupt Control (AMINTEN) R/W BADR2 + 0x24 PCP_AM_INTEN_32 VBODD VBEVEN VBLANK TCNT Reserved PIOINTEN EOTINTEN SOTINTEN INTEN INTEN INTEN INTEN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
  • Page 119 Registers 402-00005-00 3.4.9.3 Input Port Interrupt Enable (PIOIEN) R/W The PIOIEN bit enables the interrupt input bit on the input port. The input is edge triggered. The polarity is selected by the IPINTPOL bit. The status and clear bit for this interrupt is PIOINTSTAT, in the AMINTCLR register. PIOIEN Function Disable interrupt input...
  • Page 120 PCVisionplus Hardware Reference Registers 3.4.10 Software Trigger (SOFTTRIG) W-O BADR2 + 0x28 PCP_SOFTTRIG_32 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 DATA31 DATA30 DATA29...
  • Page 121 There is a fixed delay of three clock periods from the falling edge of Hsync to the start of the back porch counters. Re-syncing of the PCVisionplus internal circuitry adds a margin of error of one clock period of the crystal clock (69.84 ns) used to control the clamp circuit.
  • Page 122 PCVisionplus Hardware Reference Registers 3.4.11.3 Back Porch End Position (PBEND) R/W The eight BPEND bits define the end of the programmable clamp pulse, used for DC restoration (clamping) during the “back porch” of the video signal. The end of the clamp pulse is a number of clocks from the falling edge of HSYNC (assuming an active low horizontal sync).
  • Page 123 Registers 402-00005-00 3.4.12 PLL Programming Port (PLLPROG) R/W BADR2 + 0x34 PCP_PLLPROG_32 Reserved Reserved Reserved Reserved Reserved Reserved Reserved PLLSDATA Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
  • Page 124 PCVisionplus Hardware Reference Registers 3.4.14 Timer Counter (TIMER) R/W BADR2 + 0x3C PCP_TIMER_32 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16 Reserved Reserved Reserved...
  • Page 125 Registers 402-00005-00 3.4.15 Parallel IO Port Control (PORTCON) R/W BADR2 + 0x40 PCP_PORTCON_32 STRBIN INPORT Reserved INTINSTAT INREGCLR INSTRBPOL INREGENB OUTSTB STAT IPOL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
  • Page 126 PCVisionplus Hardware Reference Registers 3.4.15.3 Input Port Strobe Polarity (INSTRBPOL) R/W This bit defines which edge of the input strobe clocks data into the input buffer. This bit is ignored if INREGENB is zero. This bit is cleared during power up and system reset.
  • Page 127 Registers 402-00005-00 3.4.16 PIO Output Port (OUTPORT) R/W BADR2 + 0x44 PCP_OUTPORT_32 OUTP7 OUTP6 OUTP5 OUTP4 OUTP3 OUTP2 OUTP1 OUTP0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
  • Page 128 Reserved Reserved Reserved Reserved Reserved This register must be initialized to zero for normal operation of the PCVisionplus image memory. Application pro- grams must not write to this register. 3.4.19 LUT Programming BADR2 + 0x40000–0x7FFFF Low LUT Word Access DATA7...

  • Page 129: Figure 3-10. Input Lut 12-Bit Mode

    Registers 402-00005-00 OVRSM=0 INMODE=0 data Image Input Buffer Memory ILUTSADR0 Static ILUTSADR1 Page ILUTSADR2 Select ILUTSADR3 Figure 3–10. Input LUT 12-bit Mode With OVRSM=1 (oversample enabled), the Input LUT provides one page for 16-bit input addressing, and there are no page select bits available, as shown in Figure 3–11. You can load only one transform. If you are not oversampling the pixel data, program the LUT to ignore the high byte input (delayed pixel) by repeating the same data pattern.

  • Page 130: Figure 3-12. Frame Buffer Control Register Map

    PCVisionplus Hardware Reference Registers 3.5 FRAME BUFFER CONTROL REGISTERS These registers control data acquisition into the frame buffer memory. This 1MB group of addresses is organized into four 64K DWORD areas: Frame Control registers, Output Control Table, Scatter Gather (or DMA) Table, AMCC Add-on registers.
  • Page 131 Registers 402-00005-00 3.5.1 Acquisition Control (ACQREG) R/W BMADR3 + 0x00 PCP_ACQREG_32 ACQADR Reserved Reserved FLDSEL1 FLDSEL0 FCNT2 FCNT1 FCNT0 AMFLD AMVB PREVFLD FLDSTART GSTAT NEWAQ ACQMD1 ACQMD0 START STAT STAT Reserved Reserved Reserved Reserved Reserved Reserved INMODE1 INMODE0 Reserved Reserved Reserved Reserved Reserved...
  • Page 132 PCVisionplus Hardware Reference Registers 3.5.1.2 Frame Count (FCNT) R/W The three FCNT bits determine the number of images stored in memory after each acquire command (snap, grab, or triggered acquire). The FCNT bits allow up to eight images. The image size also determines the number of images that will fit into a 4MB memory frame.
  • Page 133 Registers 402-00005-00 vertical blank. It is recommended that the grab status bit GSTAT in this register be monitored to determine when the acquisition is complete. 3.5.1.5 New Acquire (NEWAQ) R-O This bit is set to one whenever a snap or grab command is written to the ACQMD bits and is cleared automatically when acquisition begins.
  • Page 134 PCVisionplus Hardware Reference Registers 3.5.1.10 Acquisition Field Status (AMFLDSTAT) R-O The AMFLDSTAT bit reflects the current field of the video input from the AM interface, used to a frame the video input to memory. AMFLDSTAT Function Even field Odd field 3.5.1.11 Input Data Format (INMODE) R/W...
  • Page 135 Registers 402-00005-00 3.5.2 Bus Master Control (BMCTLX) R/W BADR3 + 0x010 PCP_BMCTLX_32 BMBYTE SCANDIR CLIPEN PADEN BMZOOM1 BMZOOM0 BMSHIFT BMEN START7 START6 START5 START4 START3 START2 START1 START0 Reserved START14 START12 START12 START11 START10 START9 START8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved...

  • Page 136: Figure 3-13. Bus Master Data Shift

    PCVisionplus Hardware Reference Registers Image Buffer Memory xxxx 11 ... 0 xxxx 11 ... 0 xxxx 11 ... 0 xxxx 11 ... 0 pixel3 pixel2 pixel1 pixel0 Bus Master Controller Output 11 ..0 xxxx 11 ..0 xxxx pixel1 pixel0 Figure 3–13.
  • Page 137 Registers 402-00005-00 separate, automatic right-shift of 12-bit data. BMSHIFT is a left-shift. In both 8-bit and 12-bit modes, the transfer count should be half the original image value in bytes. A 1024 pixel line of 12-bit pixels occupies 2048 bytes or 512 DWORDs in image memory. The transfer count should be 512 DWORDs if no decimation occurs.
  • Page 138 PCVisionplus Hardware Reference Registers 3.5.2.8 DMA Start Address (DMASTART) R/W The 15 bit DMASTART address defines the first DMA Table address location used in a bus master transfer. The DMA Table address range is 0 to 32767 (or 0x7FFF). DMASTART...
  • Page 139 Registers 402-00005-00 3.5.4 Acquisition Start (ACQSTRT) R/W BMADR3 + 0x18 PCP_ACQSTRT_32 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 Reserved ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
  • Page 140 PCVisionplus Hardware Reference Registers 3.5.5 Acquire Line Interrupt (ACQLINEINT) R/W BMADR3 + 0x1C PCP_ACQ_LINE_INT_32 INTADR14 INTADR13 INTADR12 INTADR11 INTADR10 INTADR9 INTADR8 INTADR7 LSBMASK0 INTADR21 INTADR20 INTADR19 INTADR18 INTADR17 INTADR16 INTADR15 Reserved Reserved Reserved Reserved Reserved LSBMASK3 LSBMASK2 LSBMASK1 Reserved Reserved...
  • Page 141 Registers 402-00005-00 3.5.5.2 Interrupt Address LSB Mask (LSBMASK) R/W The four LSBMASK bits enable masking the lower order bits in the Acquire Interrupt Address. Masking changes the resolution of the acquire line interrupt. Only the settings shown below are valid. A higher order bit can only be masked off if all lower bits are also masked off.
  • Page 142 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved This register provides status and clear bits for all PCVisionplus interrupt sources. Mnemonic Function ACQLINEINTSTAT Acquire Line Interrupt Status BMINTSTAT Bus Master Complete Interrupt Status AMINTSTAT AM Interrupt Status EOFINTSTAT End of Frame Interrupt Status 4–31...
  • Page 143 Registers 402-00005-00 3.5.8.1 Acquire Line Interrupt Status (ACQLINEINTSTAT) R/W1C The ACQLINEINTSTAT bit indicates an image acquire has occurred to the memory address programmed in the ALINEINT register. The interrupt source is enabled by the ALINEINTEN bit in the INTENREG register. Read this bit to check the status.
  • Page 144 PCVisionplus Hardware Reference Registers 3.5.9 Interrupt Control (INTENREG) R/W BMADR3 + 0x2C PCP_INTENREG_32 ACQLINE Reserved Reserved Reserved Reserved EOFINTEN AMINTEN BMINTEN INTEN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
  • Page 145 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved This register provides status of the current PCVisionplus memory acquire address. ACQADR Acquire Address 0x0 (DWORD address) 0x00080 0x00100 ..0x7FFE 0x3FFF00 0x7FFF 0x3FFF80 3–78...
  • Page 146 PCVisionplus Hardware Reference Registers 3.5.11 Output Control Table (OCTDATA) R/W BADR3 + 0x40000–0x7FFFC OCTDATA ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 ADR15 ADR14 ADR13 ADR12 ADR11 ADR10 ADR9 ADR8 XCNT3 XCNT2 XCNT1 XCNT0 Reserved ADR18 ADR17 ADR16 Reserved Reserved...
  • Page 147 DWORDs (0x00100000) transfers more than the entire 4MB memory frame. For example, programming XCNT to 2048K DWORDs transfers the entire memory frame twice. The PCVisionplus image memory is partitioned into 2048-byte pages. An OCT entry must access data within a single 2048-byte page. Page boundary crossing is not allowed during a bus master transfer.
  • Page 148 PCVisionplus Hardware Reference Registers 3.5.12 Scatter Gather Table (DPDATA) R/W BADR3 + 0x80000–0xBFFFC DPDATA DPDATA7 DPDATA6 DPDATA5 DPDATA4 DPDATA3 DPDATA2 DPDATA1 DPDATA0 DPDATA15 DPDATA14 DPDATA13 DPDATA12 DPDATA11 DPDATA10 DPDATA9 DPDATA8 DPDATA23 DPDATA22 DPDATA21 DPATAT20 DPDATA19 DPDATA18 DPDATA17 DPDATA16 DPDATA31 DPDATA30...

  • Page 149: Figure 3-14. Add-On Register Map

    DATA25 DATA24 This register must be programmed once during PCVisionplus initialization, after power up and FPGA loading. The BMEN bit in the BMCTLX register (Frame Buffer Control registers) must be zero to access this register. Write the value 0x0024 4000 in location zero of the scatter gather table (DMA table) then write any value to this address to transfer the value into the correct location.
  • Page 150 DATA25 DATA24 This register initializes the PCVisionplus bus master port, and must be programmed once during PCVisionplus init- ialization, after power up and FPGA loading. The BMEN bit in the BMCTLX register (Frame Buffer Control regis- ters) must be zero to access this register. Write the value 0x1000 0000 in location zero of the scatter gather table (DMA table) then write any value to this address to transfer the value into the correct location.
  • Page 151 Registers 402-00005-00 3.5.13.4 Manual Transfer Count (MXCNT) W-O BADR3 + 0xC000C PCP_MXCNT_32 XCNT7 XCNT6 XCNT5 XCNT4 XCNT3 XCNT2 XCNT1 XCNT0 XCNT15 XCNT14 XCNT13 XCNT12 XCNT11 XCNT10 XCNT9 XCNT8 XCNT23 XCNT22 XCNT21 XCNT20 XCNT19 XCNT18 XCNT17 XCNT16 XCNT31 XCNT30 CXNT29 XCNT28 XCNT27 XCNT26 XCNT25...
  • Page 152 DAC and PLL PROGRAMMING 4.1 DAC REGISTERS PCVisionplus contains two Dual-DAC (Digital to Analog Converter) devices. Each of the two devices contains two 13-bit DACs that control the ADC reference voltages, DC Restore (clamp) Voltage and the Sync Stripper Line Rate.
  • Page 153 PREF RATE NREF Only one commands is supported on the PCVisionplus. Each 32-bit transfer programs two new DAC values, and updates all four DACs from the internal buffers. No other values of address and commands are supported. A0 C1 C0...
  • Page 154 DAC and PLL Programming PCVisionplus Hardware Reference 4.1.3 DC Restore Reference DAC This DAC programs the clamp voltage (PCLAMP) used to DC Restore the AC coupled video input. The incoming video signal is sampled during the back porch and is clamped to the voltage level programmed in this DAC.
  • Page 155 DAC and PLL Programming 402-00005-00 4.2 PLL REGISTERS PCVisionplus contains a PLL (Phase Lock Loop) for line locked clock operations (PLL mode) and for frequency synthesis (XTAL mode). The PLL internal registers are accessed through a serial interface. 4.2.1 PLL Interface The PLLCS bit in the INCON2 register and the PLLPRG register program the PLL.

  • Page 156: Figure 4-1. Pll Serial Programming Timing

    DAC and PLL Programming PCVisionplus Hardware Reference Notice the difference between the 15 reg writes in a write cycle and the 15 reg reads in a read cycle. During the read, the first clock is associated with valid data (A0), but in a write the first clock is associated with the R/W bit. Due to this different alignment, the three address bits and the 11 data bits are read with the first 14 clocks (last data D10 is read out with the 14th clock).
  • Page 157 These bits program an additional PLL feedback divider output with a programmable phase, which can be selected at Output 3. The default setting is 0x3. PCVisionplus does not use this mode of the PLL, and this register should always be programmed to 0x0.
  • Page 158 These bits program an additional feedback divider output but with a programmable phase, which can be selected at Output 4. The default setting is 0x6. PCVisionplus does not use this mode of the PLL, and this register should always be programmed to 0x0.
  • Page 159 DAC and PLL Programming 402-00005-00 4.2.8 PLL Register 4 (PLLA4) PLL Address 0x4 PCR_PLLA4_16 INTFLT PDEN PFD2 PFD1 PFD0 VCO2 VCO1 VCO0 Reserved Reserved Reserved Reserved Reserved CLKSEL INTVCO This register contains several control bits for the VCO (voltage controlled oscillator) and the phase detector. Bit 10 must always be one.
  • Page 160 4.2.8.4 Loop Filter Select (INTFLT) R/W This bit selects between external and internal loop filter mode. The PCVisionplus uses an external loop filter. This bit should always be 0. Power-up default setting is 1, which must be changed to 0.
  • Page 161 DAC and PLL Programming 402-00005-00 4.2.9 PLL Register 5 (PLLA5) R/W PLL Address 0x5 PCR_PLLA5_16 PDB1 PDB0 PDA1 PDA0 SWLW FBKPOL FBKSEL Reserved Reserved Reserved Reserved Reserved FINEEN LDLG This register controls the PLL feedback divider. Bit 10 in this register must always be one. Mnemonic Function FBKSEL...
  • Page 162 DAC and PLL Programming PCVisionplus Hardware Reference 4.2.9.5 Output Post Scaler (PDA) R/W These two bits define the divide by value of the output post scaler. The default setting is 0. Refer to the Examples for Programming PLL and XTAL mode for calculating PLL register values.
  • Page 163 8 (pos edge) 8 (neg edge) 10 (neg edge) 4.2.10.2 Output 1 Select (OMUX1) R/W The OMUX1 bit selects the source to output clock 1 which is the clock output used on PCVisionplus. Always pro- gram to zero. OMUX1 Function...
  • Page 164 DAC and PLL Programming PCVisionplus Hardware Reference 4.2.10.3 Output 2 Select (OMUX2) R/W The OMUX2 bit selects the source to output clock 2, which is not used on the PCVisionplus. Always program OMUX2 to zero. 4.2.10.4 Output 3 Select (OMUX3) R/W The OMUX3 bit selects the source to output clock 3, which is not used on the PCVisionplus.
  • Page 165 DAC and PLL Programming 402-00005-00 4.3 PROGRAMMING EXAMPLE FOR PLL MODE This example provides detailed calculations for programming the PLL and PWG registers in PLL mode. Either the “total horizontal line time” or the “active time” is required, and the desired number of pixels in the output; either active or total.
  • Page 166 DAC and PLL Programming PCVisionplus Hardware Reference Calculate the divider ratio for the feedback path: Always set PDB to 1 (register value of 0x3) and find Fdiv using the following formula: Fdiv = [Total number of pixels in horizontal period / 1]...
  • Page 167 DAC and PLL Programming 402-00005-00 PLLA6 = 0x44[0xxx] (where xxx = LCOUNT bits, from value found in tables) LCOUNT = use bit definition for the value found in tables. OMUX1 = 0 (use default) EXTREF = 1 (external reference Input operation) Calculate Window Generator Horizontal settings as follows: HACTIVE = [total # of pixels from hsync to end of the active region] –...
  • Page 168 DAC and PLL Programming PCVisionplus Hardware Reference Total Line per Field = 262.5 Line per Vsync = 3 Lines in Vblank = 14 Lines in Active Max = 242.5 (use 240) For CCIR: Total Lines per Frame = 625 Total Line per Field = 312.5 Line per Vsync = 2.5...
  • Page 169 DAC and PLL Programming 402-00005-00 4.4 PROGRAMMING EXAMPLE FOR XTAL MODE This example provides detailed calculations for programming the PLL and PWG registers in XTAL mode. The for- mulas are only slightly different from the ones used for PLL mode. The total horizontal line time or active time is required as well as the desired number of output pixels, either active or total.
  • Page 170 DAC and PLL Programming PCVisionplus Hardware Reference Calculate the divider ratio Rdiv. Rdiv divides the fixed XTAL source down to match the frequency of the feed- back path. Rdiv = Fixed clock source / line rate = 14.318 MHz / line rate For NTSC and RS-170: line rate = 15.734 KHz.
  • Page 171 DAC and PLL Programming 402-00005-00 PLLA4 = 0x75[1xxx] (where xxx = VCO[0:2] ) VCO bits = (calculated in step 3) PFD = 0x3 (PFD gain always set to 15uA/2pi-rad) PDEN = 1 (phase detector enabled) INTFLT = 0 (external loop filter selected) CLKSEL = 1 (select Pclk as feedback source) MSB = 1 (reserved bit must be 1) PLLA5 = 0x5[11xx]3 (where xx= PDA bits for PDA value in tables)
  • Page 172 DAC and PLL Programming PCVisionplus Hardware Reference For RS-170: Active = 52.656 us Hsync = 4.7 us Back Porch = 4.7 us For CCIR: Active = 51.95 us Hsync = 4.7 us Back Porch = 5.8 us NOTE The Active region must be divisible by 8.
  • Page 173 DAC and PLL Programming 402-00005-00 Interlaced: VTOTAL = [( ______ / 2) – .5 ] x 2 = _____ for Non-interlaced: VTOTAL = [(Total lines per frame ) – .5 ] x 2 Non-interlaced: VTOTAL = [( ______ ) – .5 ] x 2 = _____ VSEND = ( # of lines in Vsync –...
  • Page 174 DAC and PLL Programming PCVisionplus Hardware Reference of pixels to 644. This will cause the pixel clock calculation to give a slightly smaller Pclk producing more pixels from the fixed active time. Cropping can be adjusted to display only 640 pixels.
  • Page 175 DAC and PLL Programming 402-00005-00 4.5 TABLES FOR PROGRAMMING EXAMPLES PDA bits = 0x3: (PDA value = 1) PDA value LCNT value PDA x LCNT 4 +/– 8 +/– PDA bits = 0x2: (PDA value = 2) PDA value LCNT value PDA x LCNT 4 +/–...

  • Page 176: Figure A-1. Pcvisionplus Board, Connectors And Jumper

    8 input and 8 output, high-drive TTL channels. A jumper labeled “I/O Level” on the PCVisionplus board sets the power-up state of the parallel port outputs. All parallel port outputs have an initial setting of either all 0 or all 1 based on the jumper setting. Refer to Figure A–1.

  • Page 177: Table A-1. 15-Pin Connector

    The 15-pin D-Sub connector is pin compatible with standard camera adapter cables for single camera interfacing. This connector supports one camera. The PCVisionplus can supply up to 1A at 12V from chassis power. (new signals have been added to pins that supported a second camera on the PCVision frame grabber.) Table A–1.

  • Page 178: Table A-2. 26-Pin Connector

    Video Connections 26-Pin D-Sub The 26-pin D-Sub connector supports one camera, and provides additional signals for trigger, strobe and I/O. The PCVisionplus can supply up to 1A at 12V from chassis power. Table A–2. 26-Pin Connector Pin # Signal name...
  • Page 179 8 output, high-drive TTL channels. This port allows controlling or monitoring external events. The pin-out is OPTO22 compatible. All even numbered pins are connected to Digital Ground. A jumper labeled “I/O Level” on the PCVisionplus board sets the power-up state of the parallel port outputs. Refer to Figure A–1.

  • Page 180: Table A-4. Break-Out Cables For Pcvisionplus

    Break-out cables plug into the 15-pin and 26-pin D-Sub connectors, and split their signals into more connectors. Adapter cables plug into the camera, and connect to either a break-out cable or directly into the PCVisionplus board 15-pin connector. Break-Out Cables The following break-out cables are available for camera interfacing CAM1.

  • Page 181: Table A-5. Breakout Cable 509-00066-00 Pin-Out

    Video Connections 402-00005-00 Table A–5. Breakout Cable 509-00066-00 Pin-out PCVisionplus CAM1 15-pin Signal Description 26-pin Male Video input 1 CAM1 Clock Input 1 CLKIN_1 Digital Ground DGND 3,24 Analog Ground AGND Frame Reset 1 FRESET1 12 Volts return +12V_Ret Horizontal Sync 1 HSYNC1...

  • Page 182: Figure A-2. Pcvisionplus Breakout Cable

    PCVisionplus Hardware Reference Video Connections 1 ft. CAM1 15 pins PCVisionplus 26 pins MISC 26 pins 509-00066-00 Figure A–2. PCVisionplus Breakout Cable 6 ft. MISC_IN1 MISC_OUT1 STROBE0 STROBE1 MISC_IN0 MISC_OUT0 PCVisionplus TTL_TRIG0 26 pins TTL_TRIG1 509-00065-00 OPTO_IN1+ OPTO_IN1– OPTO_IN0+ OPTO_IN0–...

  • Page 183: Table A-6. Miscellaneous Cable 509-00065-00 Pin-Out

    Video Connections 402-00005-00 Table A–6. Miscellaneous Cable 509-00065-00 Pin-out PCVisionplus BNC Label Signal Description 26-pin Male MISC_IN1 Miscellaneous Input 1 Misc_IO_In1 MISC_OUT1 Miscellaneous Output 1 Misc_IO_Out1 STROBE0 Strobe Output 0 Strobe_0 STROBE1 Strobe Output 1 Strobe_1 MISC_IN0 Miscellaneous Input 0 Misc_IO_In0...
  • Page 184 Video Connections Camera Adapter Cables The camera adapter cables plug into the 15-pin D-Sub connectors on the PCVisionplus or on the break-out cables, and have camera connectors at the other end. This appendix covers some of the cables available. Other adapter cablesmay be available;...
  • Page 185 The clock input has no connection when used with the break out cables BCBL-PCV1 and BCBL- PCV2. The clock input is supported when plugged directly into the 15-pin connnector on the PCVisionplus board, or the 509-00066-00 cable. A–10 Rev 02; February 8, 2002...
  • Page 186 PCVisionplus Hardware Reference Video Connections Hirose (JIT) 2 This camera is compatible with the Pulnix TM Series analog monochrome cameras. The order code for this cable is ACBL-HIR2. Table A–9 gives the pin-out, and Figure A–6 illustrates this cable. Table A–9. ACBL-HIR2 Cable Pin-Out...
  • Page 187 The CVBM10–6 cable before revision I/P2, is not compatible with the 15-pin connector on the PCVisionplus or PCVision. The earlier revision cable should only be used with a break-out cable, and not be plugged directly into the 15-pin connector on the frame grabber.
  • Page 188 Variable Scan mode. The order code for this cable is ACBL–VSCAN. Table A–11 gives the pin-out, and Figure A–8 illustrates this cable. The PCVisionplus must be programmed to input the Clock on the Frame Reset pin.
  • Page 189 Video Connections 402-00005-00 A–14 Rev 02; February 8, 2002 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 190: Figure B-1. Basic Opto-Isolator

    – Figure B–1. Basic Opto-Isolator The PCVisionplus uses the HPCL-0631 for its opto-isolatoed trigger input. Chapter 1 lists the recommended operat- ing current and voltage values. Do not exceed the absolute maximum ratings of the diode in these devices. • Diode Absolute Maximum Ratings (no derating up to 85° C)

  • Page 191: Figure B-2. Opto-Coupled Input Circuit

    Using Opto-Isolators 402-00005-00 Input Circuits Internal to PCVisionplus Vcc or PWR 2.2 K ohm + input Value – input trigger Figure B–2. Opto-Coupled Input Circuit Figure B–2 shows the internal circuitry in the opto-coupled input. When the diode is excited, the transistor is on, and the internal Value is zero.

  • Page 192: Figure B-3. Input To Opto-Coupled Circuit

    PCVisionplus Hardware Reference Using Opto-Isolators Connecting to a Current Sinking Output +V dc TTL Output 2.2 K ohm 2.2 K ohm Value Value 1 K ohm trigger trigger 330 ohm 1/8 Watt Output Connecting to a Vcc or PWR Current Sourcing Output...

  • Page 193: Figure B-4. Opto-Coupled Output Circuit

    The PCVisionplus does not incorporate opto-isolators, the outputs are TTL and CMOS logic. The positive side of the LED (light emitting diode) is connected to the logic output of the PCVisionplus. The optional 1K ohm resistor limits the voltage across the diode. The negative side of the LED is connected to ground. The optional 330 ohm 1/8 Watt resistor to limits current through the diode.
  • Page 194 PCVisionplus Hardware Reference INDEX reference voltage DACs, 4–2 ADD, add 1 VCO cycle, PLL, 4–10 absolute maximum ratings, opto–isolators, B–1 address AC coupled, 2–14 DMASTART, DMA start address, 3–71 ILUTSADR, input LUT static address, 3–48 ACQADR, acquire address (status) register, 3–78 ADR, start address, OCT, 3–79...
  • Page 195 Index 402-00005-00 BM_ON. See BMEN BMBYTESEL, bus master byte select, 3–69 cables, A–5 adapter, A–9 BMCS, bus master host control/status, 3–21 break–out, A–5 BMCTLX, bus master control register, 3–68 cache, line size, CALN, 3–11 BMDONE, bus master transfer done, 3–22 CALN, cache line size, 3–11 camera, power, 1–7 BMDST, bus master destination address status, 3–18...
  • Page 196 PCVisionplus Hardware Reference Index conventions, iv DMA Table, segment size register, SGSZ, 3–74 DMA table count (scatter gather table), 2–8 FCNT, frame count, 3–65 specification, 1–5 timer register, TIMERCNT, 3–57 DMASTART, DMA start address, 3–71 counter source, CNTENSRC, clamping counter enable, 3–55 done, bus master transfer, BMDONE, 3–22...
  • Page 197 Index 402-00005-00 examples FLDSEL programming PLL mode, 4–14 field source select, 3–47 start field select, 3–65 programming XTAL mode, 4–18 FLDSHFT, field shift mode, cropping 1/2 lines, 3–47 external trigger, operation, 2–34 format, INMODE, input data format, 3–67 EXTREF, PLL external reference select, 4–13 formatting, data output, 2–8 EXTRIGSTAT0, TTL trigger 0 status, 3–36, 3–37 FPGA...
  • Page 198 PCVisionplus Hardware Reference Index grab, ACQMD, acquire command, 3–65 input clamping, DC restoration, 2–16 input conditioning, 2–14 GSTAT, grab status, 3–66 input gain, 2–14 input LUT, 2–18 HACT, horizontal active, 3–34 input MUX, 2–14 input resistance, 2–14 hardware switches, variable scan signals, 2–24 input select, VIDEOINSEL, 3–45...
  • Page 199 Index 402-00005-00 AMINTEN, AM interrupt, 3–78 LUT programming, 3–61 BMINTEN, bus master complete interrupt, 3–77 PCI bus, INTEN, 3–19 interrupts, PCI–bus, 2–3 MAINT, master abort interrupt status, 3–20 INTFLT, PLL loop filter select, 4–9 mapping AM control registers, BADR2, 3–13 INTLN, interrupt line, 3–15 board ID registers, BADR1, 3–13 INTPIN, interrupt pin, 3–16...
  • Page 200 PCVisionplus Hardware Reference Index offset, frame reset, FROFF, 3–42 PCI configuration registers, 3–6 PCI interface control registers, 2–3 OMUX1, PLL output 1 select, 4–12 PCI–bus operating temperature, specification, 1–7 interface, overview, 1–1 opto–isolators, B–1 interrupts, 2–3 OPTOSTAT0, opto–coupled trigger 0 input status, 3–37 PCIBMEN, bus master enable, 3–8...
  • Page 201 Index 402-00005-00 PLLA2, PLL register 2, 4–7 PTGV1, PTG vertical timing register, 3–29 PTGV2, PTG vertical timing register, 3–31 PLLA4, PLL register 4, 4–8 PLLA5, PLL register 5, 4–10 in PLL mode, 2–29 PLLA6, PLL register 6, 4–12 programmable window generator, 2–29 variable scan mode, 2–31 PLLA7, PLL register 7, 4–13 XTAL mode, 2–31...
  • Page 202 PCVisionplus Hardware Reference Index DID, device ID, 3–6 registers DPDATA, scatter gather table, 3–81 acquisition control, 2–3 frame buffer control, 2–3, 3–63 HDR, header type, 3–12 INCON1, input control, 3–38 general control, 2–3 host access, 2–2 INCON2, input control, 3–44 PCI configuration, 2–2...
  • Page 203 REV, module/hardware revision, 3–24 specifications SOTINT environmental, temperature, humidity, power, size, 1–7 end of trigger interrupt, 3–49 PCVisionPlus, 1–2 start of trigger interrupt, 3–49 SSERR, signaled system error, 3–10 strobe input (STROBE_I), STRTINSTAT, 3–59 target abort interrupt, TAINT, 3–20 STABT, signaled target abort, 3–9 timer interrupt, TCNTINSTAT, 3–50...
  • Page 204 PCVisionplus Hardware Reference Index polarity timing input, specification, 1–2 INTB_POL, parallel port, 3–59 timing output, specification, 1–4 STRBPOL, 3–40 transfer count strobe lights, 2–34 status, BMXC, 3–18 XCNT, OCT, 3–80 STROBE_I, input state, STRBINSTAT, 3–59 TRGCYC, trigger cycle status, 3–40 STRPINSEL, sync stripper input select, 3–46...
  • Page 205 Index 402-00005-00 VBEVENINTSTAT, vertical blank even field interrupt status, 3–50 Vsync, output frame reset on Vsync output, FRSTONV, 3–42 VBLANKINTEN, vertical blank interrupt enable, 3–52 VSYNCEN, vertical sync output enable, 3–47 VBLANKINTSTAT, vertical blank interrupt status, 3–50 VBODDINTEN, vertical blank odd field interrupt enable, 3–52 VSYNCPOL, vertical sync polarity, 3–30 VBODDINTSTAT, vertical blank odd field interrupt status, 3–50 VCLKPOL, variable scan clock input polarity, 3–46...

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