Centrality Atlas USB Chip Utilites Manuals

Manuals and User Guides for Centrality Atlas USB Chip Utilites. We have 1 Centrality Atlas USB Chip Utilites manual available for free PDF download: Programming Manual

Centrality Atlas Programming Manual

Centrality Atlas Programming Manual (181 pages)

Brand: Centrality | Category: Computer Hardware | Size: 0.84 MB

Table of Contents

Table of Contents
2
1 Introduction

8
- Documentation Conventions
  8
- Referenced Documents
  9
- Architectural Overview
  10
- Figure 1. Atlas™ Block Diagram
  10
- Key Features
  12
2 RISC Subsystem

13
- Operation Overview
  13
- RISC Address Mapping
  13
- Boot-Up Control
  15
- Wait State Control
  16
- Write Pulse Control
  17
- Timeout Control
  18
3 DSP Subsystem

19
- Operation Overview
  19
- DSP Memory Address Mapping
  20
- DMA Operation
  21
  - Setting Memory Status
    21
  - Starting DMA Transfer
    21
  - Endian Mode for DMA
    22
  - Byte Select Mode
    22
  - Figure 2. DSP Byte Select Mode
    23
- Controlling Peripherals
  24
- DSP and RISC Cooperation
  25
  - RISC Control DSP by Interrupt
    25
  - Data Exchange between the RISC and the DSP
    27
- Differences between the DSP and Adi's ADSP2181
  28
  - Memory
    28
  - Instructions
    28
  - Biased-Rounding Mode
    28
  - Non-Memory Mapped Registers
    28
  - Memory Mapped Registers
    28
  - Critical Path Limitation
    28
4 Dynamic Memory Interface

30
- Operation Overview
  30
- Pin Sharing
  31
- Normal Operation
  32
- Wake-Up Operation
  34
- Clock Switching Operation
  35
- Self-Refresh Mode
  36
5 Static Memory Interface

37
6 Clocks and Power Manager

48
- Operation Overview
  48
- Change Clock Source
  49
- Change Clock Ratio
  50
  - Change the System and I/O Clock Ratio
    50
  - Change the External Memory Clock Ratio
    50
- Change PLL Frequency
  52
- Power Mode
  53
  - Normal Mode
    53
  - Turbo Mode
    53
  - Idle Mode
    53
  - Standby Mode
    54
  - Sleep Mode
    54
7 Gpio

56
- Operation Overview
  56
- Configure GPIO Pin Sharing
  57
- Configure GPIO as Input
  58
- Configure GPIO as Output
  59
- Configure GPIO as Open-Drain
  60
- Configure GPIO as Wake-Up Source
  61
- Configure GPIO to be Accessed by DSP
  62
8 Resource Sharing Controller

63
- Operation Overview
  63
- DMA Channel Sharing
  64
- External Pin Multiplex
  65
- Figure 8. Atlas™ Pin Multiplex Diagram
  65
9 DMA Controller

67
- Operation Overview
  67
- Initialization
  68
- DMA Interrupt Handling
  70
- Single and Burst DMA
  71
- 1-D and 2-D DMA
  72
- Figure 9. 2-D DMA
  72
- Figure 10. 2-D DMA Wrap Around (X-Length > Width)
  73
- Loop DMA
  74
- Figure 11. Loop-Mode DMA
  74
- DSP Control of DMA
  77
10 PCMCIA Interface

78
- Operation Overview
  78
- Pin-Mux Programming
  79
- M6730 Register Programming
  80
- Power Logic Register Programming
  82
- Memory Window Configuration
  83
- I/O Window Configuration
  84
- Timing Control
  85
- Management Interrupt Operation
  85
- Card Interrupt Operation
  87
- Socket Initialization Sequence
  88
11 Extension Port

89
- Operation Overview
  89
- Pin-Mux Programming
  90
- Timing Register Programming
  91
- Fixed Latency Access
  92
- Variable Latency Access
  93
- DSP Access
  94
12 Universal Serial Port

95
- Operation Overview
  95
- USP Reset and Power up
  96
- USP Initialization
  97
  - USP Work Mode Initialization
    97
  - Sample Code of USP Initialization
    100
- USP Transmitting Operation
  106
- USP Receiving Operation
  108
  - I/O Mode Receiving by Interrupt
    108
  - I/O Mode Receiving by Polling FIFO Status
    108
  - DMA Recieving Mode
    109
- Interralation of Transmitting and Receiving
  110
- Pin I/O Mode Operations
  110
- USP Reconfiguration
  112
- SIB Initialization
  113
- SIB Operations
  115
  - Register Writing
    115
  - Register Reading
    115
  - Audio Data Transfer
    115
  - Telecom Data Transfer
    116
13 Audio CODEC Interface

117
- Operation Overview
  117
- Audiocodec Controller Initialization
  118
- AC'97 CODEC Configuration
  119
- I2S CODEC Configuration
  123
14 Camera Interface

125
- Operation Overview
  125
- Initialize Operations
  126
  - Initialize Camera Interface
    126
  - Camera Interrupt Operation
    126
- DMA Operations
  128
  - Initialize DMA Interface
    128
  - DMA Interrupt Operation
    128
  - DMA Operation
    129
- Sensor Operations
  130
  - Initialize Sensor Control Module
    130
  - Sensor Clock Operation
    130
  - Capture Image Operation
    130
  - Slave Mode Operation
    131
  - Pixel Data Shift Operation
    132
  - Inverse Control Operation
    133
  - Sample Pixel Clock Operation
    133
  - Master Mode Operation
    134
- I2C Master Operations
  136
  - Initialize Unit
    136
  - Write N Bytes to External Device
    136
  - Read N Bytes from External Device
    137
- I2C Slave Operations
  138
  - Initialize Unit
    138
  - Normal Operation
    138
- Quick Reference
  139
15 USB 1.1 Device Interface

140
- Operation Overview
  140
- Initialization
  142
- Control Transfer
  144
- I/O Operation
  146
- DMA Operation
  148
- Quick Reference
  150
16 Host Port Interface

151
- Operation Overview
  151
- Address Mapping
  152
- Initialization
  153
- I/O & DMA Operation
  156
- Handshaking with Host
  158
17 Secure Disk (SD) / Multi-Media Card Interface (MMC)

159
- Operation Overview
  159
- Internal Regsiter Programming
  160
- I/O Operation
  161
- DMA Operation
  162
- Initialization
  163
- No Data Command/Response Transaction
  164
- Single Block Operation
  165
  - Single Block Write
    165
  - Single Block Read
    165
- Multiple Block Operation
  166
  - Multiple Block Write
    166
  - Multiple Block Read
    166
  - Multiple Block Write Using Number Blocks
    167
  - Multiple Block Read Using Number Blocks
    167
18 Nand Flash Memory Interface

168
- Operation Overview
  168
- Initialization
  168
- I/O Operation
  168
  - IO Read
    168
  - IO Write
    169
- DMA Operation
  169
- DMA Read Example
  170
- DMA Write Example
  170
- NAND Boot-Loader
  171
  - ARM Init Process
    172
  - Figure 12. NAND Boot Flow Diagram
    172
  - Flash Controller's Global Register Init Process
    173
  - Read Device ID
    173
  - Search File "NK.BIN
    173
  - Read "NK.BIN" and Parse It
    173
- Special Notes
  174
19 LCD Controller Interface

175
- Operation Overview
  175
- Initialization
  175
- DMA Operation
  177
- Configuration Comparison for Different Mode
  178
- Palette
  179
  - Color Palette
    179
  - Grey Palette of FRC Sequence
    179
- Special Register Configuration
  180
  - Pixel Clock Divider
    180
  - FIFO Request Watermark Control
    180
- Power Sequence / Back Light Control for LCD Displays
  180
20 Revision History

181

Advertisement

Advertisement

Related Products

Centrality Categories

IP Phone Computer Hardware Gateway

More Centrality Manuals