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Centrality Atlas Programming Manual

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© 1999-2003 Centrality Commnications, Inc.
2520 Mission College Blvd. Suite #103, Santa Clara, CA 95054
Atlas™
Programming Guide
Preliminary Revision 0.6, April 2003

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Summary of Contents for Centrality Atlas

  • Page 1 Atlas™ Programming Guide Preliminary Revision 0.6, April 2003 © 1999-2003 Centrality Commnications, Inc. 2520 Mission College Blvd. Suite #103, Santa Clara, CA 95054...

  • Page 2: Table Of Contents

    Change the System and I/O Clock Ratio ................49 6.3.2 Change the External Memory Clock Ratio ................49 Change PLL Frequency......................51 Power Mode ..........................52 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 1 -...
  • Page 3 I/O Mode Transmit by Polling FIFO Status ............... 105 12.4.3 DMA Transmitting Mode....................105 12.5 USP Receiving Operation ..................... 107 12.5.1 I/O Mode Receiving by Interrupt ..................107 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 2 -...
  • Page 4 I/O Operation ........................145 15.5 DMA Operation ........................147 15.6 Quick Reference ........................149 Host Port Interface ...........................150 16.1 Operation Overview ......................150 16.2 Address Mapping ........................151 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 3 -...
  • Page 5 Pixel Clock Divider ......................179 19.6.2 FIFO Request Watermark Control ..................179 19.7 Power Sequence / Back Light Control for LCD Displays............179 Revision History ..........................180 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 4 -...
  • Page 6 **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE List of Figures Figure 1. Atlas™ Block Diagram ......................9 Figure 2. DSP Byte Select Mode......................22 Figure 3. Data Mapping in 8-bit External Data Bus ................37 Figure 4. Data Mapping in 16-bit External Data Bus ................37 Figure 5.
  • Page 7 Table 6. Staitic Memory Chip Select Mapping..................36 Table 7. Staitic Memory Chip Select Mapping..................39 Table 8. Atlas™ DMA Channel Multiplex....................63 Table 9. Atlas™ Pin Multiplex ....................... 64 Table 10. Pixel Shift Number vs DMA Register Setting ..............138 Table 11.

  • Page 8: Introduction

    This document detailed descriptions and examples of programming and developing using the Centrality Communications’ Atlas™ Processor. It is intended for the use of Centrality customers, partners, and other interested parties to gain a detailed understanding of Centrality’s technology and architecture for design purposes.

  • Page 9: Referenced Documents

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 1.2 Referenced Documents The following documents can be obtained from Centrality Communications to enhance the supplement of the Atlas™ Processor. Table 1. Reference Documents File Name Description ARM922T.PDF ARM922T processor core technical reference manual.

  • Page 10: Architectural Overview

    • RISC Core Atlas™ has an integrated ARM922T core with the AMBA ASB bus. The RISC acts as a controller, which controls the other functional blocks via writing/reading memory-mapped registers. The RISC accesses external memory via the memory bus and acts as a bus master.
  • Page 11 All of these interface blocks have the same functionality: they each provide a means to transfer data between Atlas™ and an external device. There are two types of transfer: I/O read/write and DMA. Some blocks only support I/O read/write, such as the Bluetooth and GPS blocks. Some blocks support both I/O read/write and DMA, such as the serial port, CMOS sensor, NAND Flash/Smartmedia, Flash/ROM, SD/MMC and USB interface.

  • Page 12: Key Features

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 1.4 Key Features Unlike other application processors on the market today, the Atlas™ processor provides the following key features integrated on-chip. 240MHz ARM922T RISC core 8KB I-Cache 8KB D-Cache Memory Management Unit...

  • Page 13: Risc Subsystem

    The RISC Subsystem includes an ARM922T RISC core (with 8KB I-Cache and 8KB D-Cache) and a RISC interface. The RISC interface can translate the ARM922T bus cycles into Atlas™ internal system bus cycles. There are two types of basic bus cycle of ARM922T: I/O cycle and Memory cycle. It’s decided by the address to define if a RISC bus cycle is I/O or Memory cycle.
  • Page 14 Internal Registers 5000_0000~7FFF_FFFF Reserved 768MB 4800_0000~4FFF_FFFF 128MB DSP Shared Memory 4000_0000~47FF_FFFF Extension Port 128MB 3000_0000~3FFF_FFFF PCMCIA Socket 1 256MB 2000_0000~2FFF_FFFF PCMCIA Socket 0 256MB 0000_0000~1FFF_FFFF Flash/ROM 512MB Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 13 -...

  • Page 15: Boot-Up Control

    Due to the pipeline nature of the RISC core, after the Boot-up register been set, user CANNOT access the ROM address space at once. It needs to insert at least one NOP between them. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 16: Wait State Control

    2.4 Wait State Control Most peripherals in Atlas™ are in I/O clock domain (please refer to the section 6 “Clocks and Power Manager”), while the RISC Subsystem is running at a higher system clock domain. So there is need for inserting wait states when the RISC read those slow I/O devices.

  • Page 17: Write Pulse Control

    RISCINT_WIDTH = 0x10; • When I/O clock is ¼ of the system clock domain, the write enable pulse should be 4 system clock cycles: RISCINT_WIDTH = 0x30; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 16 -...

  • Page 18: Timeout Control

    When Timeout check is enabled and the device response is longer than the Timeout value, the RISC interface will generate an interrupt to the CPU in RISCINT_TIMEOUT_INT register. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 17 -...

  • Page 19: Dsp Subsystem

    3 DSP Subsystem 3.1 Operation Overview The DSP used in Atlas™ processor acts as a acceleration computational parts for GPS, MP3, Image processing etc. The DSP core is provided by Faraday Technology Corp. and is instruction compatible with ADI’s ADSP2181 except for minor differences.

  • Page 20: Dsp Memory Address Mapping

    DSP/SDRAM DMY (GPS baseband) 0x3000 (PM) 3072 DSP only PM-in 0x0000 (PM) 1024 DSP only PM-swap (single) 0x0400 (PM) 1024 DSP/SDRAM PM-swap (double) 0x0400 (PM) DSP/SDRAM Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 19 -...

  • Page 21: Dma Operation

    DSP, for PM, address offset is the same seen by DSP. Address offset is from the beginning of the buffer, so address offset 0 in DMX-swap means address 0x400, address offset 1 means address 0x402 etc. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 20 -...

  • Page 22: Endian Mode For Dma

    It has a limitation that DSP has to load data from four-byte boundary. By set BYTE_MODE bit to 1 in register DSP_BYTE_MODE, byte select mode is enabled. Byte select mode use Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 23: Figure 2. Dsp Byte Select Mode

    SDRAM, the first transfer passes the end of buffer and the second transfer concatenate the first one from the beginning of the buffer), the second DMA should not discard the first read in data and data in storage registers. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 22 -...

  • Page 24: Controlling Peripherals

    Peripheral can interrupt the DSP, the interrupt are connected to the DSP’s IRQ2 input and can be set to either level trigger or edge trigger. For details of how to operate each peripheral, refer to the programming guide of corresponding peripheral. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 23 -...

  • Page 25: Dsp And Risc Cooperation

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 3.5 DSP and RISC Cooperation The DSP acts as an independent unit in the Atlas™ processor. It runs parallel with the RISC. Some communication methods are available between the DSP and the RISC. The DSP and the RISC can interrupt each other.
  • Page 26 = 0; dm(GEN_REG2_L) = ar; dis sec_reg; rti; Subroutine: /* execute program */ /* when completed return by executing the following sentence */ jump return_addr; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 25 -...

  • Page 27: Data Exchange Between The Risc And The Dsp

    DSP and do a few WORDs of data exchange when the DSP is running. When large amount of data need to be exchanged between the RISC and the DSP, use the DSP’s DMA function Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 28: Differences Between The Dsp And Adi's Adsp2181

    The address and meaning of memory mapped registers are totally different from ADSP2181. The description of those registers are listed in “F2016 16-bit DSP Microcomputer specification” and other Atlas™ specified registers are listed in “Atlas™ Developer’s Manual” 3.6.6 Critical path limitation There is critical path in the DSP on following instruction combination: I register read from data memory followed by a data memory access using this I register.
  • Page 29 The existing of critical path limites program with such instruction combination can not run over 120MHz. Programmer should eleminate critical path instructions by inserting NOP or changing instruction sequence. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 28 -...

  • Page 30: Dynamic Memory Interface

    4 Dynamic Memory Interface 4.1 Operation Overview Atlas™ supports the SDRAM interface at a maximum frequency of 100 MHz. The SDRAM Interface supports up to four groups of SDRAMs. All the SDRAMs used should be of the same type, operate at the same clock frequency and voltage.

  • Page 31: Pin Sharing

    The following sample code is used to enable the SDRAM controller’s control over these pins. RSC_PIN_MUX |= 0x1e0; //use MCKE<2:3>,MCS_B<2:3> as SDRAM pins PWR_PIN_RELEASE = 1; //release power manage pin holding //Configure system clock; … //Configure SDRAM; … Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 30 -...

  • Page 32: Normal Operation

    MEMC_CONFIG<8> = 1 2) MEMC_CONFIG<9> should be written as 1 3) All other register are for test purpose and should be written as 0 For MEMC_SDCFG Register: Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 31 -...
  • Page 33 If program is booting on static memory interface or NAND flash, the SDRAM can be configured as following. The MEMC_POWER register needs to be programmed to initialize SDRAM. //Configure System clock. … MEMC_SDTIM=0xB85D7222; MEMC_CONFIG=0x200; MEMC_SDCFG=0xc; MEMC_POWER=0x4F; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 32 -...

  • Page 34: Wake-Up Operation

    For the example used previously, the SDRAM should be initialized like following: //Configure System clock. … MEMC_SDTIM=0xB85D7222; MEMC_CONFIG=0x200; MEMC_SDCFG=0xc; PWR_SLEEP_STATUS = 0x8; // clear SDRAM_HOLD bit if wakeup from sleep mode MEMC_POWER=0x4F; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 33 -...

  • Page 35: Clock Switching Operation

    //Change other timing value in MEMC_SDTIM for performance only. … //Change other timing value in MEMC_SDTIM to fit the new system clock. … //Switch clock to new system clock … Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 34 -...

  • Page 36: Self-Refresh Mode

    In the previous sample code there are 4 chip-select signals being used. But even if there are only 1, 2 or 3 chip-select signals being used, the code can still be used. The unused chip-select will not affect anything if they are programmed to be GPIO. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 35 -...

  • Page 37: Static Memory Interface

    Memory Interface. The following table shows the mapping from different internal address to different chip selects. Table 6. Staitic Memory Chip Select Mapping Chip select 0 0x1000_0000~ 0x13FF_FFFF Chip select 1 0x1400_0000 ~ 0x17FF_FFFF Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 36 -...

  • Page 38: Figure 3. Data Mapping In 8-Bit External Data Bus

    External Data Bus (16-bit) Figure 4. Data Mapping in 16-bit External Data Bus In Instruction Access Mode any write command from RISC is ignored by the Static Memory Interface. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 37 -...

  • Page 39: Direct Access Mode

    FlashData = (*((volatile unsigned short *)(0x18000000 + FlashAddress))); // Perform a direct write to offset 0x01 in chip select 1 (*((volatile unsigned short *)(0x18000000 + FlashAddress)))= FlashData ; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 38 -...

  • Page 40: Dma Access Mode

    DMA_CH4_CTRL = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_TO_SDRAM); DMA_CH4_ADDR = (0x200000); //DMA start address in SDRAM //configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 39 -...

  • Page 41: Dma Write

    User should program ROM_WRITE_CTRL with • TWC= actual write cycle time; • NWC= 1; • ADINT=0; • NSEQ=0; The Interface timing diagram is should in the following figure. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 40 -...

  • Page 42: Figure 5. Static Memory Interface Simple Writetiming

    ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory , no flush ROM_FIFO_CTRL_REG=0x00; ROM_FIFO_LEVEL_CHK_REG=(0xb);//fifo level check //twc is the actually write cycyle time, user needs to change the vaule to //fit the actual system twc=0xff; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 41 -...
  • Page 43 ROM_WRITE_SEQ1 with data stored in ROM_WRITE_SEQ1. The last write operation write to current address stored in ROM_START_ADDR with data from FIFO. The address in ROM_START_ADD will increase automatically according to different Interface width. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 42 -...

  • Page 44: Figure 6. Static Memory Interface Fixed Sequence Writetiming

    ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; ROM_DMA_IO_LEN_REG = 32*2; //16 bit width, Transfer 32 DWORD ROM_START_ADD = = 0x2000000; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory , no flush Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 43 -...
  • Page 45 The Third write operation will read one 32-bit from FIFO, only LSB 28-bit are used as write address. After that it will read another 32-bit from FIFO, only LSB 16/8-bit(depending on interface width) are used as write data. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 44 -...

  • Page 46: Figure 7. Static Memory Interface Fixed Sequence Writetiming

    //16 bit width, Transfer 32 DWORD, both data and address are get from FIFO ROM_DMA_IO_LEN_REG = 32*2*2; ROM_START_ADD = = 0x2000000; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory, no flush ROM_FIFO_CTRL_REG=0x00; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 45 -...
  • Page 47 //twc is the actually write cycyle time, user needs to change the vaule to //fit the actual system twc=0xff; ROM_WRITE_CTRL= (((0)&(0x3))<<12 | ((1)&(0x1))<<11 | ((3)&(0x7))<<8 | (twc)&(0xff)); //start dma ROM_FIFO_OP_REG=0x1; //waiting for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 ); Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 46 -...

  • Page 48: Clocks And Power Manager

    Domain. The reason is that the CPU has two clock inputs: one for core clock and the other for bus clock. The bus clock is always the same as Atlas™ system clock (i.e. in System Clock Domain); the core clock is in CPU Clock Domain.

  • Page 49: Change Clock Source

    6.2 Change Clock Source The Atlas™ system can be programmed to use either PLL1 or PLL2 as the clock source. In addition, it can also select the oscillator (12MHZ or 32.768KHz) outputs as the clock source. The switching of the clocks can take place in real-time while Atlas™...

  • Page 50: Change Clock Ratio

    MEMC_CFG = 0x300; for (i=1;i<=10;i++); ARM922T has three different clocking modes: Fast Bus mode, Synchronous mode, and Asynchronous mode. Please refer to the ARM922T datasheet for more details. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 49 -...
  • Page 51 NOTE: To change the external memory clock ratio must be done when program is running either on Flash/ROM or in Instruction Cache. Otherwise, unexpected result may happen. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 50 -...

  • Page 52: Change Pll Frequency

    NOTE: Due to the PLL limitation, the output frequency has to be the multiple of 6 MHz (half of the 12 MHz Crystal input). Or, in another words, the pre-divider (MS<5:0>) has to be set to 1 or 2. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 53: Power Mode

    6.5.1 Normal Mode Normal mode is the normal operating mode of the Atlas™: all power supplies are enabled, all clocks are running, and every on-chip resource is functional. And the CPU runs at the same clock rate as the other part of the system (except for the I/O peripherals).

  • Page 54: Standby Mode

    PWR_EN pin indicating to the external system that the Atlas™ is in sleep mode. Running off the 32.768 kHz Oscillator, the sleep state machine watches for a preprogrammed wake-up event to occur, after which it asserts PWR_EN pin, and steps through an orderly wake-up sequence.
  • Page 55 While the hardware sleep is for another usage: when the system battery or power source is fail to provide enough current to Atlas™, the Atlas™ will go to sleep mode automatically to save the power consumption. This is done by the BATT_FAULT or VDD_FAULT pin. The power-down sequence is almost the same as the software sleep, except user does not need to set the force sleep bit in PWR_CTRL register.

  • Page 56: Gpio

    7 GPIO 7.1 Operation Overview The Generous Purpose Input Output (GPIO) logic of the Atlas™ processor controls 28 pins through the use of 16 registers which control the pin direction (input or output) pin function, pin state (outputs only), pin level detection (inputs only).

  • Page 57: Configure Gpio Pin Sharing

    =2’b10 on reset). Otherwise those pins are used as GPIO pins. • GPIO<15:8> are shared with the LCD Controller. RSC_PIN_MUX &= 0xfffffffe; //use LDD<8:15> as GPIO<8:15> PWR_PIN_RELEASE = 1; //release power manage pin holding Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 56 -...

  • Page 58: Configure Gpio As Input

    GPIO_INT_EN |= 0X01; //enable GPIO interrupt on gpio0 To get the current value of GPIO0, user can access register GPIO_DATA_IN: value = GPIO_DATA_IN & 0x01; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 57 -...

  • Page 59: Configure Gpio As Output

    GPIO_OUT_EN |= 0x01; //configure GPIO0 as output If GPIO0 is already set as output, user only need to change GPIO_DATA_OUT to desired value. GPIO_DATA_OUT |= 0x01; //set GPIO0 output value as 1 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 58 -...

  • Page 60: Configure Gpio As Open-Drain

    GPIO_INT_LT &= 0xfffffffe; //disable falling-edge on GPIO0 to generate interrupt. GPIO_INT_STATUS &= 0x01; //clear GPIO0 interrupt before enable the interrupt GPIO_INT_EN |= 0X01; //enable GPIO interrupt on gpio0 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 59 -...

  • Page 61: Configure Gpio As Wake-Up Source

    GPIO in sleep mode. In sleep mode the pin sharing of GPIO is not needed, all the pin are controlled by GPIO. The following codes set all the GPIO as input in sleep mode, use GPIO0 high to wake-up the Atlas™. GPIO_SL_VAL=0x0;...

  • Page 62: Configure Gpio To Be Accessed By Dsp

    GPIO except for this one. RISC needs to clear this register before it needs to access the corresponding GPIO. GPIO_DSP_EN |= 0x01; // set GPIO0 to be controlled by DSP Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 61 -...

  • Page 63: Resource Sharing Controller

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 8 Resource Sharing Controller 8.1 Operation Overview The Resource Sharing Controller (RSC) manages the two major resources of Atlas™: one is the peripheral pin; the other is the DMA channel. Atlas™ Programming Guide...

  • Page 64: Dma Channel Sharing

    The DMA channel 6, 7 & 9, 10 are shared between the four Universal Serial Ports and the Audio CODEC. The following table shows the DMA channel multiplex managed by RSC: Table 8. Atlas™ DMA Channel Multiplex USP0 USP1 USP2...

  • Page 65: External Pin Multiplex

    User can switch the pins to the second (or third) function by configuring the RSC register RSC_PIN_MUX. The Atlas™ multiplexed pins managed by the RSC are shown in the next table (the memory interface pin multiplex is not managed by RSC): Table 9.
  • Page 66 , JTAG, or Scan chain test besides of the functions listed above. Among those functions, the TIC/BIST, JTAG, or Scan chain has the highest priority. When Atlas™ is configured to those special test modes, those pins cannot be used by the normal functions any more.

  • Page 67: Dma Controller

    Normally DMA has a start address and length. When the specified number of data is transferred, the DMA will stop. But there are some applications need to transfer data to a specified memory area repeatedly without stop (like Audio). So Atlas™ DMA Controller has a special loop mode for this type of applications.

  • Page 68: Initialization

    Besides of the above register set up, user also needs to set up some peripheral FIFO parameters such Some of these registers have defaults values that can already be used. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...
  • Page 69 DMA_CH4_CTRL = ((BURST<<3) | (DIR<<2) | WIDTH); DMA_CH4_XLEN = XLEN; DMA_CH4_YLEN = YLEN; DMA_CH4_ADDR = SDRAM_ADDR; Except for the loop mode (please refer to section 9.6) Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 68 -...

  • Page 70: Dma Interrupt Handling

    & 0x04) == DMA_MASK_FROM_SDRAM) bDMAReadDone = 1; The interrupt handling for loop mode DMA is a little bit different. Please refer to section 9.6 for the details. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 69 -...

  • Page 71: Single And Burst Dma

    (Because the system bus does not allow the non-aligned burst transfer) and the bus efficiency will be desperately low. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 72: 1-D And 2-D Dma

    9.5 1-D and 2-D DMA The Atlas™ DMA controller supports both 1-D and 2-D DMA. In 2-D DMA, the system memory space is considered as a 2-D layout instead of linear layout. In another word, the system memory is considered as many data lines.

  • Page 73: Figure 10. 2-D Dma Wrap Around (X-Length > Width)

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE DMA X-Length DMA Width Extra data Extra data Figure 10. 2-D DMA Wrap Around (X-Length > Width) Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 72 -...

  • Page 74: Loop Dma

    BUFA until the valid bit of BUFB is set. Here is a simple example showing the loop DMA from SDRAM to Flash Memory: //configure and start dma Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 73 -...
  • Page 75 // if in loop mode, swap the buffer valid DMA_CH_LOOP_CTRL &= 0xfff0fef; DMA_CH_LOOP_CTRL |= 0x100000; else if (DMA_CH_LOOP_CTRL & 0x100000) { DMA_CH_LOOP_CTRL &= 0xfef0fff; DMA_CH_LOOP_CTRL |= 0x10; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 74 -...
  • Page 76 To finish a loop DMA, user needs to write the DMA_CH_VALID register. For example, if user wants to stop the DMA channel 4 which is a loop-mode DMA: // stop loop mode DMA DMA_CH_VALID = 0x10; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 75 -...

  • Page 77: Dsp Control Of Dma

    DMA control registers need to be separated for RISC and DSP. Those registers include: • DMA Width Registers (DMA_WIDTH0, 1, 2, 3) • DMA Interrupt Enable Register (DMA_INT_EN) • DMA Loop Control Register (DMA_CH_LOOP_CTRL) Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 76 -...

  • Page 78: Pcmcia Interface

    Pin_mux programming M6730 Register programming Power logic register programming Memory window configuration I/O window configuration Timing control Management interrupt operation Card interrupt operation Card initialization sequence Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 77 -...

  • Page 79: Pin-Mux Programming

    PCMCIA interface. The pin_mux programming can access the following registers: 1. PWR_CLK_EN, see Atlas developer’s manual section 5.6.3 for details register description. Set bit 14 of PWR_CLK_EN to be 1’b1.

  • Page 80: M6730 Register Programming

    Extension registers. Within this Extension registers is an Extended Index register and Extended Data register that provides access to more registers. The registers accessed through extended index and data registers are thus double indexed. For M6730 its base address in Atlas is fixed to be 0x2000_0000, the address for index register in Atlas is 0x2000_0000, for data register it’s 0x2000_0001.
  • Page 81 *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned short)value_short; *((volatile unsigned char *) PCMCIA_IO_PHYSICAL_BASE ) = (unsigned char) 0x2F; value_short = *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE); register_data = (value_short & 0xFF00) >>8; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 80 -...

  • Page 82: Power Logic Register Programming

    GPIO or extended GPIO to control the power supply logic and switch the power on /off. After PCMCIA I/F detects the PC Card insertion, the power logic must be initialized before the other logic Since the auto power scheme in M6730 doesn’t work in Atlas PCMCIA interface, the power logic register programming should follow the steps below: 1.1 After the PCMCIA card insertion is detected, CPU reads External Data Register (extended index...

  • Page 83: Memory Window Configuration

    Address register, the address [23:12] is compared with Start Address Register and End Address Register, if the access address is within the range of programmed memory window, M6730 will respond to the RISC access. Also M6730 will convert the Atlas address into physical PC card address. The...

  • Page 84: I/O Window Configuration

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 10.6 I/O Window Configuration There are two I/O windows in PCMCIA interface. The PCMCIA I/O space in Atlas is 64K and ranges from 0x2000_0000 to 0x2400_0000. Before the Atlas PCMCIA I/O address reaches to M6730 megacell, the Atlas address 0x2xxx_xxxx is converted to M6730 I/O addresss 0x0xxx_xxxx.

  • Page 85: Timing Control

    If N is the programmed value in recovery timer register, T is PCMCIA I/F recovery PCMCIA internal clock period (PCMCIA I/F internal clock is always equal to Atlas I/O clock), the recovery time is: = 2* (N +1) * T recovery...
  • Page 86 Status Change register indicates the source of a management interrupt generated by the M6730. For the management interrupts to be generated, the corresponding enables should be set in the Management Interrupt Configuration register. So is the other management interrupt. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 85 -...

  • Page 87: Card Interrupt Operation

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 10.9 Card Interrupt Operation The Socket or Card interrupt is initiated by the I/O type PC card activating the rdy/nireq signal. In Atlas we assign IRQ9 for M6730 Card interrupt and only the external signaling mode is supported.The card interrupt is only valid for I/O type PC card.

  • Page 88: Socket Initialization Sequence

    4. Configure one memory window to be attribute memory window, the memory space is for external I/O device. 5. Select the timer for attribute memory window. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 87 -...

  • Page 89: Extension Port

    I/Odevice in fixed-latency or variable latency mode. But the DMA mode is realizeded through Atlas internal bus protocol, external glue logic is needed to implement the DMA data transfer. Here only the I/O mode operation is described. The pin of extension port is muxed with PCMCIA and host port.

  • Page 90: Pin-Mux Programming

    The pin_mux programming can access the following registers: PWR_CLK_EN, see Atlas developer’s manual section 5.6.3 for details register description. Set bit 14 of PWR_CLK_EN to be 1’b1.

  • Page 91: Timing Register Programming

    The setup register controls how many cycles there are from ext_sel_b assertion to control signals (ext_rd_b or ext_wt_b) assertion in terms of Atlas I/O clock. The recovery timers controls the clock cycles from control signal de-assertion to ext_sel_b (and address) de-assertion. The setup and recovery timer registers are valid for both fixed-latency and variable latency mode.

  • Page 92: Fixed Latency Access

    2. Configure EXT_RISC_CTRL register to enable EXT_EN, RISC_EN, set WAIT_MODE to be internal wait mode. EXT_RISC_CTRL = 0x3; 3. Programe EXT_TIMER1 and EXT_TIMER2 register according to external device AC specification. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 91 -...

  • Page 93: Variable Latency Access

    2. Configure EXT_RISC_CTRL register to enable EXT_EN, RISC_EN, set WAIT_MODE to be internal wait mode. EXT_RISC_CTRL = 0x13; 3. Programe EXT_TIMER2 register to set setup and recovery time according to external device AC specification. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 92 -...

  • Page 94: Dsp Access

    2. Configure EXT_DSP_CTRL register to enable EXT_EN, DSP_EN, set WAIT_MODE to be internal wait state. 3. If necessary, configure EXT_DSP_HI_ADDR to extend the high 8-bit address. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 93 -...

  • Page 95: Universal Serial Port

    In some application, USP must be configure to several kind of serial bus, so before the USP is used, it need to be reconfigured to the corresponding mode. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 94 -...

  • Page 96: Usp Reset And Power Up

    Before USP0 work, clear all pending interrupts USP0_INT_STATUS = USP_INT_MASK_ALL; If the DMA is used for data transferring, software must enable the DMA controller PWR_CLK_EN | = DMA_EN; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 95 -...

  • Page 97: Usp Initialization

    The USP initialization has something to do with the work mode of it. Before initializing the USP registers, please read the relative section in the Atlas™ Developers Manual to make sure how to describe the frame characteristics all the USP. The configuration procedure has been described in the Chapter 6.5.7 USP Frame Configuration detailedly.
  • Page 98 3. RX data delay length after RFS/TFS is valid or frame starts 4. RX data shifter length when receiving All the characteristics above are mapped to by the fowllowing register bits. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 97 -...
  • Page 99 Then you must set the FIFO_WIDTH bit in the (TX_FIFO/RX_FIFO) control register to decide exchange a byte/word/dowrd data with the FIFO. If the DMA mode is select, FIFO_WIDTH must be set to 0x2. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 98 -...

  • Page 100: Sample Code Of Usp Initialization

    TXD to USP function again. #define USP_LITTLE_ENDIAN 0x10 #define USP_TXD_AS_GPIO 0x10000 #define USP_TX_IO_MODE #define USP_RX_IO_MODE #define USP_ENABLE 0x20 // count the clock divider usp_baud_rate = (IO_CLOCK/8/baudrate + 1)/2-1; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 99 -...
  • Page 101 // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = (0x04 << 2); USP0_RXFIFO_CTRL = (0x0C << 2); … Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 100 -...
  • Page 102 #define USP_CLK_SLAVE_MODE #define USP_RX_SYNC_VALID_HIGH 0x100 #define USP_TX_SYNC_VALID_HIGH 0x200 #define USP_SCLK_IDLE_TOGGLE 0x400 #define USP_UFLOW_RPT_ZERO 0x80000000 #define USP_RFS_SLAVE 0x80000 #define USP_TFS_SLAVE 0x100000 #define USP_TX_IO_MODE #define USP_RX_IO_MODE #define USP_ENABLE 0x20 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 101 -...
  • Page 103 USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); … // Enable TX and RX USP0_MODE1 |= USP_ENABLE; 12.3.2.6 BSPORT Mode (AD6521) Initial Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 102 -...
  • Page 104 USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 103 -...
  • Page 105 USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); … // Enable TX and RX USP0_MODE1 |= USP_ENABLE; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 104 -...

  • Page 106: Usp Transmitting Operation

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 12.4 USP Transmitting Operation There are three methods for the Atlas™ to access the TX_FIFO and transmit the data out, please refer the chapter 6.5.5.2 of Developers Manual, for detailed information of method division and description.
  • Page 107 DMA transmitting finishes. 10. If software needs to start another DMA transmitting operation, it can return to step 7. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 106 -...

  • Page 108: Usp Receiving Operation

    Software can use not only the EMPTY flag, but also the FULL, or one capacity threshold of RX_FIFO to decide whether to read new data from RX_FIFO. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 107 -...

  • Page 109: Dma Recieving Mode

    DMA receiving. 11. If software needs to start another DMA transmitting operation, it can return to step 7. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 108 -...

  • Page 110: Interralation Of Transmitting And Receiving

    Data Register, and if the pin is set to input mode, the value of pin is reflected on the corresponding bit of USP Pin I/O Data Register. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 109 -...
  • Page 111 The following example is set the RXD pin of USP0 to input mode After the USP is reset and read value of RXD pin to a integer of rfs_in . … USP_MODE1 | = 0x42000; … rfs_in = USP_PIN_IO_DATA & 0x1; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 110 -...

  • Page 112: Usp Reconfiguration

    Reinitialize the USP to second mode USP transmit/receive data under the second work mode After USP finishes the data transfer, disable the USP_EN bit Reinitialize the USP to three mode … Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 111 -...

  • Page 113: Sib Initialization

    SIB_TXFIFO_OP = 0x1; //reset the FIFO SIB_RXFIFO_OP = 0x1; //reset the FIFO SIB_TXFIFO_OP = 0x2; //start the FIFO SIB_RXFIFO_OP = 0x2; //start the FIFO //USP3 FIFO initialize Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 112 -...
  • Page 114 //reset the FIFO USP3_RXFIFO_OP = 0x1; //reset the FIFO USP3_TXFIFO_OP = 0x2; //start the FIFO USP3_RXFIFO_OP = 0x2; //start the FIFO //SIB bus enable SIB_ENA = SIB_PORT_ENABLE; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 113 -...

  • Page 115: Sib Operations

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 12.10 SIB Operations After the SIB module is initialized, Atlas™ can write or read the register data of the external SIB device, UCB1200/1300 etc. The interrupt of the UCB1200 can be connected to the GPIO of Atlas™.

  • Page 116: Telecom Data Transfer

    SIB bus to stop the telecom data transfer. Audio data can select either SIB FIFO or USP3 FIFO as the data buffer, and then telecom data will use another one. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 115 -...

  • Page 117: Audio Codec Interface

    AC’97 audio CODEC initialization AC’97 register operation AC’97 record AC’97 playback 3. I2S CODEC configuration I2S dual-channel record and playback I2S single channel record and playback L3 mode implementation Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 116 -...

  • Page 118: Audiocodec Controller Initialization

    Before configure the AC’97 or I2S interface, use needs to initialize the audio CODEC controller first. The audio CODEC controller initialization includes: 1. Program PWR_CLK_EN to provide clock to Atlas audio CODEC interface and DMA interface (the audio data transfer can only be in DMA mode), and then give a software reset to audio CODEC interface;...

  • Page 119: Ac'97 Codec Configuration

    After AC’97 CODEC is powered up, Atlas needs to reset AC’97 audio CODEC by pulling down reset pin of AC’97 audio CODEC for about 80ms. The hardware reset can be realized by Atlas GPIO or extended GPIO. Wait for another 80ms;...
  • Page 120 DMA x-length will be 0, and Y-length must be a non-zero value. Enable DMA interrupt; (Please refer to DMA interface for more information) Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 119 -...
  • Page 121 **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 5) Initialize Atlas AC’97 controller interface; Reset and initialize audio record FIFO; Program CODEC_SHARE register to enable AC’97 record channel; The play channel may also be enabled for AC’97 codec register control.
  • Page 122 5) Instruct DMA audio play channel to run by writing DMA channel 7 start address register. 6) Start audio playback FIFO; Set AC97_START bit to start AC’97 interface CODEC_TX_FIFO_OP_REG = 0x01; CODEC_AC97_CTRL |= AC97_START; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 121 -...

  • Page 123: I2S Codec Configuration

    The following steps describe the procedures necessary for I2S audio record program 1) Atlas audio CODEC interface initialization and select the I2S interface; 2) Intialise Atlas I2S CODEC ctroller a) Enable Atlas b) Program CODEC_UDA_CONTROL to set I2S BIT_CLK frequency...
  • Page 124 DMA x-length will be 0, and Y-length must be a non-zero value. DMA interrupt enable (Please refer to DMA interface for more information) 4) Initialize external I2S Codec through L3 interface by programming Atlas GPIO Reset I2S Codec; Program I2S Codec control register to set gain etc.

  • Page 125: Camera Interface

    14 Camera Interface 14.1 Operation Overview In sensor control interface, support following operation mode: Slave mode, external sensor provide VSYNC, HSYNC and PIXCLK to the Atlas™ processor. Master mode, Atlas™ processor provides VSYNC, HSYNC and PIXCLK signal to the external sensor.

  • Page 126: Initialize Operations

    (iStatus & 0x00008000) // Disable the camera interrupt INT_RISC_MASK &= (~0x00008000); iStatus = CAM_INT_CTRL; // Check which interrupt happens if (iStatus & 0x01) // Clear the interrupt Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 125 -...
  • Page 127 **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE CAM_INT_CTRL = 0x01; // Add similar code here to check other interrupts … // Enable the camera interrupt. INT_RISC_MASK |= 0x00008000; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 126 -...

  • Page 128: Dma Operations

    // Check which interrupt happens if (iStatus & 0x04) // Clear the interrupt. DMA_CH_INT = 0x04; // Set a flag here such as following code. bDMADone = 1; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 127 -...

  • Page 129: Dma Operation

    DMA_CH2_CTRL |= 0x0000; //normal DMA mode DMA_CH2_CTRL |= 0x0008; //burst DMA mode // Start dma channel2 operation, this data must be the DWORD address. DMA_CH2_ADDR = 0x20000/4; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 128 -...

  • Page 130: Sensor Operations

    Sensor Clock Operation 14.4.2.1 Step-by-step register programming Sensor clock can be provided by the CKO of Atlas™-1 except the external oscillator. If using CKO, following register must be configured. Set the PWR_PLL2_CONFIG to select a need frequency. Turn on the PLL2.

  • Page 131: Slave Mode Operation

    In this mode, PIXEL clock, HSYNC and VSYNC are generated by external sensor, so set bit8,9,10 of register CAM_CTRL to 0. Capture the video image as 14.4.3 list. 14.4.4.2 Common examples of use Following example code are based on following conditions: Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 130 -...

  • Page 132: Pixel Data Shift Operation

    DMA_CH2_YLEN = 480-1; // Set the burst DMA mode. DMA_CH2_CTRL = 0x0008; // Start the DMA operation. DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 131 -...

  • Page 133: Inverse Control Operation

    CAM_CTRL register. It must be sure that IOCLK frequency is at least 6 multiple of PIXCLK. Capture the video image as 14.4.3 list. 14.4.7.1 Common examples of use Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 132 -...

  • Page 134: Master Mode Operation

    // Set CAM_CTRL register to enable the PIXCLK, HSYNC and VSYNC output. CAM_CTRL |= 0x0700; // Set the CAM_DMA_LEN to 640*480*2; CAM_DMA_LEN = 640*480*2; // Reset the FIFO Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 133 -...
  • Page 135 CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation CAM_FIFO_OP |= 0x01; After receiving DMA interrupt, it means the receive picture has stored to SDRAM. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 134 -...

  • Page 136: I2C Master Operations

    If success interrupt happens, clear this interrupt and transmission is ok. Otherwise, if fail interrupt happens, you must check your hardware connection and try it again. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 135 -...

  • Page 137: Read N Bytes From External Device

    If success interrupt happens, Read data from CAM_I2C_MASTER_IN. Bit0—bit15 is the valid byte. Clear I C master success interrupt bit. If fail_interrupt happens, you must check your hardware connection and try it again. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 136 -...

  • Page 138: I2C Slave Operations

    CAM_I2C_SALVE_CTRL if bit8 of this register equals to 0. 14.6.2.2 Common examples of use Following example code are based on following conditions: Process register0x0b, suppose its default value = 0x7788. Slave ID of Atlas -1 is 7’h4C. // Set the slave ID to I C slave unit.

  • Page 139: Quick Reference

    Pixel Shift Number vs DMA Register Setting CAM_PIXEL_SHIFT DMA_CH2_XLEN DMA_CH2_YLEN DMA_WIDTH CAM_DMA_LEN 0x01, 0x00, XSIZE/2 YSIZE-1 XSIZE/2 XSIZE*YSIZE*2 0x10~0x16 0x02~0x0x05 XSIZE/4 YSIZE-1 XSIZE/4 XSIZE*YSIZE 0x06~0x09 XSIZE/8 YSIZE-1 XSIZE/8 XSIZE*YSIZE/2 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 138 -...

  • Page 140: Usb 1.1 Device Interface

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 15 USB 1.1 Device Interface 15.1 Operation Overview The Atlas™ USB device is USB version 1.1 compatible. Knowledge of USB standard is helpful to developers. The specification is available at http://www.usb.org. Atlas™ Programming Guide...
  • Page 141 **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 140 -...

  • Page 142: Initialization

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 15.2 Initialization The USB device register space in Atlas™ is from 0x80040000. Offset 0x0~0x7c are USB core registers; 0x80~0x90 are USB interface registers; after 0xf00 are DMA FIFO control registers. Please refer to Atlas™...
  • Page 143 **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 142 -...

  • Page 144: Control Transfer

    Device generates an EP0 TX Interrupt. • Select endpoint. USB_EPINDX = ep_num; • Flush transmition FIFO. (if need) USB_EP0CTL |= 0x10; • Write the data into USB TX data register. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 143 -...
  • Page 145 USB_EPTXDAT = data; • Set EP0 control register bit2. USB_EP0CTL |= 0x20; • Clears the EP0 TX interrupt bit and returns from the interrupt service routine. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 144 -...

  • Page 146: I/O Operation

    Get byte count for the data packet. pkt_len = USB_EPRXCNTL; • Read data from USB. data = USB_EPRXDAT; • Set RX data valid bit after read all data. USB_EPRXCTL |= USB_EP_TX_RX_VALID; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 145 -...
  • Page 147 Clears the EP1~3 RX interrupt bit and returns from the interrupt service routine. For isochronous transfer, the sequence sames to bulk transfer except the interrupt event is SOF interrupt Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 146 -...

  • Page 148: Dma Operation

    USB_CTRL = (dma_len << 8) | 0x06;(if OUT Token) • Set USB BULK mode registers (if USB data flow is BULK). USB_BULK_DMA = 0x01; • Wait until DMA finishes (interrupt from DMA controller) Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 147 -...
  • Page 149 Clears the SOF interrupt bit and returns from the interrupt service routine. (if USB data flow is ISO) For ISO transfer, length of each DMA operation cannot exceed 256 bytes. Please refer to charpter 9 for details of DMA operation. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 148 -...

  • Page 150: Quick Reference

    8-byte 8-byte Interrupt or bulk or isochronous 16-byte 32-byte x2 Interrupt or bulk or isochronous 64-byte 128-byte x2 Interrupt or bulk or isochronous 256-byte 512-byte x2 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 149 -...

  • Page 151: Host Port Interface

    16.1 Operation Overview The Host Port is used when Atlas™ acts as a PCMCIA slave to an external host (such as a PDA or Notebook PC). The Host Port operations are compatible with PC Card Standard 2.1. And the Host Port has some registers that can be accessed by both Atlas™...

  • Page 152: Address Mapping

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 16.2 Address Mapping The Host port register space in Atlas™ is from 0x8009_0000. Offset 0x0~0x3FF are CIS space; 0x400~0x53F are Function Configuration Registers; after 0x540 are other Host port control registers. For more details, please refer to the related section in Atlas™...

  • Page 153: Initialization

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 16.3 Initialization The initialization has two parts: one for the Atlas™, the other for the external PCMCIA host. For Atlas™, the initialization sequence is: • Enable Host Port clock and pins #define PWRCLK_HOST_EN 0x00002000 PWR_PIN_RELEASE = 1;...
  • Page 154 (0x01 << 8) //HP_PCMCIA_INT_EN masks #define HP_PCMCIA_XSFER_INT (0x01 << 7) //HP_CONFIG_INT_EN masks #define HP_CONIG_INT (0x01 << 0) HP_INT_EN |= HP_PCMCIA_INT_MASK | HP_PCMCIA_FUNC0_INT_MASK; HP_PCMCIA_INT_EN = HP_PCMCIA_XSFER_INT; HP_CONFIG_INT_EN_0 = HP_CONIG_INT; Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 153 -...
  • Page 155 **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE For the external PCMCIA host, please refer to the PCMCIA host’s spec. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 154 -...

  • Page 156: I/O & Dma Operation

    There is a 64x8 FIFO SRAM in the Host Port. All the data transfer are done throught this FIFO. The FIFO can be accessed by either RISC or DMA Controller (please refer to the FIFO section in Atlas™ Developer’s Manual). If RISC accesses the FIFO, the data transfer is in I/O mode; if the DMA Controller accesses the FIFO, then the data transfer is in DMA mode.
  • Page 157 Wait until data transfer finishes (HP_PCMCIA_STATUS) while (HP_PCMCIA_STATUS & 0x1); • Reset the FIFO controller HP_FIFO_OP = 0x02 ; After that, the Host port is ready for the next DMA trasnfer. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 156 -...

  • Page 158: Handshaking With Host

    The Atlas™ Host Port can communicate with the external host by two ways: polling and interrupt. Because some registers in the Host Port can be access by both Atlas™ and external host, these registers can be used for handshaking between the Atlas™ Host Port and the external host. The external host can poll the specific register bit of these registers to see if there is any change.

  • Page 159: Secure Disk (Sd) / Multi-Media Card Interface (Mmc)

    SD interface registers. The SD interface accomplish the command by writing the data in registers, and get the responding and status by reading data from registers. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 160: Internal Regsiter Programming

    SD host internal registers, the SD interface put the SDREG_RDY in the bit 16 of IO data. So user can distinguish the success reading by the bit 16 of IO data. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 161: I/O Operation

    If SD_DMA_IO_CTRL is 0x01, the SD interface is in IO writing mode. Program can write data to SD Card by SD_DATA_BUFFERS. If SD_DMA_IO_CTRL is 0x03, the SD interface is in IO reading mode. Program can read data from SD Card by SD_DATA_BUFFERS. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 160 -...

  • Page 162: Dma Operation

    Then the SD interface will read or write data between DMA and FIFO. When the DMA finish the data transfer, the bit 0 of SD_INT_STATUS will be set 1. The program will set the bit 0 of SD_DMA_IO_CTRL for choosing IO mode. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 161 -...

  • Page 163: Initialization

    90M. So the SD_CLK_RATE register must be set to provide the different devision of IO clock to work with the SD card. If the program wants to use the interrupt mode, the SD_INT_CNTL and the SD_INTERRUPT_MASK will be set correct value. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 162 -...

  • Page 164: No Data Command/Response Transaction

    After the CMD_DAT_CONT register is written, the application is required not to change the set of registers until the status register indicates that the command response has finished and the response is in the response FIFO for the application to read. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 163 -...

  • Page 165: Single Block Operation

    After the application read the response from the response FIFO registers, it must wait for the DATA_TRAN_DONE signal in the status register, and then reads the data transfer FIFO buffer. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 166: Multiple Block Operation

    BUF_RDY register. After the adapter from the card has received the last block, the adapter stops the clock. After the last data block is received, the application sends the stop transmission command. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 167: Multiple Block Write Using Number Blocks

    Before the last block, the application informs the adapter that the next block is the last block in the BUF_RDY register. After the adapter from the card has received the last block, the adapter stops the clock. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 166 -...

  • Page 168: Nand Flash Memory Interface

    18 Nand Flash Memory Interface 18.1 Operation Overview The Atlas™ Nand flash controller support five types of data transfer: DMA read, DMA write, RISC read data from FIFO, RISC write data to FIFO, RISC directly read data from Nand flash controller’s data register.

  • Page 169: Io Write

    1. Set DMA_IO_CTRL_REG to 5’b00110 for DMA read or 5’b00100 for DMA write. 2. Write LOW_ADDRESS_REG and HIGH_ADDRESS_REG according to the address you want to read. 3. Write DMA_IO_LEN_REG register and FIFO_LEVEL_CHK_REG register. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 168 -...

  • Page 170: Dma Read Example

    SMDF_FIFO_LEVEL_CHK_REG = 0x40200C; //set FIFO check level SMDF_FIFO_OP_REG = 1; //start FIFO SMDF_DMA_IO_LEN_REG = 528; //write 528 bytes SMDF_COMMAND_REG = 0x80; DMA_CH4_CTRL = 0xC; //DMA burst write Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 169 -...

  • Page 171: Nand Boot-Loader

    Nand Flash card is. Software can write ADD_NUM_REG register to charge this case, but this step will have no influence on reading performance. Following is structure diagram of Nand boot. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 170 -...

  • Page 172: Arm Init Process

    When RISC boots up, it shadows Nand flash memory space to 0, read code directly from Nand flash. In this stage, RISC performs all the initialization required before branching to the main C application code. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE...

  • Page 173: Flash Controller's Global Register Init Process

    There is 2 bytes in the page spare area to indicate the next block location, according this information read all the “NK.BIN” to SDRAM, then parse it. For detail Nand Boot specifacation, please read Nand Boot software document. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 172 -...

  • Page 174: Special Notes

    For example, original address is data<31:0>, software driver need write data<31:9> and data<7:0> to LOW_ADDRESS_REG. HIGH_ADDRESS_REG is needed only in SAMSUNG Nand Flash more than 256MB. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 173 -...

  • Page 175: Lcd Controller Interface

    **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE 19 LCD Controller Interface 19.1 Operation Overview The Atlas™ graphic LCD controller is used for applications like: GPS Navigation/Telematics systems, PDAs and Smartphones. The Atlas™ LCD Controller supports two types of displays: •...
  • Page 176 Frame Valid bit after the DMA starts. For LCD controller interrupt, there are two levels of interrupts (one is in the level of Atlas™-1Interrupt Controller, the other is in the level of LCD controller). To enable the LCD controller interrupts, both the two levels of interrupts must be enabled.

  • Page 177: Dma Operation

    Single DMA can be used to load frame data only when the frame picture is updated (for example, when Atlas™-1 is connected with some Hitachi LCD modules such as TX06D12VM1CAA). As fewer data are loaded, it can save the bus bandwidth and the power a lot.

  • Page 178: Configuration Comparison For Different Mode

    STN displays. For 16bit per pixel color mode, the image data bypass the color palette, and directly output to LCD pins, thus the palette needn’t be configured. Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 177 -...

  • Page 179: Palette

    8/32 0100 0001,0010,0100,1001 0001,0010,0100,1001 10/32 10/32 0101 0010,0101,0010,0101 0010,0101,0010,0101 12/32 12/32 0110 0010,1001,0100,1010 0101,0010,1001,0101 13/32 13/32 0111 0010,1010,0101,0101 0010,1010,0101,0101 14/32 14/32 1000 0010,1010,1010,1010 0101,0101,0101,0101 15/32 15/32 Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 178 -...

  • Page 180: Special Register Configuration

    19.7 Power Sequence / Back Light Control for LCD Displays Many LCD panels need proper power sequence for normal display. In Atlas™-1, we can use some GPIOs or external logic to implement the power sequence. Generally, if two GPIOs are required (named as ENV1 and ENV2), in panel power-up sequence, ENV1 is asserted first, and ENV2 is asserted last, while in panel power-down sequence, ENV2 is de-asserted first, and ENV1 is de-asserted last.

  • Page 181: Revision History

    Interface, Memory Interface, and GPIO Mo and Qingyi Sheng 4/15/03 Added more details for LCD controller Hongyu Zhang, Xiaoyi and NAND Flash controller Qin, and Tiefeng Liu Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 180 -...

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