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FT900
Bridgetek FT900 Manuals
Manuals and User Guides for Bridgetek FT900. We have
1
Bridgetek FT900 manual available for free PDF download: User Manual
Bridgetek FT900 User Manual (210 pages)
Embedded Microcontroller
Brand:
Bridgetek
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Table of Contents
2
Introduction
15
FT900 System Architecture
16
Figure 2.1 - FT900 System Architecture
16
2.1 Architecture Overview
16
2.2 Memory Organization
17
2.3 FT900 Boot Control
17
Table 2.1 - FT900 Program Memory Organization
17
Figure 2.2 - FT900 Boot Control
17
2.4 Debugging Support
18
Figure 2.3 - FT900 Debugging Support
18
Table 3.2 - Register Map for FT900 Series
19
Register Map
19
Table 3.1 - Peripheral Availability on FT900 Series Models
19
Notations
20
Table 4.1 - Notations Used in Register Description
20
Table 5.16 - Pin 20 - 23 Register
21
Table 5.20 - Pin 36 - 39 Register
21
Table 5.18 - Pin 28 - 31 Register
21
Table 5.17 - Pin 24 - 27 Register
21
Table 5.21 - Pin 40 - 43 Register
21
Table 5.14 - Pin 12 - 15 Register
21
Table 5.12 - Pin 04 - 07 Register
21
5.1 Register Summary
21
Table 5.13 - Pin 08 - 11 Register
21
General System Registers
21
Table 5.34 - GPIO 40 - 47 Configuration Register
22
Table 5.37 - GPIO 64 - 66 Configuration Register
22
Table 5.35 - GPIO 48 - 55 Configuration Register
22
Table 5.1 - Overview of General System Registers
22
Table 5.33 - GPIO 32 - 39 Configuration Register
22
Table 5.30 - GPIO 08 - 15 Configuration Register
22
Table 5.29 - GPIO 00 - 07 Configuration Register
22
Table 5.31 - GPIO 16 - 23 Configuration Register
22
Table 5.2 - CHIPID - Chip ID Register
23
Table 5.3 - FT900 Series Revision 0001 Configuration
23
CHIPID - Chip ID Register (Address Offset: 0X00)
23
EFCFG - Chip Configuration Register (Address Offset: 0X04)
23
5.2 Register Details
23
CLKCFG - Clock Configuration Register (Address Offset: 0X08)
24
Table 5.5 - CLKCFG - Clock Configuration Register
24
Table 5.4 - EFCFG - Chip Configuration Register
24
PMCFG - Power Management Register (Address Offset: 0X0C)
25
PTSTNSET - Test & Set Register (Address Offset: 0X10)
26
PTSTNSETR - Test & Set Shadow Register (Address Offset: 0X14)
26
Table 5.6 - PMCFG - Power Management Register
26
Table 5.7 - PTSTNSET - Test & Set Register
26
Table 5.8 - PTSTNSETR - Test & Set Shadow Register
26
MSC0CFG - Miscellaneous Configuration Register (Address Offset: 0X18)
27
Table 5.11 - Pin 00 - 03 Register
29
GPIO Pin Configuration Registers (Address Offset: 0X1C - 0X5F)
29
Table 5.10 - Pin Configuration Register Description
29
Table 5.9 - MSC0CFG - Miscellaneous Configuration Register
29
Table 5.15 - Pin 16 - 19 Register
30
Table 5.19 - Pin 32 - 35 Register
31
Table 5.23 - Pin 48 - 51 Register
32
GPIO Configuration Registers (Address Offset: 0X60 - 0X83)
33
Table 5.27 - Pin 64 - 66 Register
33
Table 5.28 - GPIO Configuration Register Description
33
Table 5.32 - GPIO 24 - 31 Configuration Register
34
Table 5.36 - GPIO 56 - 63 Configuration Register
35
Table 5.43 - GPIO 64 - 66 Interrupt Enable Register
36
Table 5.42 - GPIO 32 - 63 Interrupt Enable Register
36
Table 5.41 - GPIO 00 - 31 Interrupt Enable Register
36
Table 5.39 - GPIO 32 - 63 Value Register
36
Table 5.40 - GPIO 64 - 66 Value Register
36
GPIO Interrupt Enable Registers (Address Offset: 0X90 - 0X9B)
36
GPIO Value Registers (Address Offset: 0X84 - 0X8F)
36
Table 5.38 - GPIO 00 - 31 Value Register
36
Interrupt Pending Registers (Address Offset: 0X9C - 0Xa7)
37
ETH_PHY_CFG - Ethernet PHY Miscellaneous Configuration Register (Address Offset: 0Xa8)
37
Table 5.44 - GPIO 00 - 31 Interrupt Pending Register
37
Table 5.45 - GPIO 32 - 63 Interrupt Pending Register
37
Table 5.46 - GPIO 64 - 66 Interrupt Pending Register
37
Table 5.48 - ETH_PHY_ID - Ethernet PHY ID Register
38
ETH_PHY_ID - Ethernet PHY ID Register (Address Offset: 0Xac)
38
Table 5.47 - ETH_PHY_CFG - Ethernet PHY Miscellaneous Configuration Register
38
DAC_ADC_CONF - ADC/DAC Configuration/Status Register (Address Offset: 0Xb0)
38
DAC_ADC_CNT - ADC/DAC Count Register (Address Offset: 0Xb4)
39
Table 5.49 - DAC_ADC_CONF - ADC/DAC Configuration/Status Register
39
DAC_ADC_DATA - ADC/DAC Data Register (Address Offset: 0Xb8)
40
Table 5.50 - DAC_ADC_CNT - ADC/DAC Count Register
40
Table 5.51 - DAC_ADC_DATA - ADC/DAC Data Register
40
Interrupt Controller
41
6.1 Register Summary
41
Table 6.1 - Interrupt Assignment Table
41
Table 6.3 - IRQ00-03 Assignment Register
42
Table 6.11 - IRQ Control Register
42
Table 6.9 - IRQ24-27 Assignment Register
42
Table 6.4 - IRQ04-07 Assignment Register
42
IRQ00-03 Assignment Register (Address Offset: 0X00)
42
Table 6.2 - Overview of Interrupt Control Registers
42
IRQ08-11 Assignment Register (Address Offset: 0X08)
42
IRQ04-07 Assignment Register (Address Offset: 0X04)
42
6.2 Register Details
42
Table 6.8 - IRQ20-23 Assignment Register
43
Table 6.5 - IRQ08-11 Assignment Register
43
Table 6.6 - IRQ12-15 Assignment Register
43
Table 6.7 - IRQ16-19 Assignment Register
43
IRQ24-27 Assignment Register (Address Offset: 0X18)
43
IRQ20-23 Assignment Register (Address Offset: 0X14)
43
IRQ16-19 Assignment Register (Address Offset: 0X10)
43
IRQ12-15 Assignment Register (Address Offset: 0X0C)
43
IRQ28-31 Assignment Register (Address Offset: 0X1C)
44
IRQ Control Register (Address Offset: 0X20)
44
Table 6.10 - IRQ28-31 Assignment Register
44
Efuse
45
7.1 Introduction
45
7.2 EFUSE Operation
45
7.3 EFUSE Bits
45
Table 7.1 - EFUSE Bits
46
USB Host
47
8.1 Register Summary
47
8.2 EHCI Operational Registers
48
HC Capability Register (Address Offset: 0X00)
48
HCSPARAMS - HC Structural Parameters (Address Offset: 0X04)
48
HCCPARAMS - HC Capability Parameters (Address Offset: 0X08)
48
Table 8.1 - Overview of USB Host Controller Registers
48
Table 8.2 - HC Capability Register
48
Table 8.3 - HCSPARAMS - HC Structural Parameters
48
USBCMD - HC USB Command Register (Address Offset: 0X10)
49
Table 8.4 - HCCPARAMS - HC Capability Parameters
49
USBSTS - HC USB Status Register (Address Offset: 0X14)
50
Table 8.5 - USBCMD - HC USB Command Register
50
USBINTR - HC USB Interrupt Enable Register (Address Offset: 0X18)
51
Table 8.6 - USBSTS - HC USB Status Register
51
PERIODICLISTBASE - HC Periodic Frame List Base Address Register (Address Offset: 0X24)
52
ASYNCLISTADDR - HC Current Asynchronous List Address Register (Address Offset: 0X28)
52
Table 8.7 - USBINTR - HC USB Interrupt Enable Register
52
Table 8.8 - FRINDEX - HC Frame Index Register
52
Table 8.9 - PERIODICLISTBASE - HC Periodic Frame List Base Address Register
52
FRINDEX - HC Frame Index Register (Address Offset: 0X1C)
52
PORTSC - HC Port Status and Control Register (Address Offset: 0X30)
53
Table 8.10 - ASYNCLISTADDR - HC Current Asynchronous List Address Register
53
8.3 Configuration Registers
54
EOF Time & Asynchronous Schedule Sleep Timer Register (Address Offset: 0X34)
54
Table 8.11 - PORTSC - HC Port Status and Control Register
54
Table 8.13 - Bus Monitor Control / Status Register
56
Table 8.14 - HPROT - Master Protection Information Setting Register
56
Bus Monitor Control / Status Register (Address Offset: 0X40)
56
Table 8.12 - EOF Time & Asynchronous Schedule Sleep Timer Register
56
HPROT - Master Protection Information Setting Register (Address Offset: 0X78)
56
8.4 USB Host Testing Registers
57
Vendor Specific IO Control Register (Address Offset: 0X54)
57
Vendor Specific Status Register (Address Offset: 0X58)
57
Test Register (Address Offset: 0X50)
57
Table 8.15 - Vendor Specific IO Control Register
57
Table 8.16 - Vendor Specific Status Register
57
Table 8.17 - Test Register
57
Table 8.19 - HC_RSRV2 - Reserved 2 Register
58
Table 8.18 - HC_RSRV1 - Reserved 1 Register
58
HC_RSRV2 - Reserved 2 Register (Address Offset: 0X74)
58
HC_RSRV1 - Reserved 1 Register (Address Offset: 0X70)
58
USB Peripheral
59
Register Summary
59
9.2 Initialization Registers
61
DC_ADDRESS_ENABLE - Address Register (Address Offset: 0X18)
61
DC_MODE - Mode Register (Address Offset: 0X10)
61
Table 9.1 - Overview of USB Peripheral Registers
61
Table 9.2 - DC_ADDRESS_ENABLE - Address Register
61
Table 9.5 - DC_EP_INT_ENABLE - Endpoints Interrupt Enable Register
62
Table 9.4 - DC_INT_ENABLE - Interrupt Enable Register
62
Table 9.3 - DC_MODE - Mode Register
62
DC_EP0_CONTROL - Endpoint 0 Control Register (Address Offset: 0X1C)
62
9.3 Control Endpoint Data Flow Registers
62
DC_EP_INT_ENABLE - Endpoints Interrupt Enable Register (Address Offset: 0X0C)
62
DC_INT_ENABLE - Interrupt Enable Register (Address Offset: 0X08)
62
DC_EP0_STATUS - Endpoint 0 Status Register (Address Offset: 0X20)
63
DC_EP0_BUFFER_LENGTH - Endpoint 0 Buffer Length Register (Address Offset: 0X24)
63
Table 9.6 - DC_EP0_CONTROL - Endpoint 0 Control Register
63
Table 9.7 - DC_EP0_STATUS - Endpoint 0 Status Register
63
DC_EP0_BUFFER - Endpoint 0 Buffer Register (Address Offset: 0X28)
64
9.4 Other Endpoint Data Flow Registers
64
Dc_Ep(X)_Control - Endpoint Control Registers (Address Offset: 0X2C/0X3C/0X4C/0X5C/0X6C/0X7C/0X8C)
64
Table 9.8 - DC_EP0_BUFFER_LENGTH - Endpoint 0 Buffer Length Register
64
Table 9.9 - DC_EP0_BUFFER - Endpoint 0 Buffer Register
64
Table 9.10 - DC_EP(X)_Control - Endpoint Control Registers
65
Dc_Ep(X)_Status - Endpoint Status Registers (Address Offset: 0X30/0X40/0X50/0X60/0X70/0X80/0X90)
65
Dc_Ep(X)_Buffer_Length_Lsb - Endpoint Buffer Length LSB Registers (Address Offset: 0X34/0X44/0X54/0X64/0X74/0X84/0X94)
66
Dc_Ep(X)_Buffer_Length_Msb - Endpoint Buffer Length MSB Registers (Address Offset: 0X35/0X45/0X55/0X65/0X75/0X85/0X95)
66
Dc_Ep(X)_Buffer - Endpoint Buffer Registers (Address Offset: 0X38/0X48/0X58/0X68/0X78/0X88/0X98)
66
Table 9.11 - DC_EP(X)_Status - Endpoint Status Registers
66
Table 9.12 - DC_EP(X)_Buffer_Length_Lsb - Endpoint Buffer Length LSB Registers
66
Table 9.13 - DC_EP(X)_Buffer_Length_Msb - Endpoint Buffer Length MSB Registers
66
Table 9.14 - DC_EP(X)_Buffer - Endpoint Buffer Registers
66
Table 9.18 - DC_FRAME_NUMBER_MSB - Frame Number MSB Register
67
Table 9.17 - DC_FRAME_NUMBER_LSB - Frame Number LSB Register
67
Table 9.16 - DC_EP_INT_STATUS - Endpoints Interrupt Status Register
67
Table 9.15 - DC_INT_STATUS - Interrupt Status Register
67
DC_FRAME_NUMBER_MSB - Frame Number MSB Register (Address Offset: 0X15)
67
DC_FRAME_NUMBER_LSB - Frame Number LSB Register (Address Offset: 0X14)
67
DC_EP_INT_STATUS - Endpoints Interrupt Status Register (Address Offset: 0X04)
67
DC_INT_STATUS - Interrupt Status Register (Address Offset: 0X00)
67
9.5 General Registers
67
10 Ethernet
68
10.1 Register Summary
68
Table 10.1 - Memory Organization of TX/RX RAM
68
Register Details
69
ETH_INT_STATUS - Interrupt Status Register (Address Offset: 0X0)
69
Table 10.2 - Overview of Ethernet Registers
69
ETH_INT_ENABLE - Interrupt Enable Register (Address Offset: 0X1)
70
Table 10.3 - ETH_INT_STATUS - Interrupt Status Register
70
Table 10.4 - ETH_INT_ENABLE - Interrupt Enable Register
70
Table 10.5 - ETH_RX_CNTL - Receive Control Register
71
ETH_TX_CNTL - Transmit Control Register (Address Offset: 0X03)
71
ETH_RX_CNTL - Receive Control Register (Address Offset: 0X02)
71
ETH_DATA_N0 - Data Register (Octet N) (Address Offset: 0X04)
72
ETH_DATA_N2 - Data Register (Octet N+2) (Address Offset: 0X06)
72
ETH_DATA_N3 - Data Register (Octet N+3) (Address Offset: 0X07)
72
ETH_ADDR_1 - Address Register (Octet 1) (Address Offset: 0X08)
72
ETH_ADDR_2 - Address Register (Octet 2) (Address Offset: 0X09)
72
Table 10.6 - ETH_TX_CNTL - Transmit Control Register
72
Table 10.7 - ETH_DATA_N0 - Data Register (Octet N)
72
Table 10.8 - ETH_DATA_N1 - Data Register (Octet N+1)
72
Table 10.9 - ETH_DATA_N2 - Data Register (Octet N+2)
72
ETH_DATA_N1 - Data Register (Octet N+1) (Address Offset: 0X05)
72
Table 10.13 - ETH_ADDR_3 - Address Register (Octet 3)
73
Table 10.16 - ETH_ADDR_6 - Address Register (Octet 6)
73
Table 10.15 - ETH_ADDR_5 - Address Register (Octet 5)
73
Table 10.14 - ETH_ADDR_4 - Address Register (Octet 4)
73
ETH_ADDR_4 - Address Register (Octet 4) (Address Offset: 0X0B)
73
ETH_MNG_CNTL - Management Control Register (Address Offset: 0X0F)
73
ETH_THRESHOLD - Threshold Register (Address Offset: 0X0E)
73
ETH_ADDR_6 - Address Register (Octet 6) (Address Offset: 0X0D)
73
ETH_ADDR_5 - Address Register (Octet 5) (Address Offset: 0X0C)
73
ETH_ADDR_3 - Address Register (Octet 3) (Address Offset: 0X0A)
73
Table 10.22 - ETH_MNG_TX1 - Management Transmit Data 1 Register
74
Table 10.21 - ETH_MNG_TX0 - Management Transmit Data 0 Register
74
Table 10.20 - ETH_MNG_ADDR - Management Address Register
74
Table 10.19 - ETH_MNG_DIV - Management Divider Register
74
Table 10.18 - ETH_MNG_CNTL - Management Control Register
74
ETH_MNG_TX1 - Management Transmit Data 1 Register (Address Offset: 0X13)
74
ETH_MNG_TX0 - Management Transmit Data 0 Register (Address Offset: 0X12)
74
ETH_MNG_ADDR - Management Address Register (Address Offset: 0X11)
74
ETH_MNG_DIV - Management Divider Register (Address Offset: 0X10)
74
ETH_MNG_RX0 - Management Receive Data 0 Register (Address Offset: 0X14)
75
ETH_MNG_RX1 - Management Receive Data 1 Register (Address Offset: 0X15)
75
ETH_NUM_PKT - Number of Packets Register (Address Offset: 0X16)
75
ETH_TR_REQ - Transmission Request Register (Address Offset: 0X17)
75
Table 10.23 - ETH_MNG_RX0 - Management Receive Data 0 Register
75
Table 10.24 - ETH_MNG_RX1 - Management Receive Data 1 Register
75
Table 10.25 - ETH_NUM_PKT - Number of Packets Register
75
Table 10.26 - ETH_TR_REQ - Transmission Request Register
75
11 CAN Bus Controller
76
Table 11.1 - Symbols Used in the CAN Frame Buffer
76
Table 11.2 - Standard Frames Memory Buffer Layout
77
Table 11.3 - Extended Frames Memory Buffer Layout
77
11.1 Register Summary
78
11.2 Register Details
79
CAN_MODE - Mode Register (Address Offset: 0X00)
79
CAN_CMD - Command Register (Address Offset: 0X01)
79
Table 11.4 - Overview of CAN Registers
79
Table 11.5 - CAN_MODE - Mode Register
79
CAN_STATUS - Status Register (Address Offset: 0X02)
80
Table 11.6 - CAN_CMD - Command Register
80
Table 11.7 - CAN_STATUS - Status Register
80
Table 11.8 - CAN_INT_STATUS - Interrupt Status Register
81
CAN_INT_ENABLE - Interrupt Enable Register (Address Offset: 0X04)
81
CAN_INT_STATUS - Interrupt Status Register (Address Offset: 0X03)
81
Table 11.10 - CAN_RX_MSG - Receive Message Register
82
Table 11.11 - CAN_BUS_TIM_0 - Bus Timing 0 Register
82
CAN_RX_MSG - Receive Message Register (Address Offset: 0X05)
82
Table 11.9 - CAN_INT_ENABLE - Interrupt Enable Register
82
CAN_BUS_TIM_1 - Bus Timing 1 Register (Address Offset: 0X07)
82
CAN_BUS_TIM_0 - Bus Timing 0 Register (Address Offset: 0X06)
82
11.2.9 CAN_TX_BUF - Transmit Buffer Register
83
Table 11.12 - CAN_BUS_TIM_1 - Bus Timing 1 Register
83
Table 11.13 - CAN_TX_BUF_0 - Transmit Buffer 0 Register
83
Table 11.14 - CAN_TX_BUF_1 - Transmit Buffer 1 Register
83
Table 11.18 - CAN_RX_BUF_1 - Receive Buffer 1 Register
84
Table 11.17 - CAN_RX_BUF_0 - Receive Buffer 0 Register
84
Table 11.16 - CAN_TX_BUF_3 - Transmit Buffer 3 Register
84
Table 11.15 - CAN_TX_BUF_2 - Transmit Buffer 2 Register
84
11.2.10 CAN_RX_BUF - Receive Buffer Register
84
11.2.11 CAN Acceptance Filter
85
Table 11.19 - CAN_RX_BUF_2 - Receive Buffer 2 Register
85
Table 11.20 - CAN_RX_BUF_3 - Receive Buffer 3 Register
85
Figure 11.1 - CAN Acceptance Filter
85
Table 11.21- CAN_ACC_CODE_0 - Acceptance Code 0 Register
86
Table 11.25 - CAN_ACC_MASK_0 - Acceptance Mask 0 Register
87
Table 11.26 - CAN_ACC_MASK_1 - Acceptance Mask 1 Register
87
Table 11.24 - CAN_ACC_CODE_3 - Acceptance Code 3 Register
87
Table 11.22 - CAN_ACC_CODE_1 - Acceptance Code 1 Register
87
Table 11.23 - CAN_ACC_CODE_2 - Acceptance Code 2 Register
87
CAN_ERR_CODE - Error Code Capture Register (Address Offset: 0X18)
88
CAN_RX_ERR_CNTR - Receive Error Counter Register (Address Offset: 0X19)
88
Table 11.27 - CAN_ACC_MASK_2 - Acceptance Mask 2 Register
88
Table 11.28 - CAN_ACC_MASK_3 - Acceptance Mask 3 Register
88
Table 11.29 - CAN_ERR_CODE - Error Code Capture Register
88
Table 11.30 - CAN_RX_ERR_CNTR - Receive Error Counter Register
88
CAN_TX_ERR_CNTR - Transmit Error Counter Register (Address Offset: 0X1A)
89
CAN_ARB_LOST_CODE - Arbitration Lost Code Capture Register (Address Offset: 0X1B)
89
Table 11.31 - CAN_TX_ERR_CNTR - Transmit Error Counter Register
89
Table 11.32 - CAN_ARB_LOST_CODE - Arbitration Lost Code Capture Register
89
Table 12.9 - 11.2.8 SDH_BUF_DATA - Buffer Data Port Register
90
12 SD Host
90
12.1 Register Summary
90
12.2 Register Details
93
SDH_AUTO_CMD23_ARG2 - Auto CMD23 Argument 2 Register (Address Offset: 0X00)
93
SDH_BLK_SIZE - Block Size Register (Address Offset: 0X04)
93
SDH_BLK_COUNT - Block Count Register (Address Offset: 0X06)
93
SDH_ARG_1 - Argument 1 Register (Address Offset: 0X08)
93
Table 12.1 - Overview of SD Host Registers
93
Table 12.2 - 11.2.1 SDH_AUTO_CMD23_ARG2 - Auto CMD23 Argument 2 Register
93
Table 12.3 - 11.2.2 SDH_BLK_SIZE - Block Size Register
93
Table 12.4 - 11.2.3 SDH_BLK_COUNT - Block Count Register
93
Table 12.5 - 11.2.4 SDH_ARG_1 - Argument 1 Register
93
Table 12.6 - 11.2.5 SDH_TNSFER_MODE - Transfer Mode Register
94
SDH_TNSFER_MODE - Transfer Mode Register (Address Offset: 0X0C)
94
SDH_CMD - Command Register (Address Offset: 0X0E)
94
Table 12.8 - 11.2.7 SDH_RESPONSE - Response Register
95
SDH_RESPONSE - Response Register (Address Offset: 0X10-0X1C)
95
Table 12.7 - 11.2.6 SDH_CMD - Command Register
95
SDH_BUF_DATA - Buffer Data Port Register (Address Offset: 0X20)
95
SDH_PRESENT_STATE - Present State Register (Address Offset: 0X24)
96
Table 12.10 - 11.2.9 SDH_PRESENT_STATE - Present State Register
97
SDH_HST_CNTL_1 - Host Control 1 Register (Address Offset: 0X28)
98
SDH_PWR_CNTL - Power Control Register (Address Offset: 0X29)
98
SDH_BLK_GAP_CNTL - Block Gap Control Register (Address Offset: 0X2A)
98
Table 12.11 - SDH_HST_CNTL_1 - Host Control 1 Register
98
Table 12.12 - SDH_PWR_CNTL - Power Control Register
98
Table 12.14 - SDH_CLK_CNTL - Clock Control Register
99
Table 12.15 - SDH_TIMEOUT_CNTL - Timeout Control Register
99
SDH_CLK_CNTL - Clock Control Register (Address Offset: 0X2C)
99
Table 12.13 - SDH_BLK_GAP_CNTL - Block Gap Control Register
99
SDH_SW_RST - Software Reset Register (Address Offset: 0X2F)
99
SDH_TIMEOUT_CNTL - Timeout Control Register (Address Offset: 0X2E)
99
SDH_NRML_INT_STATUS - Normal Interrupt Status Register (Address Offset: 0X30)
100
SDH_ERR_INT_STATUS - Error Interrupt Status Register (Address Offset: 0X32)
100
Table 12.16 - SDH_SW_RST - Software Reset Register
100
Table 12.17 - SDH_NRML_INT_STATUS - Normal Interrupt Status Register
100
Table 12.18 - 11.2.17 SDH_ERR_INT_STATUS - Error Interrupt Status Register
101
SDH_NRML_INT_ENABLE - Normal Interrupt Status Enable Register (Address Offset: 0X34)
101
SDH_NRML_INT_SGNL_ENABLE - Normal Interrupt Signal Enable Register (Address Offset: 0X38)
102
Table 12.19 - SDH_NRML_INT_ENABLE - Normal Interrupt Status Enable Register
102
Table 12.20 - SDH_ERR_INT_ENABLE - Error Interrupt Status Enable Register
102
SDH_ERR_INT_ENABLE - Error Interrupt Status Enable Register (Address Offset: 0X36)
102
SDH_ERR_INT_SGNL_ENABLE - Error Interrupt Signal Enable Register (Address Offset: 0X3A)
103
SDH_AUTO_CMD12_ERR_STATUS - Auto CMD12 Error Status Register (Address Offset: 0X3C)
103
Table 12.21 - SDH_NRML_INT_SGNL_ENABLE - Normal Interrupt Signal Enable Register
103
Table 12.22 - SDH_ERR_INT_SGNL_ENABLE - Error Interrupt Signal Enable Register
103
Table 12.23 - SDH_AUTO_CMD12_ERR_STATUS - Auto CMD12 Error Status Register
104
Table 12.24 - SDH_HOST_CNTL_2 - Host Control 2 Register
104
SDH_CAP_1 - Capabilities Register 1 (Address Offset: 0X40)
104
SDH_HOST_CNTL_2 - Host Control 2 Register (Address Offset: 0X3E)
104
SDH_CAP_2 - Capabilities Register 2 (Address Offset: 0X44)
105
Table 12.25 - SDH_CAP_1 - Capabilities Register 1
105
SDH_RSRV_1 - Reserved 1 Register (Address Offset: 0X48)
106
SDH_RSRV_2 - Reserved 2 Register (Address Offset: 0X4C)
106
SDH_FORCE_EVT_CMD_ERR_STATUS - Force Event Register for Auto CMD Error Status (Address Offset: 0X50)
106
Table 12.26 - SDH_CAP_2 - Capabilities Register 2
106
Table 12.27 - SDH_RSRV_1 - Reserved 1 Register
106
Table 12.28 - SDH_RSRV_2 - Reserved 2 Register
106
Table 12.29 - SDH_FORCE_EVT_CMD_ERR_STATUS - Force Event Register for Auto CMD Error
106
Table 12.32 - SDH_RSRV_4 - Reserved 4 Register
107
Table 12.30 - SDH_FORCE_EVT_ERR_INT_STATUS - Force Event for Error Interrupt Status
107
Table 12.31- SDH_RSRV_3 - Reserved 3 Register
107
SDH_PRST_INIT - Preset Value for Initialization (Address Offset: 0X60)
107
SDH_RSRV_3 - Reserved 3 Register (Address Offset: 0X54)
107
SDH_FORCE_EVT_ERR_INT_STATUS - Force Event for Error Interrupt Status Register (Address Offset: 0X52)
107
SDH_RSRV_4 - Reserved 4 Register (Address Offset: 0X58)
107
SDH_PRST_DFLT_SPD - Preset Value for Default Speed (Address Offset: 0X62)
108
SDH_PRST_HIGH_SPD - Preset Value for the High Speed (Address Offset: 0X64)
108
SDH_PRST_SDR12 - Preset Value for SDR12 (Address Offset: 0X66)
108
Table 12.33 - SDH_PRST_INIT - Preset Value for Initialization
108
Table 12.34 - SDH_PRST_DFLT_SPD - Preset Value for Default Speed
108
Table 12.35 - SDH_PRST_HIGH_SPD - Preset Value for the High Speed
108
Table 12.36 - SDH_PRST_SDR12 - Preset Value for SDR12
109
Table 12.37 - SDH_PRST_SDR25 - Preset Value for SDR25
109
SDH_PRST_SDR50 - Preset Value for SDR50 (Address Offset: 0X6A)
109
SDH_PRST_SDR25 - Preset Value for SDR25 (Address Offset: 0X68)
109
SDH_PRST_SDR104 - Preset Value for SDR104 (Address Offset: 0X6C)
110
SDH_PRST_DDR50 - Preset Value for DDR50 (Address Offset: 0X6E)
110
Table 12.38 - SDH_PRST_SDR50 - Preset Value for SDR50
110
Table 12.39 - SDH_PRST_SDR104 - Preset Value for SDR104
110
SDH_RSRV_5 - Reserved 5 Register (Address Offset: 0Xfc)
111
SDH_HC_VER - Host Controller Version Register (Address Offset: 0Xfe)
111
SDH_VNDR_0 - Vendor-Defined 0 Register (Address Offset: 0X100)
111
Table 12.40 - SDH_PRST_DDR50 - Preset Value for DDR50
111
Table 12.41 - SDH_RSRV_5 - Reserved 5 Register
111
Table 12.42 - SDH_HC_VER - Host Controller Version Register
111
Table 12.45 - SDH_VNDR_2 - Vendor-Defined 2 Register
112
Table 12.44 - SDH_VNDR_1 - Vendor-Defined 1 Register
112
SDH_VNDR_3 - Vendor-Defined 3 Register (Address Offset: 0X10C)
112
Table 12.43 - SDH_VNDR_0 - Vendor-Defined 0 Register
112
SDH_VNDR_1 - Vendor-Defined 1 Register (Address Offset: 0X104)
112
SDH_VNDR_2 - Vendor-Defined 2 Register (Address Offset: 0X108)
112
SDH_VNDR_4 - Vendor-Defined 4 Register (Address Offset: 0X110)
113
SDH_VNDR_5 - Vendor-Defined 5 Register (Address Offset: 0X114)
113
SDH_VNDR_6 - Vendor-Defined 6 Register (Address Offset: 0X118)
113
SDH_VNDR_7 - Vendor-Defined 7 Register (Address Offset: 0X11C)
113
Table 12.46 - SDH_VNDR_3 - Vendor-Defined 3 Register
113
Table 12.47 - SDH_VNDR_4 - Vendor-Defined 4 Register
113
Table 12.48 - SDH_VNDR_5 - Vendor-Defined 5 Register
113
Table 12.49 - SDH_VNDR_6 - Vendor-Defined 6 Register
113
Table 12.50 - SDH_VNDR_7 - Vendor-Defined 7 Register
113
Table 12.51 - SDH_VNDR_8 - Vendor-Defined 8 Register
114
Table 12.54 - SDH_HW_ATTR - Hardware Attributes Register
114
Table 12.53 - SDH_RSRV_6 - Reserved 6 Register
114
Table 12.52 - SDH_VNDR_9 - Vendor-Defined 9 Register
114
SDH_VNDR_9 - Vendor-Defined 9 Register (Address Offset: 0X124)
114
SDH_CPR_MOD_CNTL - Cipher Mode Control Register (Address Offset: 0X180)
114
SDH_HW_ATTR - Hardware Attributes Register (Address Offset: 0X178)
114
SDH_RSRV_6 - Reserved 6 Register (Address Offset: 0X128)
114
SDH_VNDR_8 - Vendor-Defined 8 Register (Address Offset: 0X120)
114
Table 12.55 - SDH_CPR_MOD_CNTL - Cipher Mode Control Register
115
Table 12.56 - SDH_CPR_MOD_STATUS - Cipher Mode Status Register
116
Table 12.59 - SDH_IN_DATA_LSB -Input Data LSB Register
116
Table 12.58 - SDH_CPR_MOD_SIG_EN - Cipher Mode Signal Enable Register
116
Table 12.57 - SDH_CPR_MOD_STATUS_EN - Cipher Mode Status Enable Register
116
SDH_CPR_MOD_STATUS - Cipher Mode Status Register (Address Offset: 0X184)
116
SDH_IN_KEY_LSB - Input Key LSB Register (Address Offset: 0X194)
116
SDH_IN_DATA_LSB -Input Data LSB Register (Address Offset: 0X18C)
116
SDH_CPR_MOD_SIG_EN - Cipher Mode Signal Enable Register (Address Offset: 0X18A)
116
SDH_CPR_MOD_STATUS_EN - Cipher Mode Status Enable Register (Address Offset: 0X188)
116
SDH_IN_DATA_MSB -Input Data MSB Register (Address Offset: 0X190)
116
Table 12.62 - SDH_IN_KEY_MSB - Input Key MSB Register
117
Table 12.65 - SDH_SCRT_CONS_DATA - Secret Constant Table Data Port
117
Table 12.63 - SDH_OUT_DATA_LSB - Output Data LSB Register
117
Table 12.64 - SDH_OUT_DATA_MSB - Output Data MSB Register
117
SDH_SCRT_CONS_DATA - Secret Constant Table Data Port (Address Offset: 0X1A4)
117
SDH_OUT_DATA_MSB - Output Data MSB Register (Address Offset: 0X1A0)
117
SDH_OUT_DATA_LSB - Output Data LSB Register (Address Offset: 0X19C)
117
SDH_IN_KEY_MSB - Input Key MSB Register (Address Offset: 0X198)
117
13 Uart
118
13.1 Register Summary
119
Table 13.1 - Overview of UART Registers
120
Uart Mode Selection
121
Table 13.2 - UART Mode Selection
121
UART_INT_ENABLE - Interrupt Enable Register (Address Offset: 0X01)
123
Table 13.5 - UART_DIV_LSB - Divisor LSB Register
123
Table 13.4 - UART_THR - Transmitter Holding Register
123
Table 13.3 - UART_RBR - Receiver Buffer Register
123
Table 13.6 - UART_DIV_MSB - Divisor MSB Register
123
UART_DIV_MSB - Divisor MSB Register (Address Offset: 0X01 and LCR[7] = 1)
123
UART_DIV_LSB - Divisor LSB Register (Address Offset: 0X00 and LCR[7] = 1)
123
UART_THR - Transmitter Holding Register (Address Offset: 0X00 and LCR[7] = 0)
123
UART_RBR - Receiver Buffer Register (Address Offset: 0X00 and LCR[7] = 0)
123
13.3 Standard 550 Compatible Registers
123
UART_INT_STATUS - Interrupt Status Register (Address Offset: 0X02)
124
Table 13.7 - UART_INT_ENABLE - Interrupt Enable Register
124
Table 13.8 - UART_INT_STATUS - Interrupt Status Register
124
UART_FCR - FIFO Control Register (Address Offset: 0X02)
125
Table 13.9 - Interrupt Status Register Software Handling
125
Table 13.10 - UART_FCR - FIFO Control Register - 550 Mode
125
Table 13.11 - UART_RCVR - FIFO Trigger Level - 550 Mode
126
Table 13.12 - UART FCR - FIFO Control Register - 650 Mode
126
Table 13.14 - XMIT FIFO Trigger Level
127
UART_LCR - Line Control Register (Address Offset: 0X03)
127
Table 13.13 - UART_RCVR - FIFO Trigger Level - 650 Mode
127
UART_MCR - Modem Control Register (Address Offset: 0X04)
128
Table 13.15 - UART_LCR - Line Control Register
128
UART_LSR - Line Status Register (Address Offset: 0X05)
129
Table 13.16 - UART_MCR - Modem Control Register
129
UART_MSR - Modem Status Register (Address Offset: 0X06)
130
Table 13.17 - UART_LSR - Line Status Register
130
Table 13.18 - UART_MSR - Modem Status Register
131
Table 13.19 - UART_SPR - SPR Register
131
UART_SPR - SPR Register (Address Offset: 0X07)
131
UART_EFR - Enhanced Feature Register (Address Offset: 0X02)
131
13.4 650 Compatible Registers
131
Table 13.21 - UART_XON1 - XON1 Register
132
Table 13.24 - UART_XOFF2 - XOFF2 Register
132
Table 13.23 - UART_XOFF1 - XOFF1 Register
132
Table 13.22 - UART_XON2 - XON2 Register
132
UART_XON2 - XON2 Register (Address Offset: 0X05)
132
Table 13.20 - UART_EFR - Enhanced Feature Register
132
UART_XOFF1 - XOFF1 Register (Address Offset: 0X06)
132
UART_XON1 - XON1 Register (Address Offset: 0X04)
132
UART_XOFF2 - XOFF2 Register (Address Offset: 0X07)
132
13.5 950 Compatible Registers
133
UART_ASR - Additional Status Register (Address Offset: 0X01)
133
UART_RFL - Receiver FIFO Level Register (Address Offset: 0X03)
133
UART_TFL - Transmitter FIFO Level Register (Address Offset: 0X04)
133
Table 13.25 - UART_ASR - Additional Status Register
133
Table 13.26 - UART_RFL - Receiver FIFO Level Register
133
Table 13.27 - UART_TFL - Transmitter FIFO Level Register
133
Figure 13.1 - ICR Registers Write Access
134
Table 13.28 - UART_ICR - ICR Register
134
13.6 Indexed Control Registers
134
UART_ICR - ICR Register (Address Offset: 0X05)
134
Figure 13.2 - ICR Registers Read Access
135
UART_ACR - Additional Control Register (SPR Offset: 0X00)
136
Table 13.29 - UART_ACR- Additional Control Register
136
UART_CPR - Clock Prescaler Register (SPR Offset: 0X01)
137
UART_TCR - Time Clock Register (SPR Offset: 0X02)
137
UART_CKS Clock Select Register (SPR Offset: 0X03)
137
Table 13.30 - UART_CPR - Clock Prescaler Register
137
Table 13.31 - UART_TCR - Time Clock Register
137
Table 13.33 - UART_TTL - Transmitter Trigger Level Register
138
Table 13.35 - UART_FCL - Flow Control Level LSB Register
138
Table 13.34 - UART_RTL - Receiver Trigger Level Register
138
UART_RTL - Receiver Trigger Level Register (SPR Offset: 0X05)
138
Table 13.32 - UART_CKS Clock Select Register
138
UART_FCL - Flow Control Level LSB Register (SPR Offset: 0X06)
138
UART_TTL - Transmitter Trigger Level Register (SPR Offset: 0X04)
138
UART_FCH - Flow Control Level Register MSB (SPR Offset: 0X07)
138
Table 13.36 - UART_FCH - Flow Control Level Register MSB
139
Table 13.40 - UART_REV - Revision Register
139
Table 13.39 UART_ID3 - Identification 3 Register
139
Table 13.38 - UART_ID2 - Identification 2 Register
139
Table 13.37 - UART_ID1 - Identification 1 Register
139
UART_CSR - Channel Software Reset Register (SPR Offset: 0X0C)
139
UART_REV - Revision Register (SPR Offset: 0X0B)
139
UART_ID3 - Identification 3 Register (SPR Offset: 0X0A)
139
UART_ID2 - Identification 2 Register (SPR Offset: 0X09)
139
UART_ID1 - Identification 1 Register (SPR Offset: 0X08)
139
UART_NMR - Nine Bit Mode Register (SPR Offset: 0X0D)
140
UART_MDM - Modem Disable Mask Register (SPR Offset: 0X0E)
140
Table 13.42 - UART_NMR - Nine Bit Mode Register
140
Table 13.47 - UART_PIDX - Port Index Register
141
Table 13.44 - UART_RFC - Readable FCR Register
141
Table 13.46 - UART_RSRV_1 - Reserved 1 Register
141
Table 13.45 - UART_GDS - Good Data Status Register
141
UART_GDS - Good Data Status Register (SPR Offset: 0X10)
141
Table 13.43 - UART_MDM - Modem Disable Mask Register
141
UART_RFC - Readable FCR Register (SPR Offset: 0X0F)
141
UART_CKA - Clock Alteration Register (SPR Offset: 0X13)
141
UART_RSRV_1 - Reserved 1 Register (SPR Offset: 0X11)
141
UART_PIDX - Port Index Register (SPR Offset: 0X12)
141
14 Timers and Watchdog
142
Table 14.1 - Timers/Watchdog Operation
143
Table 14.3 - TIMER_CONTROL_0 - Timers Control Register 0
143
Table 14.2 - Overview of Timers/Watchdog Registers
143
TIMER_CONTROL_0 - Timers Control Register 0 (Address Offset: 0X00)
143
Register Details
143
14.1 Register Summary
143
TIMER_CONTROL_2 - Timers Control Register 2 (Address Offset: 0X02)
144
TIMER_CONTROL_3 - Timers Control Register 3 (Address Offset: 0X03)
144
Table 14.4 - TIMER_CONTROL_1 - Timers Control Register 1
144
Table 14.5 - TIMER_CONTROL_2 - Timers Control Register 2
144
Table 14.6 - TIMER_CONTROL_3 - Timers Control Register 3
144
TIMER_CONTROL_1 - Timers Control Register 1 (Address Offset: 0X01)
144
Table 14.7 - TIMER_CONTROL_4 - Timers Control Register 4
145
Table 14.10 - TIMER_WDG - Watchdog Start Value
145
Table 14.9 - TIMER_SELECT - Timers A..D Select Register
145
Table 14.8 - TIMER_INT - Timers Interrupt Register
145
TIMER_WDG - Watchdog Start Value (Address Offset: 0X07)
145
TIMER_INT - Timers Interrupt Register (Address Offset: 0X05)
145
TIMER_CONTROL_4 - Timers Control Register 4 (Address Offset: 0X04)
145
TIMER_SELECT - Timers a
145
TIMER_READ_MS - Timer a
146
Table 14.14 - TIMER_PRESC_MS - Prescaler Start Value 15:8
146
Table 14.12 - TIMER_WRITE_MS - Timer A..D Start Value 15:8
146
Table 14.11 - TIMER_WRITE_LS - Timer A..D Start Value 7:0
146
Table 14.13 - TIMER_PRESC_LS - Prescaler Start Value 7:0
146
TIMER_READ_LS - Timer a
146
TIMER_PRESC_MS - Prescaler Start Value 15:8 (Address Offset: 0X0B)
146
TIMER_PRESC_LS - Prescaler Start Value 7:0 (Address Offset: 0X0A)
146
TIMER_WRITE_MS - Timer a
146
TIMER_WRITE_LS - Timer a
146
15 I2S
147
Table 15.1 - Oversampling Rates Supported by FT900 I2S
148
Table 15.2 - FT900 I2S Settings
148
15.1 Register Summary
149
Register Details
149
I2SCR - Configuration Register 1 (Address Offset: 0X00)
149
Table 15.3 - Overview of I2S Registers
149
Table 15.4 - I2SCR - Configuration Register 1
149
I2SCR2 - Configuration Register 2 (Address Offset: 0X02)
150
Table 15.5 - I2SCR2 - Configuration Register 2
150
Table 15.6 - I2SIRQEN - Interrupt Enable Register
151
I2SIRQEN - Interrupt Enable Register (Address Offset: 0X04)
151
I2SIRQPEND - Interrupt Pending Register (Address Offset: 0X06)
151
I2SRWDATA - Transmit / Receive Data Register (Address Offset: 0X08)
152
I2SRXCOUNT - RX Count Register (Address Offset: 0X0C)
152
I2STXCOUNT - TX Count Register (Address Offset: 0X0E)
152
Table 15.7 - I2SIRQPEND - Interrupt Pending Register
152
Table 15.8 - I2SRWDATA - Transmit / Receive Data Register
152
Table 15.9 - I2SRXCOUNT - RX Count Register
152
Table 15.10 - I2STXCOUNT - TX Count Register
152
16 SPI Master
153
16.1 Register Summary
153
Table 16.1 - Overview of SPI Master Registers
153
Table 16.2 - SPIM_CNTL - Control Register
154
16.2 Register Details
154
SPIM_STATUS - Status Register (Address Offset: 0X04)
154
SPIM_CNTL - Control Register (Address Offset: 0X00)
154
SPIM_DATA - Receiver and Transmitter Data Registers (Address Offset: 0X08)
155
SPIM_SLV_SEL_CNTL - Slave Select Control Register (Address Offset: 0X0C)
155
SPIM_FIFO_CNTL - FIFO Control Register (Address Offset: 0X10)
155
Table 16.3 - SPIM_STATUS - Status Register
155
Table 16.4 - SPIM_DATA - Receiver and Transmitter Data Registers
155
Table 16.5 - SPIM_SLV_SEL_CNTL - Slave Select Control Register
155
Table 16.9 - SPIM_RX_FIFO_COUNT - SPI Master RX FIFO Count Register
156
Table 16.8 - SPIM_ALT_DATA - Alternative SPI Master Data Register
156
Table 16.7 - SPIM_TNSFR_FRMT_CNTL - Transfer Format Control Register
156
Table 16.6 - SPIM_FIFO_CNTL - FIFO Control Register
156
SPIM_RX_FIFO_COUNT - SPI Master RX FIFO Count Register (Address Offset: 0X1C)
156
SPIM_TNSFR_FRMT_CNTL - Transfer Format Control Register (Address Offset: 0X14)
156
SPIM_ALT_DATA - Alternative SPI Master Data Register (Address Offset: 0X18)
156
SPI Slaves
157
Register Summary
157
Table 17.1 - Overview of SPI Slave Registers
157
Register Details
158
SPIS_CNTL - Control Register (Address Offset: 0X00)
158
SPIS_STATUS - Status Register (Address Offset: 0X04)
158
Table 17.2 - SPIS_CNTL - Control Register
158
Table 17.4 - SPIS_DATA - Receiver and Transmitter Data Registers
159
Table 17.6 - SPIS_FIFO_CNTL - FIFO Control Register
159
Table 17.5 - SPIS_SLV_SEL_CNTL - Slave Select Control Register
159
SPIS_FIFO_CNTL - FIFO Control Register (Address Offset: 0X10)
159
Table 17.3 - SPIS_STATUS - Status Register
159
SPIS_SLV_SEL_CNTL - Slave Select Control Register (Address Offset: 0X0C)
159
SPIS_DATA - Receiver and Transmitter Data Registers (Address Offset: 0X08)
159
SPIS_TNSFR_FRMT_CNTL - Transfer Format Control Register (Address Offset: 0X14)
160
SPIS_ALT_DATA - Alternative SPI Slave Data Register (Address Offset: 0X18)
160
SPIS_RX_FIFO_COUNT - SPI Slave RX FIFO Count Register (Address Offset: 0X1C)
160
Table 17.7 - SPIS_TNSFR_FRMT_CNTL - Transfer Format Control Register
160
Table 17.8 - SPIS_ALT_DATA - Alternative SPI Slave Data Register
160
Table 17.9 - SPIS_RX_FIFO_COUNT - SPI Slave RX FIFO Count Register
160
Table 18.1 - Overview of I2C Master Registers
161
18.1 Register Summary
161
18 I2C Master
161
Table 18.2 - I2CM_SLV_ADDR - Slave Address Register
162
Table 18.3 - I2CM_CNTL - Control Register
162
18.2 Register Details
162
I2CM_CNTL - Control Register (Address Offset: 0X01)
162
I2CM_SLV_ADDR - Slave Address Register (Address Offset: 0X00)
162
I2CM_STATUS - Status Register (Address Offset: 0X01)
163
I2CM_DATA - Receive / Transmit Data Register (Address Offset: 0X02)
163
I2CM_TIME_PERIOD - Timer Period Register (Address Offset: 0X03)
163
Table 18.4 - I2CM_STATUS - Status Register
163
Table 18.5 - I2CM_DATA - Receive / Transmit Data Register
163
Table 18.6 - I2CM_TIME_PERIOD - Timer Period Register
163
Table 18.9 - I2CM_FIFO_INT_ENABLE - FIFO Mode Interrupt Enable
164
Table 18.8 - I2CM_FIFO_LEN - FIFO Mode Byte Length
164
I2CM_FIFO_INT_ENABLE - FIFO Mode Interrupt Enable (Address Offset: 0X05)
164
Table 18.7 - I2CM_HS_TIME_PERIOD - High Speed Timer Period Register
164
I2CM_FIFO_LEN - FIFO Mode Byte Length (Address Offset: 0X04)
164
I2CM_HS_TIME_PERIOD - High Speed Timer Period Register (Address Offset: 0X03)
164
I2CM_FIFO_INT_PEND - FIFO Mode Interrupt Pending (Address Offset: 0X06)
165
I2CM_FIFO_DATA - FIFO Data Register (Address Offset: 0X07)
165
I2CM_TRIG - Trigger Register (Address Offset: 0X08)
165
Table 18.10 - I2CM_FIFO_INT_PEND - FIFO Mode Interrupt Pending
165
Table 18.11 - I2CM_FIFO_DATA - FIFO Data Register
165
Table 18.12 - I2CM_TRIG - Trigger Register
165
Table 19.1 - Overview of I2C Master Registers
166
19 I2C Slave
166
19.1 Register Summary
166
19.2 Register Details
167
I2CS_OWN_ADDR - Own Address Register (Address Offset: 0X00)
167
I2CS_CNTL - Control Register (Address Offset: 0X01)
167
I2CS_STATUS - Status Register (Address Offset: 0X01)
167
Table 19.2 - I2CS_OWN_ADDR - Own Address Register
167
Table 19.3 - I2CS_CNTL - Control Register
167
Table 19.7 - I2CS_FIFO_INT_ENABLE - FIFO Mode Interrupt Enable
168
Table 19.6 - I2CS_FIFO_LEN - FIFO Mode Byte Length
168
Table 19.5 - I2CS_DATA - Receive / Transmit Data Register
168
Table 19.4 - I2CS_STATUS - Status Register
168
I2CS_FIFO_INT_ENABLE - FIFO Mode Interrupt Enable (Address Offset: 0X05)
168
I2CS_FIFO_LEN - FIFO Mode Byte Length (Address Offset: 0X04)
168
I2CS_DATA - Receive / Transmit Data Register (Address Offset: 0X02)
168
I2CS_FIFO_INT_PEND - FIFO Mode Interrupt Pending (Address Offset: 0X06)
169
I2CS_FIFO_DATA - FIFO Data Register (Address Offset: 0X07)
169
I2CS_TRIG - Trigger Register (Address Offset: 0X08)
169
Table 19.8 - I2CS_FIFO_INT_PEND - FIFO Mode Interrupt Pending
169
Table 19.9 - I2CS_FIFO_DATA - FIFO Data Register
169
Table 19.10 - I2CS_TRIG - Trigger Register
169
Table 20.1 - Overview of RTC Registers
170
Table 20.3 - RTC_CMR - Counter Match Register
170
Table 20.2 - RTC_CCVR - Current Counter Value Register
170
20.2 Register Details
170
RTC_CMR - Counter Match Register (Address Offset: 0X04)
170
20.1 Register Summary
170
RTC_CCVR - Current Counter Value Register (Address Offset: 0X00)
170
20 Rtc
170
Table 20.4 - RTC_CLR - Counter Load Register
171
RTC_CLR - Counter Load Register (Address Offset: 0X08)
171
Table 20.5 - RTC_CCR - - Counter Control Register
171
Table 20.7 - RTC_RSTAT - Interrupt Raw Status Register
171
RTC_RSTAT - Interrupt Raw Status Register (Address Offset: 0X14)
171
RTC_STAT - Interrupt Status Register (Address Offset: 0X10)
171
RTC_CCR - Counter Control Register (Address Offset: 0X0C)
171
Table 20.6 - RTC_STAT - Interrupt Status Register
171
RTC_EOI - End of Interrupt Register (Address Offset: 0X18)
172
RTC_COMP_VERSION - Component Version Register (Address Offset: 0X1C)
172
Table 20.8 - RTC_EOI - End of Interrupt Register
172
Table 20.9 - RTC_COMP_VERSION - Component Version Register
172
21 Pwm
173
Register Summary
173
Table 21.34 - PWM_INTMASK - PWM Interrupt Mask Register
174
Table 21.1 - Overview of PWM Registers
175
Table 21.2 - PWM_CTRL0 - PCM Control Register
175
PWM_CTRL1 - PWM Control Register (Address Offset: 0X01)
175
21.2 Register Details
175
PWM_CTRL0 - PCM Control Register (Address Offset: 0X00)
175
PWM_PRESCALER - PWM Prescaler Register (Address Offset: 0X02)
176
PWM_CNTL - PWM Counter Register (LSB) (Address Offset: 0X03)
176
PWM_CNTH - PWM Counter Register (MSB) (Address Offset: 0X04)
176
PWM_CMP0L - Comparator 0 Value Register (LSB) (Address Offset: 0X05)
176
Table 21.3 - PWM_CTRL1 - PWM Control Register
176
Table 21.4 - PWM_PRESCALER - PWM Prescaler Register
176
Table 21.5 - PWM_CNTL - PWM Counter Register (LSB)
176
Table 21.6 - PWM_CNTH - PWM Counter Register (MSB)
176
Table 21.7 - PWM_CMP0L - Comparator 0 Value Register (LSB)
176
PWM_CMP3H - Comparator 3 Value Register (MSB) (Address Offset: 0X0C)
177
Table 21.10 - PWM_CMP1H - Comparator 1 Value Register (MSB)
177
Table 21.9 - PWM_CMP1L - Comparator 1 Value Register (LSB)
177
Table 21.8 - PWM_CMP0H - Comparator 0 Value Register (MSB)
177
PWM_CMP1L - Comparator 1 Value Register (LSB) (Address Offset: 0X07)
177
PWM_CMP3L - Comparator 3 Value Register (LSB) (Address Offset: 0X0B)
177
PWM_CMP2H - Comparator 2 Value Register (MSB) (Address Offset: 0X0A)
177
PWM_CMP2L - Comparator 2 Value Register (LSB) (Address Offset: 0X09)
177
PWM_CMP1H - Comparator 1 Value Register (MSB) (Address Offset: 0X08)
177
PWM_CMP0H - Comparator 0 Value Register (MSB) (Address Offset: 0X06)
177
Table 21.17 - PWM_CMP5L - Comparator 5 Value Register (LSB)
178
Table 21.16 - PWM_CMP4H - Comparator 4 Value Register (MSB)
178
PWM_CMP6H - Comparator 6 Value Register (MSB) (Address Offset: 0X12)
178
PWM_CMP7L - Comparator 7 Value Register (LSB) (Address Offset: 0X13)
178
Table 21.15 - PWM_CMP4L - Comparator 4 Value Register (LSB)
178
PWM_CMP6L - Comparator 6 Value Register (LSB) (Address Offset: 0X11)
178
PWM_CMP5L - Comparator 5 Value Register (LSB) (Address Offset: 0X0F)
178
PWM_CMP4H - Comparator 4 Value Register (MSB) (Address Offset: 0X0E)
178
PWM_CMP4L - Comparator 4 Value Register (LSB) (Address Offset: 0X0D)
178
PWM_CMP5H - Comparator 5 Value Register (MSB) (Address Offset: 0X10)
178
PWM_TOGGLE4 - Channel 4 out Toggle Comparator Mask Register (Address Offset: 0X19)
179
Table 21.25 - PWM_TOGGLE2 - Channel 2 out Toggle Comparator Mask Register
179
Table 21.23 - PWM_TOGGLE0 - Channel 0 out Toggle Comparator Mask
179
Table 21.22 - PWM_CMP7H - Comparator 7 Value Register (MSB)
179
Table 21.24 - PWM_TOGGLE1 - Channel 1 out Toggle Comparator Mask
179
PWM_TOGGLE3 - Channel 3 out Toggle Comparator Mask Register (Address Offset: 0X18)
179
PWM_TOGGLE1 - Channel 1 out Toggle Comparator Mask Register (Address Offset: 0X16)
179
PWM_CMP7H - Comparator 7 Value Register (MSB) (Address Offset: 0X14)
179
PWM_TOGGLE0 - Channel 0 out Toggle Comparator Mask Register (Address Offset: 0X15)
179
PWM_TOGGLE2 - Channel 2 out Toggle Comparator Mask Register (Address Offset: 0X17)
179
Table 21.28 - PWM_TOGGLE5 - Channel 5 out Toggle Comparator Mask Register
180
Table 21.31 - PWM_OUT_CLR_EN - PWM out Clear Enable Register
180
Table 21.30 - PWM_TOGGLE7 - Channel 7 out Toggle Comparator Mask Register
180
Table 21.29 - PWM_TOGGLE6 - Channel 6 out Toggle Comparator Mask Register
180
PWM_OUT_CLR_EN - PWM out Clear Enable Register (Address Offset: 0X1D)
180
PWM_INIT - PWM Initialization Register (Address Offset: 0X1F)
180
PWM_CTRL_BL_CMP8 - Control Block CMP8 Value Register (Address Offset: 0X1E)
180
PWM_TOGGLE7 - Channel 7 out Toggle Comparator Mask Register (Address Offset: 0X1C)
180
PWM_TOGGLE6 - Channel 6 out Toggle Comparator Mask Register (Address Offset: 0X1B)
180
PWM_TOGGLE5 - Channel 5 out Toggle Comparator Mask Register (Address Offset: 0X1A)
180
Table 21.35 - PWM_INTSTATUS - PWM Interrupt Status Register
181
Table 21.36 - PWM_SAMPLE_FREQ_H - PWM Data Sampling Frequency High Byte Register
181
21.2.35 PWM_SAMPLE_FREQ_H - PWM Data Sampling Frequency High Byte Register
181
Offset: 0X22)
181
PWM_INTSTATUS - PWM Interrupt Status Register (Address Offset: 0X21)
181
PWM_INTMASK - PWM Interrupt Mask Register (Address Offset: 0X20)
181
PWM_SAMPLE_FREQ_L - PWM Data Sampling Frequency Low Byte Register (Address Offset: 0X23)
182
PCM_VOLUME - PCM Volume Register (Address Offset: 0X24)
182
PWM_BUFFER - PCM Buffer Register (Address Offset: 0X3C)
182
Table 21.37 - PWM_SAMPLE_FREQ_L - PWM Data Sampling Frequency Low Byte Register
182
Table 21.38 - PCM_VOLUME - PCM Volume Register
182
Table 21.39 - PWM_BUFFER - PCM Buffer Register
182
DCAP_REG1 - Data Capture Interface Register 1 (Address Offset: 0X00)
183
Table 22.2 - DCAP_REG1 - Data Capture Interface Register 1
183
Table 22.1 - Overview of Data Capture Interface Registers
183
Register Details
183
Register Summary
183
Data Capture Interface
183
DCAP_REG2 - Data Capture Interface Register 2 (Address Offset: 0X04)
184
DCAP_REG3 - Data Capture Interface Register 3 (Address Offset: 0X08)
184
DCAP_REG4 - Data Capture Interface Register 4 (Address Offset: 0X0C)
184
Table 22.3 - DCAP_REG2 - Data Capture Interface Register 2
184
Table 22.4 - DCAP_REG3 - Data Capture Interface Register 3
184
Table 22.5 - DCAP_REG4 - Data Capture Interface Register 4
184
Flash Controller
185
Register Summary
185
Table 23.2 - RSADDR1 - Memory Start Address Register (LSB)
186
Table 23.4 - RSADDR2 - Memory Start Address Register (MSB)
186
Table 23.3 - RSADDR1 - Memory Start Address Register (Byte 1)
186
23.2 Register Details
186
Table 23.1 - Overview of Data Capture Interface Registers
186
RSADDR1 - Memory Start Address Register (Byte 1) (Address Offset: 0X01)
186
RSADDR0 - Memory Start Address Register (LSB) (Address Offset: 0X00)
186
RSADDR2 - Memory Start Address Register (MSB) (Address Offset: 0X02)
186
BLENGTH2 - Data Byte Length Register (MSB) (Address Offset: 0X08)
187
Table 23.8 - BLENGTH0 - Data Byte Length Register (LSB) (LSB)
187
Table 23.7 - FSADDR2 - Flash Start Address Register (MSB)
187
Table 23.5 - FSADDR0 - Flash Start Address Register (LSB)
187
Table 23.6 - FSADDR1 - Flash Start Address Register (Byte 1)
187
BLENGTH1 - Data Byte Length Register (Byte 1) (Address Offset: 0X07)
187
BLENGTH0 - Data Byte Length Register (LSB) (Address Offset: 0X06)
187
FSADDR2 - Flash Start Address Register (MSB) (Address Offset: 0X05)
187
FSADDR1 - Flash Start Address Register (Byte 1) (Address Offset: 0X04)
187
FSADDR0 - Flash Start Address Register (LSB) (Address Offset: 0X03)
187
COMMAND - Command Register (Address Offset: 0X09)
188
SEMAPHORE - Semaphore Register (Address Offset: 0X0B)
188
CONFIG - Configuration Register (Address Offset: 0X0C)
188
Table 23.11 - COMMAND - Command Register
188
Table 23.12 - SEMAPHORE - Semaphore Register
188
Table 23.13 - CONFIG - Configuration Register
188
Table 23.17 - CHIPID0 - Chip ID Register (LSB)
189
Table 23.16 - CRCH - Flash Content CRC Register (MSB)
189
Table 23.15 - CRCL - Flash Content CRC Register (LSB)
189
CHIPID0 - Chip ID Register (LSB) (Address Offset: 0X7C)
189
Table 23.14 - STATUS - Status Register
189
CRCL - Flash Content CRC Register (LSB) (Address Offset: 0X0E)
189
STATUS - Status Register (Address Offset: 0X0D)
189
CRCH - Flash Content CRC Register (MSB) (Address Offset: 0X0F)
189
Table 23.18 - CHIPID1 - Chip ID Register (Byte 1)
190
Table 23.21 - DRWDATA - Data Register
190
Table 23.19 - CHIPID2 - Chip ID Register (Byte 2)
190
Table 23.20 - CHIPID3 - Chip ID Register (MSB)
190
23.3 Flash Controller Commands
190
DRWDATA - Data Register (Address Offset: 0X80)
190
CHIPID3 - Chip ID Register (MSB) (Address Offset: 0X7F)
190
CHIPID2 - Chip ID Register (Byte 2) (Address Offset: 0X7E)
190
CHIPID1 - Chip ID Register (Byte 1) (Address Offset: 0X7D)
190
Table 23.22 - Flash Controller Command Group 1
192
Table 23.23 - Flash Controller Command Group 2
194
24 Contact Information
195
Appendix A - References
196
Document References
196
Acronyms and Abbreviations
196
Appendix B - List of Tables & Figures List of Tables
198
Appendix B - List of Tables & Figures
198
List of Tables
198
List of Figures
209
Appendix C - Revision History
210
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