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Bridgetek FT900 User Manual

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Application Note
AN_324
FT900 User Manual
Version 1.3
Issue Date: 29-08-2023
This document provides details about the peripherals of the FT900 as well as
the general system registers.
Use of Bridgetek devices in life support and/or safety applications is entirely at the user's risk, and
the user agrees to defend, indemnify and hold Bridgetek harmless from any and all damages,
claims, suits or expense resulting from such use.
Bridgetek Pte Ltd (BRT Chip)
1 Tai Seng Avenue, Tower A #03-05 Singapore 536464
Tel: +65 6547 4827
Web Site:
http://www.brtchip.com
Copyright © Bridgetek Pte Ltd

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Summary of Contents for Bridgetek FT900

  • Page 1 This document provides details about the peripherals of the FT900 as well as the general system registers. Use of Bridgetek devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold Bridgetek harmless from any and all damages, claims, suits or expense resulting from such use.

  • Page 2: Table Of Contents

    Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table of Contents 1 Introduction .............. 14 2 FT900 System Architecture ........15 2.1 Architecture Overview ............15 2.2 Memory Organization ............16 2.3 FT900 Boot Control ............. 16 2.4 Debugging Support ............. 17 3 Register Map .............
  • Page 3 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 6.2 Register Details ..............41 6.2.1 IRQ00-03 Assignment Register (address offset: 0x00) ..........41 6.2.2 IRQ04-07 Assignment Register (address offset: 0x04) ..........41 6.2.3 IRQ08-11 Assignment Register (address offset: 0x08) ..........41 6.2.4 IRQ12-15 Assignment Register (address offset: 0x0C) ...........
  • Page 4 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 8.4.1 Vendor Specific IO Control Register (address offset: 0x54) ........56 8.4.2 Vendor Specific Status Register (address offset: 0x58) ........... 56 8.4.3 Test Register (address offset: 0x50)..............56 8.4.4 HC_RSRV1 - Reserved 1 Register (address offset: 0x70) ........
  • Page 5 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 10.2 Register Details ..............68 10.2.1 ETH_INT_STATUS – Interrupt Status Register (address offset: 0x0) ....... 68 10.2.2 ETH_INT_ENABLE – Interrupt Enable Register (address offset: 0x1) ....... 69 10.2.3 ETH_RX_CNTL –...
  • Page 6 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 11.2.8 CAN_BUS_TIM_1 – Bus Timing 1 Register (address offset: 0x07) ......81 11.2.9 CAN_TX_BUF - Transmit Buffer Register ............. 82 11.2.10 CAN_RX_BUF - Receive Buffer Register ............. 83 11.2.11 CAN Acceptance Filter ..................
  • Page 7 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.21 SDH_ERR_INT_SGNL_ENABLE – Error Interrupt Signal Enable Register (address offset: 0x3A) ......................102 12.2.22 SDH_AUTO_CMD12_ERR_STATUS – Auto CMD12 Error Status Register (address offset: 0x3C) ......................102 12.2.23 SDH_HOST_CNTL_2 –...
  • Page 8 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.54 SDH_CPR_MOD_CNTL – Cipher Mode Control Register (address offset: 0x180) ..113 12.2.55 SDH_CPR_MOD_STATUS – Cipher Mode Status Register (address offset: 0x184) .. 115 12.2.56 SDH_CPR_MOD_STATUS_EN – Cipher Mode Status Enable Register (address offset: 0x188) ........................
  • Page 9 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 13.5 950 COMPATIBLE REGISTERS ......... 132 13.5.1 UART_ASR - Additional Status Register (address offset: 0x01) ......132 13.5.2 UART_RFL - Receiver FIFO Level Register (address offset: 0x03) ......132 13.5.3 UART_TFL - Transmitter FIFO Level Register (address offset: 0x04) ......
  • Page 10 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 14.2.7 TIMER_SELECT - Timers A..D Select Register (address offset: 0x06) ..... 144 14.2.8 TIMER_WDG - Watchdog Start Value (address offset: 0x07) ......... 144 14.2.9 TIMER_WRITE_LS - Timer A..D Start Value 7:0 (address offset: 0x08) ....145 14.2.10 TIMER_WRITE_MS - Timer A..D Start Value 15:8 (address offset: 0x09) ....
  • Page 11 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 17.2.1 SPIS_CNTL – Control Register (address offset: 0x00) .......... 157 17.2.2 SPIS_STATUS – Status Register (address offset: 0x04) ........157 17.2.3 SPIS_DATA – Receiver and Transmitter Data Registers (address offset: 0x08) ..158 17.2.4 SPIS_SLV_SEL_CNTL –...
  • Page 12 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 19.2.9 I2CS_TRIG - Trigger Register (address offset: 0x08) ........... 168 20 RTC ............... 169 20.1 Register Summary ............169 20.2 Register Details ............... 169 20.2.1 RTC_CCVR - Current Counter Value Register (address offset: 0x00) ...... 169 20.2.2 RTC_CMR - Counter Match Register (address offset: 0x04) ........
  • Page 13 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 21.2.20 PWM_CMP7L - Comparator 7 Value Register (LSB) (address offset: 0x13) .... 177 21.2.21 PWM_CMP7H - Comparator 7 Value Register (MSB) (address offset: 0x14) ... 178 21.2.22 PWM_TOGGLE0 - Channel 0 OUT Toggle Comparator Mask Register (address offset:...
  • Page 14 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 23.2 Register Details ............... 185 23.2.1 RSADDR0 – Memory Start Address Register (LSB) (address offset: 0x00) ....185 23.2.2 RSADDR1 – Memory Start Address Register (Byte 1) (address offset: 0x01)... 185 23.2.3 RSADDR2 –...

  • Page 15: Introduction

    Clearance No.: BRT#081 1 Introduction FT900 is a programmable System-on-Chip device with a 12132-bit general purpose embedded microprocessor core and a plethora of connectivity options. It has been developed for high speed, data bridging tasks. With a parallel data capture interface, 10/100 Base-TX Ethernet interface, CAN bus, and USB 2.0 Hi-Speed peripheral and host ports, this device offers excellent interconnect...

  • Page 16: Ft900 System Architecture

    2 FT900 System Architecture 2.1 Architecture Overview The FT900 core contains the 32-bit CPU (FT32), with control logic, flash memory and RAM. The flash memory size is 256 KB. The RAM consists of 256 KB shadow program memory and 64 KB data memory.

  • Page 17: 2.2 Memory Organization

    Interrupt vector 32 (NMI) 0x8C Program entry point Table 2.1 - FT900 Program Memory Organization 2.3 FT900 Boot Control Upon reset, boot control takes control of the memory buses and puts the CPU in a reset state. It automatically transfers the data from the flash memory to the CPU program memory, starting from address 0 on both sides.

  • Page 18: 2.4 Debugging Support

    FT900 bootloader. The protocol used for debugging is the GDB remote protocol and a port of GDB is available in the Bridgetek FT9XX Toolchain. The GDB serial debug protocol commands are interpreted by a debug interpreter in the bootloader.

  • Page 19: Register Map

    This section lists the I/O map for registers / memory in the device. Please note that some peripherals are not available on some models in the FT900 series. The details can be found in the table below. An (X) indicates that the peripheral exists and a minus (-) indicates that the peripheral is not available.

  • Page 20: Notations

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 4 Notations These notations are used in the register descriptions: Terms Description Reserved Do not read/write the location Read-only Read-only / Clear-when-read Read- and Write-able...

  • Page 21: General System Registers

    Document Reference No.: BRT_000131 Clearance No.: BRT#081 5 General System Registers This section describes the registers that govern the general behavior of the FT900. 5.1 Register Summary Listed below are the registers with their offset from the base address (0x10000). All registers can be accessed via Byte (8-bit), Word (16-bit) or Double-Word (32-bit) mode.

  • Page 22: Table 5.1 - Overview Of General System Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0x60 GPIO 00 – 07 Configuration Register 0x00000000 Section 5.2.9.1 0x64 GPIO 08 – 15 Configuration Register 0x00000000 Section 5.2.9.2 0x68 GPIO 16 – 23 Configuration Register 0x00000000 Section 5.2.9.3...

  • Page 23: 5.2 Register Details

    LSBs (XXXX) shows the revision of the chip. Table 5.2 - CHIPID - Chip ID Register For revision 0001 of the FT900 series, the pre-configured bits of the chip ID register (CHIPID) and the chip configuration register (EFCFG, section 5.2.2) for different models are listed in in the table...

  • Page 24: Clkcfg - Clock Configuration Register (Address Offset: 0X08)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value If set, FLASH write/erase to bytes 196608 – FLASH_WR_B3_ENA 262143 is allowed; otherwise, it is permanently non-writable/non-erasable. If set, FLASH write/erase to bytes 131072 –...

  • Page 25: Pmcfg - Power Management Register (Address Offset: 0X0C)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.4 PMCFG - Power Management Register (address offset: 0x0C) Default Name Type Description Value 31:26 Reserved PM_GPIO_IRQ_PEND RW1C GPIO interrupt during system shut down with clock not running...

  • Page 26: Ptstnset - Test & Set Register (Address Offset: 0X10)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value this bit will force the PM to check for host connection activities regardless. Normally USB device activity detection is performed only when required; setting...

  • Page 27: Msc0Cfg - Miscellaneous Configuration Register (Address Offset: 0X18)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.7 MSC0CFG - Miscellaneous Configuration Register (address offset: 0x18) Default Name Type Description Value PERI_SOFTRESET RWAC Write 1 to cause soft reset to all peripherals. It is automatically cleared.
  • Page 28 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value for EHCI to complete its reset (~200ms). HOST_RESET_EHCI RWAC Write 1 to cause USB Host EHCI reset; it is automatically cleared immediately.

  • Page 29: Gpio Pin Configuration Registers (Address Offset: 0X1C - 0X5F)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value BCDDEV_DCP_FOUND 1: DCP detected Table 5.9 - MSC0CFG - Miscellaneous Configuration Register 5.2.8 GPIO Pin Configuration Registers (address offset: 0x1C – 0x5F) These registers control the pin configurations.

  • Page 30: Table 5.15 - Pin 16 - 19 Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.8.2 Pin 04 – 07 Register (address offset: 0x20) Pin Functionality Bits Default Name Type Value 31:24 PIN07_CFG 8’h04 GPIO 7 Cam Pclk 23:16 PIN06_CFG 8’h04...

  • Page 31: Table 5.19 - Pin 32 - 35 Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.8.7 Pin 24 – 27 Register (address offset: 0x34) Default Pin Functionality Bits Name Type Value 31:24 PIN27_CFG 8’h04 GPIO 27 SPIM SCK 23:16 PIN26_CFG 8’h04...

  • Page 32: Table 5.23 - Pin 48 - 51 Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.8.12 Pin 44 – 47 Register (address offset: 0x48) Pin Functionality Bits Default (note that I2C Master & Slave pads can be swopped) Name Type...

  • Page 33: Gpio Configuration Registers (Address Offset: 0X60 - 0X83)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.8.17 Pin 64 – 66 Register (address offset: 0x5C) Default Pin Functionality Bits Name Type Value 31:24 Reserved 8’h04 23:16 PIN66_CFG 8’h04 GPIO 66 I2SM CLK24...

  • Page 34: Table 5.32 - Gpio 24 - 31 Configuration Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.9.1 GPIO 00 – 07 Configuration Register (address offset: 0x60) Name Type Default Value Description 31:28 GPIO07_CFG For GPIO 7 27:24 GPIO06_CFG For GPIO 6...

  • Page 35: Table 5.36 - Gpio 56 - 63 Configuration Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 15:12 GPIO35_CFG For GPIO 35 11:8 GPIO34_CFG For GPIO 34 GPIO33_CFG For GPIO 33 GPIO32_CFG For GPIO 32 Table 5.33 - GPIO 32 – 39 Configuration Register 5.2.9.6...

  • Page 36: Gpio Value Registers (Address Offset: 0X84 - 0X8F)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.10 GPIO Value Registers (address offset: 0x84 – 0x8F) These registers contain the values for the GPIO pins. Each register contains the value of 32 digital pins except the last register, which only contains the value of 3 pins (64 to 66).

  • Page 37: Interrupt Pending Registers (Address Offset: 0X9C - 0Xa7)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 5.2.12 Interrupt Pending Registers (address offset: 0x9C – 0xA7) These registers hold the interrupt pending flags for the GPIO pins. Each register holds the flags for 32 digital pins except the last register, which only holds the flags for 3 pins (64 to 66).

  • Page 38: Eth_Phy_Id - Ethernet Phy Id Register (Address Offset: 0Xac)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 MAC clock) Reserved ETHERNET_PHYAD Ethernet PHY Address Table 5.47 - ETH_PHY_CFG - Ethernet PHY Miscellaneous Configuration Register 5.2.14 ETH_PHY_ID - Ethernet PHY ID Register (address offset: 0xAC)

  • Page 39: Dac_Adc_Cnt - Adc/Dac Count Register (Address Offset: 0Xb4)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description 6: Channel 5 selected 7: Channel 6 selected Write 1 to start DAC 0 conversion. When DAC_CONT1 is not set, this bit...

  • Page 40: Dac_Adc_Data - Adc/Dac Data Register (Address Offset: 0Xb8)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value conversion in the DAC 0 FIFO. The FIFO contains at most DAC_DATA_COUNT0 samples for conversion Table 5.50 - DAC_ADC_CNT - ADC/DAC Count Register 5.2.17 DAC_ADC_DATA - ADC/DAC Data Register (address offset: 0xB8)

  • Page 41: Interrupt Controller

    The interrupt controller takes in 32 interrupts, and based on the interrupt priorities assigned generates the interrupt to the FT900 together with an ISR address. Nested interrupts are allowed if enabled. By default, it is disabled. Up to 16 levels of nesting is allowed which defaults to only 1 level if nesting is enabled.

  • Page 42: 6.2 Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Address Register Default Value References Offset 0x00 IRQ00-03 Assignment Register 0x03020100 Section 6.2.1 0x04 IRQ04-07 Assignment Register 0x07060504 Section 6.2.2 0x08 IRQ08-11 Assignment Register 0x0B0A0908 Section 6.2.3...

  • Page 43: Irq12-15 Assignment Register (Address Offset: 0X0C)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 20:16 PR10ASSIGN 5’h0A Priority assignment for interrupt 10 15:13 Reserved 12:8 PR09ASSIGN 5’h09 Priority assignment for interrupt 9 Reserved PR08ASSIGN 5’h08 Priority assignment for interrupt 8 Table 6.5 - IRQ08-11 Assignment Register...

  • Page 44: Irq28-31 Assignment Register (Address Offset: 0X1C)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 20:16 PR26ASSIGN 5’h1A Priority assignment for interrupt 26 15:13 Reserved 12:8 PR25ASSIGN 5’h19 Priority assignment for interrupt 25 Reserved PR24ASSIGN 5’h18 Priority assignment for interrupt 24 Table 6.9 - IRQ24-27 Assignment Register...

  • Page 45: Efuse

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 7 EFUSE 7.1 Introduction The EFUSE is the only way to modify the content of the Chip Configuration Register. There are 64 bits in the EFUSE, in which the lower 32 bits correspond to the 32 bits in the register.

  • Page 46: Table 7.1 - Efuse Bits

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Description Each bit corresponds 16kB of FLASH location, with bit 0 referring to locations 0-16383. When set the data residing in the said FLASH locations are not...

  • Page 47: Usb Host

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 8 USB Host This is a single -port USB host controller which is compliant with the USB 2.0 specification and compatible with the Enhanced Host Controller Interface (EHCI) specification. It supports HS/FS/LS transactions, control/bulk/interrupt/isochronous transfers and split-transaction of the hub.

  • Page 48: 8.2 Ehci Operational Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0x74 HC_RSRV2 Reserved 2 Register 0x00000000 Section 8.4.5 Table 8.1 - Overview of USB Host Controller Registers 8.2 EHCI Operational Registers 8.2.1 HC Capability Register (address offset: 0x00) This register has information on the host controller interface specification number implemented in this host controller.

  • Page 49: Usbcmd - Hc Usb Command Register (Address Offset: 0X10)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value When this bit is set to 1, the system software can specify and use a smaller frame list and configure the host controller via Frame List Size field of the USBCMD register.

  • Page 50: Usbsts - Hc Usb Status Register (Address Offset: 0X14)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value This controls whether the host controller skips the processing of asynchronous schedule. 0: Do not process the asynchronous schedule 1: Use the ASYNCLISTADDR register to access...

  • Page 51: Usbintr - Hc Usb Interrupt Enable Register (Address Offset: 0X18)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description Interrupt on Async Advance INT_OAA RW1C 1’b0 This bit indicates the assertion of interrupt on Async Advance Doorbell Host System Error...

  • Page 52: Frindex - Hc Frame Index Register (Address Offset: 0X1C)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value controller will issue an interrupt at the next interrupt threshold. USB Error Interrupt Enable When this is 1 and the USBERRINT bit in the USBERR_INT_EN 1’b0...

  • Page 53: Portsc - Hc Port Status And Control Register (Address Offset: 0X30)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 the next asynchronous queue head to be executed. These form the upper 27 bits of the address. Reserved Table 8.10 - ASYNCLISTADDR – HC Current Asynchronous List Address Register 8.2.10 PORTSC –...

  • Page 54: 8.3 Configuration Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description controller will unconditionally set this to 0 when: The software sets Force Port Resume bit to 0 (from 1) The software sets Port Reset bit to 1 (from 0) Note: Before setting this bit, Run/Stop bit should be set to 0.
  • Page 55 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value draws the minimal power from the power supplies. This is part of the power management. EOF 2 Timing Points Control EOF2 timing point before next SOF.

  • Page 56: Bus Monitor Control / Status Register (Address Offset: 0X40)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value Asynchronous Schedule Sleep Timer Controls the Asynchronous Schedule sleep timer. 5 us ASYN_SCH_SLPT 2’h1 10 us 15 us 20 us Table 8.12 - EOF Time &...

  • Page 57: 8.4 Usb Host Testing Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 8.4 USB Host Testing Registers 8.4.1 Vendor Specific IO Control Register (address offset: 0x54) Name Type Default Value Description 31:6 Reserved Vendor-Specific Test Mode Control Load This controls the active low output U_VCTLOAD_N to the PHY.

  • Page 58: Hc_Rsrv1 - Reserved 1 Register (Address Offset: 0X70)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 8.4.4 HC_RSRV1 - Reserved 1 Register (address offset: 0x70) Default Name Type Description Value 31:0 Reserved Table 8.18 - HC_RSRV1 - Reserved 1 Register 8.4.5 HC_RSRV2 - Reserved 2 Register (address offset: 0x74)

  • Page 59: Usb Peripheral

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 9 USB Peripheral This is a USB device controller fully compliant with the USB 2.0 specification. It supports a control end point - End Point 0 (EP0) - and up to 7 other End Points (EP1-7).
  • Page 60 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0x45 DC_EP2_BUFFER_LENGTH_MSB – Endpoint 2 0x00 Section 9.4.4 Buffer Length MSB Register 0x48 DC_EP2_BUFFER – Endpoint 2 Buffer Register 0x00 Section 9.4.5 0x4C DC_EP3_CONTROL – Endpoint 3 Control Register 0x00 Section 9.4.1...

  • Page 61: 9.2 Initialization Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Buffer Length MSB Register 0x98 DC_EP7_BUFFER – Endpoint 7 Buffer Register 0x00 Section 9.4.5 General Registers 0x00 DC_INT_STATUS – Interrupt Status Register 0x00 Section 9.5.1 0x04 DC_EP_INT_STATUS –...

  • Page 62: Dc_Int_Enable - Interrupt Enable Register (Address Offset: 0X08)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 USB function enables. Setting this to 1 USB_DEV_EN 1’b0 enables the USB device Table 9.3 - DC_MODE – Mode Register 9.2.3 DC_INT_ENABLE – Interrupt Enable Register (address offset: 0x08) This register enables the different interrupt sources by writing a 1 to the corresponding bit.

  • Page 63: Dc_Ep0_Status - Endpoint 0 Status Register (Address Offset: 0X20)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description Reserved Endpoint Maximum packet size 2’h0: 8 bytes EP_SIZE 2’h0 2’h1: 16 bytes 2’h2: 32 bytes 2’h3: 64 bytes Send STALL...

  • Page 64: Dc_Ep0_Buffer - Endpoint 0 Buffer Register (Address Offset: 0X28)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value Reserved Indicates the number of data bytes received. BUF_LEN 7’h00 Valid only if OUT_PKT_RDY is 1. Table 9.8 - DC_EP0_BUFFER_LENGTH – Endpoint 0 Buffer Length Register 9.3.4 DC_EP0_BUFFER –...

  • Page 65: Dc_Ep(X)_Status - Endpoint Status Registers (Address Offset: 0X30/0X40/0X50/0X60/0X70/0X80/0X90)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Endpoint Mode. This parameter has to be fixed during the Set Configuration request. 0x0: EP disabled EP_MODE 2’h0 0x1: EP configured for bulk transfers 0x2: EP configured for interrupt transfers 0x3: EP configured for isochronous transfers Endpoint Direction.

  • Page 66: Dc_Ep(X)_Buffer_Length_Lsb - Endpoint Buffer Length Lsb Registers (Address Offset: 0X34/0X44/0X54/0X64/0X74/0X84/0X94)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value Software can clear this bit by writing a 1 to this bit. IN packet ready. Valid only when the Endpoint direction is IN.

  • Page 67: 9.5 General Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 9.5 General Registers 9.5.1 DC_INT_STATUS – Interrupt Status Register (address offset: 0x00) This register indicates that the hardware condition of the corresponding interrupt has occurred.

  • Page 68: 10 Ethernet

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 10 Ethernet This is a MAC core that conforms to the IEEE 802.3-2002 specification with the following features: • Supports 10BASE-T and 100BASE-TX/FX modes •...

  • Page 69: Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0x01 ETH_INT_ENABLE – Interrupt Enable Register 0x00 Section 10.2.2 0x02 ETH_RX_CNTL – Receive Control Register 0x00 Section 10.2.3 0x03 ETH_TX_CNTL – Transmit Control Register 0x00 Section 10.2.4...

  • Page 70: Eth_Int_Enable - Interrupt Enable Register (Address Offset: 0X1)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description Write a 1 to clear the status flag. Set when an error on RX has been encountered. This occurs when the RXER...

  • Page 71: Eth_Rx_Cntl - Receive Control Register (Address Offset: 0X02)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 10.2.3 ETH_RX_CNTL – Receive Control Register (address offset: 0x02) This register configures the receiver. Name Type Default Value Description RX_MEM_SIZE 2’h0 Memory size – 2048 Bytes Reserved 1: clears the receiver FIFO;...

  • Page 72: Eth_Data_N0 - Data Register (Octet N) (Address Offset: 0X04)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 shorter than the minimum frame size 0: padding will not be appended to frames shorter than the minimum frame size 1: enable transmitter TX_ENABLE 1’b0 0: disable transmitter Table 10.6 - ETH_TX_CNTL –...

  • Page 73: Eth_Addr_3 - Address Register (Octet 3) (Address Offset: 0X0A)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 10.2.11 ETH_ADDR_3 – Address Register (octet 3) (address offset: 0x0A) Default Name Type Description Value ADDRESS 8’h00 MAC hardware address octet Table 10.13 - ETH_ADDR_3 – Address Register (octet 3) 10.2.12 ETH_ADDR_4 –...

  • Page 74: Eth_Mng_Div - Management Divider Register (Address Offset: 0X10)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Reserved This bit should be updated together with the START bit. WRITE 1’b0 1: perform write transaction 0: perform read transaction Setting this bit to 1 will initiate the START 1’b0...

  • Page 75: Eth_Mng_Rx0 - Management Receive Data 0 Register (Address Offset: 0X14)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 10.2.21 ETH_MNG_RX0 – Management Receive Data 0 Register (address offset: 0x14) Default Name Type Description Value This is the lower byte of a word of data read RX_LSB 8’h00...

  • Page 76: 11 Can Bus Controller

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 11 CAN Bus Controller Two CAN bus controllers are supported by this device. The controllers have the following features. • Conforms to Bosch CAN 2.0B specification •...

  • Page 77: Table 11.2 - Standard Frames Memory Buffer Layout

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 23:16 UNUSED 31:24 UNUSED Table 11.2 - Standard Frames Memory Buffer Layout The memory buffer layout for extended frames is: Offset Data Bits Extended Frame buffer content for TX/RX RAM...

  • Page 78: 11.1 Register Summary

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 11.1 Register Summary Listed below are the registers with their offset from the base addresses (0x10240 for CAN1 and 0X10260 for CAN2). All registers and buffer locations can only be accessed via Byte (8-bit) mode.

  • Page 79: 11.2 Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Register 0x17 CAN_ACC_MASK_3 – Acceptance Mask 3 0x00 Section 11.2.11.8 Register 0x18 CAN_ERR_CODE – Error Code Capture Register 0x00 Section 11.2.12 0x19 CAN_RX_ERR_CNTR – Receive Error Counter 0x00 Section 11.2.13...

  • Page 80: Can_Status - Status Register (Address Offset: 0X02)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Reserved Table 11.6 - CAN_CMD – Command Register 11.2.3 CAN_STATUS – Status Register (address offset: 0x02) Name Type Default Value Description Receive Buffer Status: RX_BUF_STS 1’b0...

  • Page 81: Can_Int_Status - Interrupt Status Register (Address Offset: 0X03)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 11.2.4 CAN_INT_STATUS – Interrupt Status Register (address offset: 0x03) Name Type Default Value Description Reserved Arbitration Lost Interrupt Set when the CAN core has lost arbitration...

  • Page 82: Can_Rx_Msg - Receive Message Register (Address Offset: 0X05)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 RX_EN 1’b0 Mask for RX interrupt. TX_EN 1’b0 Mask for TX interrupt. BUS_ERR_EN 1’b0 Mask for BUS_ERR interrupt. DATA_OVRN_EN 1’b0 Mask for DATA_OVRN interrupt. Table 11.9 - CAN_INT_ENABLE – Interrupt Enable Register 11.2.6 CAN_RX_MSG –...

  • Page 83: 11.2.9 Can_Tx_Buf - Transmit Buffer Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 1: bus level is sampled three times (recommended for low/medium speed buses where there is a benefit from filtering spikes) Number of clock cycles per Time Segment 2 TIM_SEG2 3’h0...

  • Page 84: 11.2.10 Can_Rx_Buf - Receive Buffer Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 11.2.9.3 CAN_TX_BUF_2 – Transmit Buffer 2 Register (address offset: 0x0A) Default Name Type Description Value This is used to write a CAN frame for transmission. When write is performed on...

  • Page 85: 11.2.11 Can Acceptance Filter

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 11.2.10.3 CAN_RX_BUF_2 – Receive Buffer 2 Register (address offset: 0x0E) Default Name Type Description Value This is used to read a received CAN frame. When read is performed on CAN_RX_BUF_3, DATA 8’h00...

  • Page 86: Table 11.21- Can_Acc_Code_0 - Acceptance Code 0 Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Single Filter Configuration: In single filter configuration, one long filter can be defined (four bytes). If a standard frame message is received, the complete identifier including RTR bit and the first two data bytes (if received) are used for acceptance filtering.

  • Page 87: Table 11.22 - Can_Acc_Code_1 - Acceptance Code 1 Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 ACC_CODE 1’b0 Unused ID14 DATA1[5] ID14 ACC_CODE 1’b0 Unused ID13 DATA1[4] ID13 Table 11.22 - CAN_ACC_CODE_1 – Acceptance Code 1 Register 11.2.11.3 CAN_ACC_CODE_2 – Acceptance Code 2 Register (address offset: 0x12)

  • Page 88: Can_Err_Code - Error Code Capture Register (Address Offset: 0X18)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 11.2.11.7 CAN_ACC_MASK_2 – Acceptance Mask 2 Register (address offset: 0x16) Default Name Type Description Value This register determines which bits in CAN_ACC_CODE_2 is used for the acceptance filter.

  • Page 89: Can_Tx_Err_Cntr - Transmit Error Counter Register (Address Offset: 0X1A)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 11.2.14 CAN_TX_ERR_CNTR – Transmit Error Counter Register (address offset: 0x1A) Name Type Default Value Description This is the low-byte of the current transmit error counter as the width of the transmit error counter is 9-bit.

  • Page 90: 12 Sd Host

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12 SD Host The device supports a SD Host with the following features. • Supports PIO data transfers • Supports configurable SD bus modes: 4-bit mode and 8-bit mode •...
  • Page 91 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Register 0x2C SDH_CLK_GAP_CNTL – Clock Control Register 0x0000 Section 12.2.13 0x2E SDH_TIMEOUT_CNTL – Timeout Control Register 0x00 Section 12.2.14 0x2F SDH_SW_RST – Software Reset Register 0x00 Section 12.2.15...
  • Page 92 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Register 0x6A SDH_PRST_SDR50 – Preset value for SDR50 0x0000 Section 12.2.37 Register 0x6C SDH_PRST_SDR104 – Preset value for SDR104 0x0000 Section 12.2.38 Register 0x6E SDH_PRST_DDR50 – Preset value for DDR50 0x0000 Section 12.2.39...

  • Page 93: 12.2 Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0x1A0 SDH_OUT_DATA_MSB – Output Data MSB 0x00000000 Section 12.2.63 Register 0x1A4 SDH_SCRT_CONS_DATA – Secret Constant 0x00000000 Section 12.2.64 Table Data Port Table 12.1 - Overview of SD Host Registers 12.2 Register Details...

  • Page 94: Sdh_Tnsfer_Mode - Transfer Mode Register (Address Offset: 0X0C)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.5 SDH_TNSFER_MODE – Transfer Mode Register (address offset: 0x0C) The host driver should set this register before issuing the data transfer command or resume command. When in the SDIO transfer, the values of this register should be preserved after the suspend command and should be restored before the resume command.

  • Page 95: Sdh_Response - Response Register (Address Offset: 0X10-0X1C)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value CCCR CMD52 for writing Suspend Bus Suspend in CCCR Normal Other commands Data Present Select 1: indicates that data is present and...

  • Page 96: Sdh_Present_State - Present State Register (Address Offset: 0X24)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.9 SDH_PRESENT_STATE – Present State Register (address offset: 0x24) The host driver can access the status from this read-only register. Default Name Type Description Value...

  • Page 97: Table 12.10 - 11.2.9 Sdh_Present_State - Present State Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value (2) After getting the CRC status of any block where data transmission is stopped by SP_BLK_GAP. A BLK_GAP_EVT interrupt will be generated when SP_BLK_GAP is set to 1 and this bit changes to 0.

  • Page 98: Sdh_Hst_Cntl_1 - Host Control 1 Register (Address Offset: 0X28)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.10 SDH_HST_CNTL_1 – Host Control 1 Register (address offset: 0x28) Name Type Default Value Description Card Detect Signal Selection CD_SEL 1’b0 1: The test level for the card detection...

  • Page 99: Sdh_Clk_Cntl - Clock Control Register (Address Offset: 0X2C)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 1: Stop at block gap request; the host controller will stop at the block gap by using READ_WAIT or stop IO_SD_CLK in a read SP_BLK_GAP 1’b0...

  • Page 100: Sdh_Nrml_Int_Status - Normal Interrupt Status Register (Address Offset: 0X30)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value 31:27 Reserved SOFT_RST_DAT RWAC 1’b0 1: Software reset for data line SOFT_RST_CMD RWAC 1’b0 1: Software reset for command line...

  • Page 101: Sdh_Nrml_Int_Enable - Normal Interrupt Status Enable Register (Address Offset: 0X34)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value Reserved RW1C 1’b0 Write 0 to this bit AUTO_CMD12_ERR RW1C 1’b0 Auto CMD12 error CUR_LIM_ERR RW1C 1’b0 Current limit error...

  • Page 102: Sdh_Err_Int_Enable - Error Interrupt Status Enable Register (Address Offset: 0X36)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 CMD_CMPLT_ST_EN 1’b0 Command Complete status enable Table 12.19 - SDH_NRML_INT_ENABLE – Normal Interrupt Status Enable Register 12.2.19 SDH_ERR_INT_ENABLE – Error Interrupt Status Enable Register (address offset:...

  • Page 103: Sdh_Err_Int_Sgnl_Enable - Error Interrupt Signal Enable Register (Address Offset: 0X3A)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 CARD_INSERT_SIG_EN 1’b0 Card Insert signal enable BUF_RD_RDY_SIG_EN 1’b0 Buffer Read Ready signal enable BUF_WR_RDY_SIG_EN 1’b0 Buffer Write Ready signal enable Reserved 1’b0 Write 0 to this bit BLK_GAP_EVT_SIG_EN 1’b0...

  • Page 104: Sdh_Host_Cntl_2 - Host Control 2 Register (Address Offset: 0X3E)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value 15:8 Reserved Command not executed by Auto CMD_NO_EX_BY_CMD12 1’b0 CMD12 error Reserved AUTO_CMD_IDX_ERR 1’b0 Auto CMD index error AUTO_CMD_END_BIT_ERR 1’b0...

  • Page 105: Sdh_Cap_2 - Capabilities Register 2 (Address Offset: 0X44)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description VOLTAGE_3_3_SUPPORT 1’b1 Voltage supports 3.3V SUSPEND_RESUME_SUPP 0: Suspend / Resume not 1’b0 supported Reserved 1’b1 HI_SPEED_SUPPORT 1’b1 1: High speed supported Reserved 1’b0...

  • Page 106: Sdh_Rsrv_1 - Reserved 1 Register (Address Offset: 0X48)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description SDR104_SUPPORT 1’b0 not supported SDR50_SUPPORT 1’b1 not supported Table 12.26 - SDH_CAP_2 – Capabilities Register 2 12.2.26 SDH_RSRV_1 – Reserved 1 Register (address offset: 0x48)

  • Page 107: Sdh_Force_Evt_Err_Int_Status - Force Event For Error Interrupt Status Register (Address Offset: 0X52)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.29 SDH_FORCE_EVT_ERR_INT_STATUS – Force Event for Error Interrupt Status Register (address offset: 0x52) The Force Event register is not a physical register. It is an address to which the error interrupt status register can be written.

  • Page 108: Sdh_Prst_Dflt_Spd - Preset Value For Default Speed (Address Offset: 0X62)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 10: Driver type C is selected 01: Driver type A is selected 00: Driver type B is selected 13:11 Reserved Clock Generator Select Value The version does not support the CLK_GEN_SEL 1’b0...

  • Page 109: Sdh_Prst_Sdr25 - Preset Value For Sdr25 (Address Offset: 0X68)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 V signalling bus speed modes. This field is meaningless for the 3.3-V signalling. 11: Driver type D is selected 10: Driver type C is selected...

  • Page 110: Sdh_Prst_Sdr104 - Preset Value For Sdr104 (Address Offset: 0X6C)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 00: Driver type B is selected 13:11 Reserved Clock Generator Select Value The version does not support the CLK_GEN_SEL 1’b0 programmable clock generator and is...

  • Page 111: Sdh_Rsrv_5 - Reserved 5 Register (Address Offset: 0Xfc)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Clock Generator Select Value The version does not support the CLK_GEN_SEL 1’b0 programmable clock generator and is fixed to SDCLK Frequency Select Value The 10-bit pre-set value for setting the SDCLK_FREQ_SEL SDCLK Frequency Select in the Clock Control.

  • Page 112: Sdh_Vndr_1 - Vendor-Defined 1 Register (Address Offset: 0X104)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 …. 0x01: Latch value at the 1 0x00: Latch value at SCLK edge Reserved 1: Use the pulse latching function for the read P_LAT_EN 1’b1 data and response.

  • Page 113: Sdh_Vndr_4 - Vendor-Defined 4 Register (Address Offset: 0X110)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Value 31:29 Reserved 28:24 Reserved 5’h1F 23:0 Reserved Table 12.46 - SDH_VNDR_3 – Vendor-defined 3 Register 12.2.46 SDH_VNDR_4 – Vendor-defined 4 Register (address offset: 0x110)

  • Page 114: Sdh_Vndr_8 - Vendor-Defined 8 Register (Address Offset: 0X120)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.50 SDH_VNDR_8 – Vendor-defined 8 Register (address offset: 0x120) Name Type Default Value Description 31:1 Reserved 1: Enable the AHB master AHB_RESP_ERR_STS_EN 1’b0 response error status Table 12.51 - SDH_VNDR_8 –...

  • Page 115: Table 12.55 - Sdh_Cpr_Mod_Cntl - Cipher Mode Control Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description decryption. Change Endianness In this mode, the endianness of the encrypted data will be changed before CH_ENDIAN 1’b0 being written to the TX FIFO.

  • Page 116: Sdh_Cpr_Mod_Status - Cipher Mode Status Register (Address Offset: 0X184)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.55 SDH_CPR_MOD_STATUS – Cipher Mode Status Register (address offset: 0x184) Name Type Default Value Description 31:1 Reserved Cipher is ready When this bit is set to 1, reading 0x19C...

  • Page 117: Sdh_In_Key_Msb - Input Key Msb Register (Address Offset: 0X198)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 12.2.61 SDH_IN_KEY_MSB – Input Key MSB Register (address offset: 0x198) Name Type Default Value Description 31:0 32’h0000_0000 Input port for the input key bits 63:32 Table 12.62 - SDH_IN_KEY_MSB –...

  • Page 118: 13 Uart

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 13 UART The device supports 2 UARTs with the following features: • Software compatible with 16450 ("450"), 16550 (“550”), 16550A (“Extended 550”), 16650 (“650”), 16750 (“750”) and 16C950 (“950”) UARTs •...

  • Page 119: 13.1 Register Summary

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 • Complete status reporting capabilities • False start bit detection • Line-break generation and detection. Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Break, parity, overrun, framing error simulation •...

  • Page 120: Table 13.1 - Overview Of Uart Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 950 COMPATIBLE REGISTERS 0x01 UART_ASR - Additional Status Register 0x00 Section 13.5.1 0x03 UART_RFL - Receiver FIFO Level Register 0x00 Section 13.5.2 0x04 UART_TFL - Transmitter FIFO Level Register 0x00 Section 13.5.3...

  • Page 121: Uart Mode Selection

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 13.2 UART MODE SELECTION The operation of the UART depends on a number of standard mode settings. These modes are referred to throughout this section. The compatibility modes are tabulated below.
  • Page 122 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 650 Mode The 650 mode is active when EFR[4] is set (enhanced mode is enabled). As 650 software drivers usually put the device into enhanced mode, running 650 drivers on the UART device will result in 650 compatibilities with 128 deep FIFO’s, as long as FCR[0] is set.

  • Page 123: 13.3 Standard 550 Compatible Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 13.3 STANDARD 550 COMPATIBLE REGISTERS 13.3.1 UART_RBR - Receiver Buffer Register (address offset: 0x00 and LCR[7] = 0) Default Name Type Description Value DATA 8’h00 FIFO Data Read from RX Buffer Table 13.3 - UART_RBR - Receiver Buffer Register...

  • Page 124: Uart_Int_Status - Interrupt Status Register (Address Offset: 0X02)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 LINE_STS_EN 1’h0 Enable Receiver Line Status Interrupt Enable Transmitter Holding Register Empty TX_EMTY_EN 1’h0 Interrupt RX_AVL_EN 1’h0 Enable Received Data Available Interrupt Table 13.7 - UART_INT_ENABLE - Interrupt Enable Register 13.3.6 UART_INT_STATUS - Interrupt Status Register (address offset: 0x02)

  • Page 125: Uart_Fcr - Fifo Control Register (Address Offset: 0X02)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Interrupt Function UART_INT_S TATUS [5:0] INT TYPE INT Source Level set in 9-bit mode 100000 CTS or RTS change of state When CTS or RTS bits will change Table 13.9 - Interrupt Status Register Software Handling...

  • Page 126: Table 13.11 - Uart_Rcvr - Fifo Trigger Level - 550 Mode

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 RCVR FIFO TRIGGER LEVEL Fcr[7:6] Standard FIFO*mode (16 B) Extended FIFO*mode*(128B) Table 13.11 - UART_RCVR - FIFO Trigger Level – 550 mode * ‐ depends on Ext FIFO enable (FCR(5)) bit value In this mode the transmitter trigger level is equal to 1.

  • Page 127: Uart_Lcr - Line Control Register (Address Offset: 0X03)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 RCVR FIFO TRIGGER LEVEL FCR[7:6] Lower trigger for flow Interrupt trigger and upper trigger for flow control control Table 13.13 - UART_RCVR - FIFO Trigger Level – 650 mode THR TRIG(1:0) ‐...

  • Page 128: Uart_Mcr - Modem Control Register (Address Offset: 0X04)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value 0: parity disabled Number of STOP bits 0: 1 Stop bit generated STOP_BITS 1’h0 1: 1.5 stop bits generated for 5 data bits or 2 STOP...

  • Page 129: Uart_Lsr - Line Status Register (Address Offset: 0X05)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0: the OUT1 output is forced to a logic 1 Request to send 1’h0 1: the RTS output is forced to a logic 0 0: the RTS output is forced to a logic 1 Data Terminal Ready 1’h0...

  • Page 130: Uart_Msr - Modem Status Register (Address Offset: 0X06)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value parity bit is detected as a logic 0 bit (Spacing level). 0: whenever the CPU reads the contents of the Line Status Register.

  • Page 131: Uart_Spr - Spr Register (Address Offset: 0X07)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value is equivalent to DTR in the Modem Control Register. Clear to Send This bit is the complement of the Clear to Send (CTS) input.

  • Page 132: Uart_Xon1 - Xon1 Register (Address Offset: 0X04)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 In‐band transmit flow control mode 00: Disable in‐band flow control 01: Enable single character in‐band transmit flow control. Recognizing XON2 as the XON character IBT_FCM 1’h0...

  • Page 133: 13.5 950 Compatible Registers

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 13.5 950 COMPATIBLE REGISTERS To access these registers ACR[7] must be set to 1. 13.5.1 UART_ASR - Additional Status Register (address offset: 0x01) Name Type...

  • Page 134: Uart_Icr - Icr Register (Address Offset: 0X05)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Note: Reading from this register requires that last value written to LCR was not 0xBF and ACR[7]=1 13.5.4 UART_ICR - ICR Register (address offset: 0x05)

  • Page 135: Figure 13.2 - Icr Registers Read Access

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Last value written to LCR≠0xBF SPR ⇐ ‘0x00’ Enable access ACR[6]⇐’1’ ICR[6] ⇐ ‘1’ SPR ⇐ address value ⇐ ICR Read from another Indexed Control Register SPR ⇐...

  • Page 136: Uart_Acr - Additional Control Register (Spr Offset: 0X00)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 13.6.1 UART_ACR - Additional Control Register (SPR offset: 0x00) Default Name Type Description Value Additional status enable ADL_STS_EN 1’h0 1: ASR, TFL and RFL are enabled...

  • Page 137: Uart_Cpr - Clock Prescaler Register (Spr Offset: 0X01)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 13.6.2 UART_CPR - Clock Prescaler Register (SPR offset: 0x01) Name Type Default Value Description PSCL 5’h00 Clock prescaler Reserved Table 13.30 - UART_CPR - Clock Prescaler Register 13.6.3 UART_TCR - Time Clock Register (SPR offset: 0x02)

  • Page 138: Uart_Ttl - Transmitter Trigger Level Register (Spr Offset: 0X04)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 10: The baud rate generator output is selected for the receiver clock (internal BAUD_OUT connection) 11: The transmitter clock is selected for the receiver clock Table 13.32 - UART_CKS Clock Select Register...

  • Page 139: Uart_Id1 - Identification 1 Register (Spr Offset: 0X08)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 level and FCH stores the upper trigger level. Both registers are able to store level values from 0 to 127. Name Type Default Value Description...

  • Page 140: Uart_Nmr - Nine Bit Mode Register (Spr Offset: 0X0D)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 13.6.14 UART_NMR - Nine Bit Mode Register (SPR offset: 0x0D) To enable 9‐bit data mode NMR[0] bit must be logic 0. In this mode data are nine bits wide, and the 9‐th bit is stored in LSR[2] for receiving.

  • Page 141: Uart_Rfc - Readable Fcr Register (Spr Offset: 0X0F)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description when IER[3]=1 1: Disables level 4 interrupt from delta DSR. Delta CTS disable. 0: Enables level 4 interrupt from delta CTS CTS_MASK 1’h0...

  • Page 142: 14 Timers And Watchdog

    Clearance No.: BRT#081 14 Timers and Watchdog FT900 consists of a 32-bit watchdog timer and four 16-bit users’ timers. The watchdog timer is clocked off the main clock. The watchdog can be initialized with a 5-bit register. The value of this register points to a bit of the 32-bit counter which will be set. A timer decrements and signals an interrupt when it rolls over.

  • Page 143: 14.1 Register Summary

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Current value can be read from TIMER_READ_LS and TIMER_READ_MS registers. Write into stop_x bit in TIMER_CONTROL_1 register to stop the timer. Table 14.1 - Timers/Watchdog Operation 14.1 Register Summary...

  • Page 144: Timer_Control_1 - Timers Control Register 1 (Address Offset: 0X01)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 14.2.2 TIMER_CONTROL_1 - Timers Control Register 1 (address offset: 0x01) Name Type Default Value Description stop_d RWAC 1’b0 1: To trigger stopping timer D stop_c RWAC 1’b0...

  • Page 145: Timer_Control_4 - Timers Control Register 4 (Address Offset: 0X04)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 14.2.5 TIMER_CONTROL_4 - Timers Control Register 4 (address offset: 0x04) Name Type Default Value Description presc_clear RWAC 1’b0 1: To trigger clearing prescaler clear_d RWAC 1’b0...

  • Page 146: Timer_Write_Ls - Timer A

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 14.2.9 TIMER_WRITE_LS - Timer A..D Start Value 7:0 (address offset: 0x08) Default Name Type Description Value timer_write_7_0 8’h00 Write low byte of the timer start value Table 14.11 - TIMER_WRITE_LS - Timer A..D Start Value 7:0...

  • Page 147: 15 I2S

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 15 I2S The I2S interface supports both Master and Slave modes. The formats supported are I2S, Left Justified and Right Justified. In the Master mode, 2 clock sources are to be provided externally. One is 24.576MHz and the other 22.5792MHz.

  • Page 148: Table 15.1 - Oversampling Rates Supported By Ft900 I2S

    64fs 24.576MHz 128fs Table 15.1 - Oversampling rates supported by FT900 I2S In this mode (i.e., Master mode), the number of BCLK cycles per channel per sampling cycle can only be either 16 or 32. The table shows the supported bit length with the number of BCLK per sampling cycle in the Master mode.

  • Page 149: 15.1 Register Summary

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 maximum frequency of BCLK is 12.288MHz regardless of the sampling frequency and bit length. 15.1 Register Summary Listed below are the registers with their offset from the base address (0x10350). All registers can only be accessed via Word (16-bit) mode.

  • Page 150: I2Scr2 - Configuration Register 2 (Address Offset: 0X02)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 1: Use 22.5792MHz input as the reference clock. 0: Use 24.576MHz input as the reference clock. BCLK 1’b0 1: Invert the polarity of BCLK. Polarity LRCLK Out 1’b0...

  • Page 151: I2Sirqen - Interrupt Enable Register (Address Offset: 0X04)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 15.2.3 I2SIRQEN - Interrupt Enable Register (address offset: 0x04) Name Type Default Value Description 15:13 Reserved RX FIFO 1’b0 1: Enable Receive FIFO Overflow Interrupt.

  • Page 152: I2Srwdata - Transmit / Receive Data Register (Address Offset: 0X08)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Write 1 to clear. TX FIFO Under RW1C 1’b0 1: Transmit FIFO Underflow Interrupt Pending. Write 1 to clear. Table 15.7 - I2SIRQPEND - Interrupt Pending Register 15.2.5 I2SRWDATA - Transmit / Receive Data Register (address offset: 0x08)

  • Page 153: 16 Spi Master

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 16 SPI Master There is a SPI Master module in the device. Listed below are the key features of this SPI master: • Full duplex synchronous serial data transfer •...

  • Page 154: 16.2 Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 16.2 Register Details 16.2.1 SPIM_CNTL – Control Register (address offset: 0x00) Name Type Default Value Description SP_IE 1’b0 1: To enable SPI Master interrupt SP_E 1’b0...

  • Page 155: Spim_Data - Receiver And Transmitter Data Registers (Address Offset: 0X08)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Default Name Type Description Value SPI in IDLE state with TX FIFO or THR register THRE 1’b0 empty 0: Transmission is in progress Transmitter Empty TX_EMPTY 1’b0...

  • Page 156: Spim_Tnsfr_Frmt_Cntl - Transfer Format Control Register (Address Offset: 0X14)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description Write 1 to TX FIFO and its logic; The shift register TX_RST 1’b0 is not affected; This bit will clear itself Write 1 to RX FIFO and its logic;...

  • Page 157: Spi Slaves

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 17 SPI Slaves There are two independent SPI slaves in the device. Listed below are the key features of the SPI slaves: • Full duplex synchronous serial data transfer •...

  • Page 158: Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 17.2 Register Details 17.2.1 SPIS_CNTL – Control Register (address offset: 0x00) Default Name Type Description Value SP_IE 1’b0 1: To enable SPI Slave interrupt SP_E 1’b0...

  • Page 159: Spis_Data - Receiver And Transmitter Data Registers (Address Offset: 0X08)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Slave Select Control Enable 1: auto SS assertions enabled SSC_EN 1’b0 0: auto SS assertions disabled – SS always shows contents of Slave Select Control Register Table 17.3 - SPIS_STATUS –...

  • Page 160: Spis_Tnsfr_Frmt_Cntl - Transfer Format Control Register (Address Offset: 0X14)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 17.2.6 SPIS_TNSFR_FRMT_CNTL – Transfer Format Control Register (address offset: 0x14) Default Name Type Description Value 1: Enable FIFO extension and allow 16 bits data FIFO_EXT 1’b0...

  • Page 161: 18 I2C Master

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 18 I2C Master The I2C Master conforms to v2.1 and v3.0 of the I2C specification. Listed below are the key features supported by the I2C master: •...

  • Page 162: 18.2 Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 18.2 Register Details 18.2.1 I2CM_SLV_ADDR – Slave Address Register (address offset: 0x00) Default Name Type Description Value SLV_ADDR 7’h00 This is 7-bit address bits 0: next operation is a transmission RX_OP 1’b0...

  • Page 163: I2Cm_Status - Status Register (Address Offset: 0X01)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 18.2.3 I2CM_STATUS – Status Register (address offset: 0x01) Default Name Type Description Value Reserved 1: indicates the Bus is Busy, and access is not possible.

  • Page 164: I2Cm_Hs_Time_Period - High Speed Timer Period Register (Address Offset: 0X03)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 18.2.6 I2CM_HS_TIME_PERIOD – High Speed Timer Period Register (address offset: 0x03) Default Name Type Description Value TIME_ENB 1’b0 Set to use this register. Set to indicate to the Bus controller to use FAST FAST 1’b0...

  • Page 165: I2Cm_Fifo_Int_Pend - Fifo Mode Interrupt Pending (Address Offset: 0X06)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 18.2.9 I2CM_FIFO_INT_PEND – FIFO Mode Interrupt Pending (address offset: 0x06) Default Name Type Description Value DONE RW1C 1’b0 FIFO_BL operation complete interrupt pending I2C_INT RW1C 1’b0...

  • Page 166: 19 I2C Slave

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 19 I2C Slave The I2C Slave conforms to v2.1 and v3.0 of the I2C specification. Listed below are the key features supported by the I2C slave: •...

  • Page 167: 19.2 Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 19.2 Register Details 19.2.1 I2CS_OWN_ADDR – Own Address Register (address offset: 0x00) Default Name Type Description Value Reserved OWN_ADDR 7’h00 This is the seven address bits of the Slave controller.

  • Page 168: I2Cs_Data - Receive / Transmit Data Register (Address Offset: 0X02)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Name Type Default Value Description 1: indicates that the Master has ended the transmit operation. It means no more RX_REQ will REC_FIN 1’b0 during this...

  • Page 169: I2Cs_Fifo_Int_Pend - Fifo Mode Interrupt Pending (Address Offset: 0X06)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 19.2.7 I2CS_FIFO_INT_PEND – FIFO Mode Interrupt Pending (address offset: 0x06) Default Name Type Description Value DONE RW1C 1’b0 FIFO_BL operation complete interrupt pending I2C_INT RW1C 1’b0...

  • Page 170: 20 Rtc

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 20 RTC This is a Real Time Clock (RTC) running off a dedicated 32.768 kHz oscillator. It is powered by the internal 1.2V regulator. 20.1 Register Summary Listed below are the registers with their offset from the base address (0x10280).

  • Page 171: Rtc_Clr - Counter Load Register (Address Offset: 0X08)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 20.2.3 RTC_CLR - Counter Load Register (address offset: 0x08) Default Name Type Description Value Loaded in the counter as the loaded value, which is 31:0 DATA 32’h0...

  • Page 172: Rtc_Eoi - End Of Interrupt Register (Address Offset: 0X18)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 20.2.7 RTC_EOI - End of Interrupt Register (address offset: 0x18) Default Name Type Description Value 31:1 Reserved By reading this location, the match interrupt is RTC_EOI 1’h0...

  • Page 173: 21 Pwm

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 21 PWM The device supports 7 separate independent PWM channels. All channels share an 8-bit prescaler to scale the system clock frequency to the desired channels.

  • Page 174: Table 21.34 - Pwm_Intmask - Pwm Interrupt Mask Register

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0x0C PWM_CMP3H - Comparator 3 Value Register (MSB) 0x00 Section 21.2.13 0x0D PWM_CMP4L - Comparator 4 Value Register (LSB) 0x00 Section 21.2.14 0x0E PWM_CMP4H - Comparator 4 Value Register (MSB) 0x00 Section 21.2.15...

  • Page 175: 21.2 Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0x24 PCM_VOLUME - PCM Volume Register 0x00 Section 21.2.37 0x3C PWM_BUFFER - PCM Buffer Register 0xXXXX Section 21.2.38 Table 21.1 - Overview of PWM Registers 21.2 Register Details...

  • Page 176: Pwm_Prescaler - Pwm Prescaler Register (Address Offset: 0X02)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 PWM trigger enable: Disabled PWM_TRIGGER_EN 2’h0 Positive Edge Negative Edge Any Edge PWM_EN 1’b0 Set to 1 to enable PWM. Table 21.3 - PWM_CTRL1 - PWM Control Register 21.2.3 PWM_PRESCALER - PWM Prescaler Register (address offset: 0x02)

  • Page 177: Pwm_Cmp0H - Comparator 0 Value Register (Msb) (Address Offset: 0X06)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 21.2.7 PWM_CMP0H - Comparator 0 Value Register (MSB) (address offset: 0x06) Name Type Default Value Description CMP16_0_MSB 8’h00 MSB of comparator 0 16-bit value. Table 21.8 - PWM_CMP0H - Comparator 0 Value Register (MSB) 21.2.8 PWM_CMP1L - Comparator 1 Value Register (LSB) (address offset: 0x07)

  • Page 178: Pwm_Cmp4L - Comparator 4 Value Register (Lsb) (Address Offset: 0X0D)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 21.2.14 PWM_CMP4L - Comparator 4 Value Register (LSB) (address offset: 0x0D) Name Type Default Value Description CMP16_4_LSB 8’h00 LSB of comparator 4 16-bit value. Table 21.15 - PWM_CMP4L - Comparator 4 Value Register (LSB) 21.2.15 PWM_CMP4H - Comparator 4 Value Register (MSB) (address offset: 0x0E)

  • Page 179: Pwm_Cmp7H - Comparator 7 Value Register (Msb) (Address Offset: 0X14)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 21.2.21 PWM_CMP7H - Comparator 7 Value Register (MSB) (address offset: 0x14) Name Type Default Value Description CMP16_7_MSB 8’h00 MSB of comparator 7 16-bit value. Table 21.22 - PWM_CMP7H - Comparator 7 Value Register (MSB) 21.2.22 PWM_TOGGLE0 - Channel 0 OUT Toggle Comparator Mask Register (address...

  • Page 180: Pwm_Toggle5 - Channel 5 Out Toggle Comparator Mask Register (Address Offset: 0X1A)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 21.2.27 PWM_TOGGLE5 - Channel 5 OUT Toggle Comparator Mask Register (address offset: 0x1A) Default Name Type Description Value Channel 5 PWM OUT toggle comparator mask (each bit TOGGLE_EN_5 8’h00...

  • Page 181: Pwm_Intmask - Pwm Interrupt Mask Register (Address Offset: 0X20)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 21.2.33 PWM_INTMASK - PWM Interrupt Mask Register (address offset: 0x20) Name Type Default Value Description Reserved FIFO_EMPTY_MASK 1’b0 FIFO empty interrupt mask FIFO_FULL_MASK 1’b0 FIFO full interrupt mask FIFO_HALF_MASK 1’b0...

  • Page 182: Pwm_Sample_Freq_L - Pwm Data Sampling Frequency Low Byte Register (Address Offset: 0X23)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 21.2.36 PWM_SAMPLE_FREQ_L - PWM Data Sampling Frequency Low Byte Register (address offset: 0x23) Default Name Type Description Value PWM_SAMPLE_FREQ_L 8’h22 PWM Data Sampling Frequency Low Byte Table 21.37 - PWM_SAMPLE_FREQ_L - PWM Data Sampling Frequency Low Byte Register...

  • Page 183: Data Capture Interface

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 22 Data Capture Interface There is an 8-bit parallel interface to collect byte streaming data from a sensor peripheral - e.g. a camera module - in a 2Kbyte internal FIFO. The interface will provide a clock to the peripheral at a speed of 25MHz (max).

  • Page 184: Dcap_Reg2 - Data Capture Interface Register 2 (Address Offset: 0X04)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 22.2.2 DCAP_REG2 – Data Capture Interface Register 2 (address offset: 0x04) Default Name Type Description Value 31:12 Reserved Specifies the number of bytes that can be safely read...

  • Page 185: Flash Controller

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 23 Flash Controller There are two ways to access the memory control unit. One is via the CPU I/O interface and the other via the one-wire debugger interface. The CPU I/O interface is described here.

  • Page 186: 23.2 Register Details

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 0x0F CRCH – Flash Content CRC Register (MSB) 0xXX Section 23.2.15 0x7C CHIPID0 – Chip ID Register (LSB) (only via one-wire 0xXX Section 23.2.16 debugger) 0x7D CHIPID1 –...

  • Page 187: Fsaddr0 - Flash Start Address Register (Lsb) (Address Offset: 0X03)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 23.2.4 FSADDR0 – Flash Start Address Register (LSB) (address offset: 0x03) Default Name Type Description Value LSB of the start address of flash location to perform...

  • Page 188: Command - Command Register (Address Offset: 0X09)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Note 1: When the flash is the destination (write case), the byte length must be a multiple of 256 bytes (1 page of flash entry). There is no such restriction on byte length if the flash is the source (read case).

  • Page 189: Status - Status Register (Address Offset: 0X0D)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 23.2.13 STATUS – Status Register (address offset: 0x0D) Default Name Type Description Value Reserved 1: The control unit is busy. This means no other command should be issued.

  • Page 190: Chipid1 - Chip Id Register (Byte 1) (Address Offset: 0X7D)

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 23.2.17 CHIPID1 – Chip ID Register (Byte 1) (address offset: 0x7D) Default Name Type Description Value Byte 1 of the 32-bit chip ID, only accessible via the 0xXX one-wire debugger.
  • Page 191 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Command Code Description The Write Enable (WREN) instruction is for setting the Write Enable Latch (WEL) bit. Those instructions such as PP, SE, CMDWREN 0x06...

  • Page 192: Table 23.22 - Flash Controller Command Group 1

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Command Code Description The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a...
  • Page 193 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Command Code Description be multiples of 256 bytes. Data to be transferred will be in DRWDATA. Similar to CMDDBG2F1 except at the end of the transfer, a CPU reset...

  • Page 194: Table 23.23 - Flash Controller Command Group 2

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Command Code Description The start address of the Data Memory destination will be dictated by RSADDRx which must be 32-bit aligned. The start address of the Flash Memory destination will be dictated by FSADDRx which must be 256-byte aligned.

  • Page 195: 24 Contact Information

    Bridgetek. Use of Bridgetek devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless Bridgetek from any and all damages, claims, suits or expense resulting from such use.

  • Page 196: Appendix A - References

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Appendix A – References Document References N.A. Acronyms and Abbreviations Terms Description Analogue to Digital Converter Battery Charger Detection Controller Area Network CPRM Content Protection for Recordable Media...
  • Page 197 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Terms Description Used in Ethernet as the “Station Management Controller” UART Universal Asynchronous Receiver Transmitter Universal Serial Bus USB-IF USB Implementers Forum Product Page Document Feedback...

  • Page 198: Appendix B - List Of Tables & Figures

    List of Tables Table 2.1 - FT900 Program Memory Organization ..............16 Table 3.1 - Peripheral Availability on FT900 Series Models ............18 Table 3.2 - Register Map for FT900 Series ................18 Table 4.1 - Notations used in Register Description ..............19 Table 5.1 - Overview of General System Registers ..............
  • Page 199 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 5.32 - GPIO 24 – 31 Configuration Register ..............33 Table 5.33 - GPIO 32 – 39 Configuration Register ..............34 Table 5.34 - GPIO 40 – 47 Configuration Register ..............34 Table 5.35 - GPIO 48 –...
  • Page 200 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 8.9 - PERIODICLISTBASE – HC Periodic Frame List Base Address Register ....... 51 Table 8.10 - ASYNCLISTADDR – HC Current Asynchronous List Address Register ...... 52 Table 8.11 - PORTSC –...
  • Page 201 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 10.12 - ETH_ADDR_2 – Address Register (octet 2) ............71 Table 10.13 - ETH_ADDR_3 – Address Register (octet 3) ............72 Table 10.14 - ETH_ADDR_4 – Address Register (octet 4) ............72 Table 10.15 - ETH_ADDR_5 –...
  • Page 202 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 11.26 - CAN_ACC_MASK_1 – Acceptance Mask 1 Register ..........86 Table 11.27 - CAN_ACC_MASK_2 – Acceptance Mask 2 Register ..........87 Table 11.28 - CAN_ACC_MASK_3 – Acceptance Mask 3 Register ..........87 Table 11.29 - CAN_ERR_CODE –...
  • Page 203 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 12.32 - SDH_RSRV_4 – Reserved 4 Register ............... 106 Table 12.33 - SDH_PRST_INIT – Preset value for initialization ..........107 Table 12.34 - SDH_PRST_DFLT_SPD – Preset value for default speed ........107 Table 12.35 - SDH_PRST_HIGH_SPD –...
  • Page 204 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 13.7 - UART_INT_ENABLE - Interrupt Enable Register ..........123 Table 13.8 - UART_INT_STATUS - Interrupt Status Register ..........123 Table 13.9 - Interrupt Status Register Software Handling ............124 Table 13.10 - UART_FCR - FIFO Control Register –...
  • Page 205 Table 14.15 - TIMER_READ_LS - Timer A..D Current Value 7:0 ..........145 Table 14.16 - TIMER_READ_MS - Timer A..D Current Value 15:8 ........... 145 Table 15.1 - Oversampling rates supported by FT900 I2S ............. 147 Table 15.2 - FT900 I2S settings ..................147 Table 15.3 - Overview of I2S Registers ................
  • Page 206 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 17.4 - SPIS_DATA – Receiver and Transmitter Data Registers ........158 Table 17.5 - SPIS_SLV_SEL_CNTL – Slave Select Control Register ......... 158 Table 17.6 - SPIS_FIFO_CNTL – FIFO Control Register ............158 Table 17.7 - SPIS_TNSFR_FRMT_CNTL –...
  • Page 207 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 21.4 - PWM_PRESCALER - PWM Prescaler Register ............175 Table 21.5 - PWM_CNTL - PWM Counter Register (LSB) ............175 Table 21.6 - PWM_CNTH - PWM Counter Register (MSB) ............175 Table 21.7 - PWM_CMP0L - Comparator 0 Value Register (LSB) ..........
  • Page 208 Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Table 22.5 - DCAP_REG4 – Data Capture Interface Register 4 ..........183 Table 23.1 - Overview of Data Capture Interface Registers ............ 185 Table 23.2 - RSADDR1 – Memory Start Address Register (LSB) ..........185 Table 23.3 - RSADDR1 –...

  • Page 209: List Of Figures

    Document Reference No.: BRT_000131 Clearance No.: BRT#081 List of Figures Figure 2.1 - FT900 System Architecture ................15 Figure 2.2 - FT900 Boot Control ..................16 Figure 2.3 - FT900 Debugging Support ................17 Figure 11.1 - CAN Acceptance Filter ..................84 Figure 13.1 - ICR registers write access ................

  • Page 210: Appendix C - Revision History

    Application Note AN_324 FT900 User Manual Version 1.3 Document Reference No.: BRT_000131 Clearance No.: BRT#081 Appendix C – Revision History Document Title: AN_324 FT900 User Manual Document Reference No.: BRT_000131 Clearance No.: BRT#081 Product Page: https://brtchip.com/ft9xx-toolchain/ Document Feedback: Send Feedback...

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