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AT32WB415 Series
ARTERY AT32WB415 Series Bluetooth MCU Manuals
Manuals and User Guides for ARTERY AT32WB415 Series Bluetooth MCU. We have
1
ARTERY AT32WB415 Series Bluetooth MCU manual available for free PDF download: Reference Manual
ARTERY AT32WB415 Series Reference Manual (374 pages)
Brand:
ARTERY
| Category:
Recording Equipment
| Size: 5 MB
Table of Contents
Table of Contents
2
System Architecture
27
Figure 1-1 AT32WB415 Series Microcontrollers System Architecture
28
System Overview
29
ARM Cortex
29
TM -M4 Processor
29
Bit Band
29
Figure 1-2 Internal Block Diagram of Cortex ® -M4
29
Figure 1-3 Comparison between Bit-Band Region and Its Alias Region: Image a
29
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image B
30
Table 1-1 Bit-Band Address Mapping in SRAM
30
Interrupt and Exception Vectors
31
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
31
Table 1-3 AT32WB415 Series Vector Table
31
System Tick (Systick)
34
Reset
34
Figure 1-5 Reset Process
34
Figure 1-6 Example of MSP and PC Initialization
35
List of Abbreviations for Registers
36
Device Characteristics Information
36
Flash Memory Size Register
36
Device Electronic Signature
36
Table 1-4 List of Abbreviations for Registers
36
Table 1-5 List of Abbreviations for Registers
36
Memory Resources
37
Internal Memory Address Map
37
Figure 2-1AT32WB415 Address Mapping
37
Flash Memory
38
SRAM Memory
38
Peripheral Address Map
38
Table 2-1 Flash Memory Organization (256 KB)
38
Table 2-2 Peripheral Boundary Address
38
Power Control (PWC)
41
Introduction
41
Main Features
41
Figure 3-1 Block Diagram of each Power Supply
41
Por/Lvr
42
Power Voltage Monitor (PVM)
42
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
42
Figure 3-3 PVM Threshold and Output
42
Power Domain
43
Power Saving Modes
43
PWC Registers
45
Power Control Register (PWC_CTRL)
45
Power Control/Status Register (PWC_CTRLSTS)
45
Table 3-1 PW Register Map and Reset Values
45
Clock and Reset Manage (CRM)
47
Clock
47
Clock Sources
47
Figure 4-1 AT32WB415 Clock Tree
47
System Clock
48
Peripheral Clock
48
Clock Fail Detector
48
Auto Step-By-Step System Clock Switch
48
Internal Clock Output
49
Interrupts
49
Reset
49
System Reset
49
Battery Powered Domain Reset
49
Figure 4-2 System Reset Circuit
49
CRM Registers
50
Clock Control Register (CRM_CTRL)
50
Table 4-1 CRM Register Map and Reset Values
50
Clock Configuration Register (CRM_CFG)
51
Clock Interrupt Register (CRM_CLKINT)
53
APB2 Peripheral Reset Register (CRM_APB2RST)
54
APB1 Peripheral Reset Register1 (CRM_APB1RST)
55
APB Peripheral Clock Enable Register (CRM_AHBEN)
55
APB2 Peripheral Clock Enable Register (CRM_AHB2EN)
56
APB1 Peripheral Clock Enable Register (CRM_AHB1EN)
57
Battery Powered Domain Control Register (CRM_BPDC)
58
Control/Status Register (CRM_CTRLSTS)
58
APB Peripheral Reset Register (CRM_APBRST)
59
PLL Configuration Register (CRM_PLL)
59
Additional Register (CRM_MISC1)
60
OTG_FS Extended Control Register (CRM_OTG_EXTCTRL)
60
Additional Register (CRM_MISC2)
60
Flash Memory Controller (FLASH)
62
FLASH Introduction
62
Table 5-1 Flash Memory Architecture(256 K)
62
Table 5-2 User System Data Area
62
Flash Memory Operation
63
Unlock/Lock
63
Erase Operation
64
Figure 5-1 Flash Memory Page Erase Process
64
Figure 5-2 Flash Memory Mass Erase Process
65
Programming Operation
66
Figure 5-3 Flash Memory Programming Process
66
Read Operation
67
Main Flash Memory Extension Area
67
User System Data Area
67
Unlock/Lock
67
Erase Operation
67
Programming Operation
68
Figure 5-4 System Data Area Erase Process
68
Figure 5-5 System Data Area Programming Process
69
Read Operation
70
Flash Memory Protection
70
Access Protection
70
Erase/Program Protection
70
Table 5-3 Flash Memory Access Limit
70
Special Functions
71
Security Library Settings
71
Bootloader Code Area Used as Flash Memory Extension
72
CRC Verify
72
Flash Memory Registers
73
Flash Performance Select Register (FLASH_PSR)
73
Table 5-4 Flash Memory Interface-Register Map and Reset Value
73
Flash Unlock Register (FLASH_UNLOCK)
74
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
74
Flash Status Register (FLASH_STS)
74
Flash Control Register (FLASH_CTRL)
74
Flash Address Register (FLASH_ADDR)
75
User System Data Register (FLASH_USD)
75
Erase/Program Protection Status Register (FLAS H_EPPS)
76
Flash Security Library Status Register0 (SLIB_STS0)
76
Flash Security Library Status Register1 (SLIB_STS1)
76
Security Library Password Clear Register (SLIB_PWD_CLR)
77
Security Library Additional Status Register (SLIB_MISC_STS)
77
Flash CRC Address Register (FLASH_CRC_ARR)
77
Flash CRC Control Register (FLASH_CRC_CTRL)
77
Flash CRC Check Result Register (FLASH_CRC_CHKR)
78
Security Library Password Setting Register (SLIB_SET_PWD)
78
Security Library Address Setting Register (SLIB_SET_RANGE)
78
(Em_Slib_Set)
79
Boot Mode Setting Register (BTM_MODE_SET)
79
Security Library Unlock Register (FLASH_UNLOCK)
79
General-Purpose I/Os (Gpios)
80
Introduction
80
Functional Overview
80
GPIO Structure
80
GPIO Reset Status
80
Figure 6-1 GPIO Basic Structure
80
General-Purpose Input Configuration
81
Analog Input/Output Configuration
81
General-Purpose Output Configuration
81
GPIO Port Protection
81
GPIO Registers
81
Table 6-1 GPIO Register Map and Reset Values
81
GPIO Configuration Register Low (Gpiox_Cfglr) (X=A
82
GPIO Configuration Register High (Gpiox_Cfghr) (X=A
82
GPIO Input Register (Gpiox_Idt) (X=A
82
GPIO Output Register (Gpiox_Odt) (X= a
83
GPIO Set/Clear Register (Gpiox_Scr) (X=A
83
GPIO Bit Clear Register (Gpiox_Clr) (X=A
83
GPIO Write Protection Register (Gpiox_Wpr) (X=A
83
Multiplexed Function I/Os (IOMUX)
84
Introduction
84
Functional Overview
84
IOMUX Structure
84
Figure 7-1 Basic Structure of IOMUX Basic Structure
84
MUX Input Configuration
85
MUX Output or Bidirectional MUX Configuration
85
Peripheral MUX Function Configuration
85
IOMUX Map Priority
85
Table 7-1 IOMUX Input Configuration
85
Hardware Preemption
86
Debug Port Priority
86
Other Peripheral Output Priority
86
External Interrupt/Wake-Up Lines
86
IOMUX Registers
87
Event Output Control Register (IOMUX_EVTOUT)
87
IOMUX Remap Register (IOMUX_REMAP)
88
IOMUX External Interrupt Configuration Register1 (IOMUX_EXINTC1)
89
IOMUX External Interrupt Configuration Register2 (IOMUX_EXINTC2)
90
IOMUX External Interrupt Configuration Register3 (IOMUX_EXINTC3)
91
IOMUX External Interrupt Configuration Register4 (IOMUX_EXINTC4)
92
IOMUX Remap Register2 (IOMUX_REMAP2)
92
IOMUX Remap Register3 (IOMUX_REMAP3)
93
IOMUX Remap Register4 (IOMUX_REMAP4)
93
IOMUX Remap Register5 (IOMUX_REMAP5)
94
IOMUX Remap Register6 (IOMUX_REMAP6)
94
IOMUX Remap Register7 (IOMUX_REMAP7)
95
IOMUX Remap Register8 (IOMUX_REMAP8)
96
External Interrupt/Event Controller (EXINT)
97
EXINT Introduction
97
Function Overview and Configuration Procedure
97
Figure 8-1 External Interrupt/Event Controller Block Diagram
97
EXINT Registers
98
Interrupt Enable Register (EXINT_INTEN)
98
Event Enable Register (EXINT_EVTEN)
98
Polarity Configuration Register1 (EXINT_ POLCFG1)
98
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
98
Polarity Configuration Register2 (EXINT_ POLCFG2)
99
Software Trigger Register (EXINT_ SWTRG)
99
Interrupt Status Register (EXINT_ INTSTS)
99
DMA Controller (DMA)
100
Introduction
100
Main Features
100
Figure 9-1 DMA Block Diagram
100
Function Overview
101
DMA Configuration
101
Handshake Mechanism
101
Arbiter
101
Figure 9-2 Re-Arbitrae after Request/Acknowledge
101
Programmable Data Transfer Width
102
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
102
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
102
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
102
Errors
103
Interrupts
103
Fixed DMA Request Mapping
103
Flexible DMA Request Mapping
103
Table 9-1 DMA Error Event
103
Table 9-2 DMA Interrupt Requests
103
Table 9-3 DMA1 Requests for each Channel
103
Table 9-4 DMA2 Requests for each Channel
103
Table 9-5 DMA Flexible Request Sources
104
DMA Registers
105
Table 9-6 DMA Register Map and Reset Value
105
DMA Interrupt Status Register (DMA_STS)
106
DMA Interrupt Flag Clear Register (DMA_CLR)
107
DMA Channel-X Configuration Register (Dma_Cxctrl) (X = 1
109
DMA Channel-X Number of Data Register (Dma_Cxdtcnt) (X = 1
110
DMA Channel-X Peripheral Address Register (Dma_Cxpaddr)
110
DMA Channel-X Memory Address Register (Dma_Cxmaddr
111
DMA Channel Source Register (DMA_SRC_SEL0)
111
DMA Channel Source Register1 (DMA_SRC_SEL1)
111
CRC Calculation Unit (CRC)
112
CRC Introduction
112
CRC Registers
112
Data Register (CRC_DT)
112
Common Data Register (CRC_CDT)
112
Table 10-1 CRC Register Map and Reset Value
112
Control Register (CRC_CTRL)
113
Initialization Register (CRC_IDT)
113
C Interface
114
I 2 C Introduction
114
I 2 C Main Features
114
I 2 C Function Overview
114
Figure 11-1 I C Bus Protocol
114
I 2 C Interface
115
Figure 11-2 I2C Function Block Diagram
115
C Slave Communication Flow
117
Figure 11-3 Transfer Sequence of Slave Transmitter
117
C Master Communication Flow
118
Figure 11-4 Transfer Sequence of Slave Receiver
118
Figure 11-5 Transfer Sequence of Master Transmitter
119
Figure 11-6 Transfer Sequence of Master Receiver
120
Figure 11-7 Transfer Sequence of Master Receiver When N>2
121
Figure 11-8 Transfer Sequence of Master Receiver When N=2
122
Figure 11-9 Transfer Sequence of Master Receiver When N=1
123
Data Transfer Using DMA
124
Smbus
125
C Interrupt Requests
127
C Debug Mode
127
I 2 C Registers
127
Table 11-1 I 2 C Register Map and Reset Values
127
Control Register1 (I2C_CTRL1)
128
Control Register2 (I2C_CTRL2)
129
Own Address Register1 (I2C_OADDR1)
130
Own Address Register2 (I2C_OADDR2)
130
Data Register (I2C_DT)
130
Status Register1 (I2C_STS1)
131
Status Register2 (I2C_STS2)
133
Clock Control Register (I2C_ CLKCTRL)
133
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
135
USART Introduction
135
Figure 12-1 USART Block Diagram
135
Full-Duplex/Half-Duplex Selector
137
Mode Selector
137
Introduction
137
Configuration Procedure
137
USART Frame Format and Configuration
138
DMA Transfer Introduction
138
Transmission Using DMA
138
Reception Using DMA
138
Baud Rate Generation
139
Introduction
139
Configuration
139
Transmitter
139
Transmitter Introduction
139
Transmitter Configuration
139
Receiver
140
Receiver Introduction
140
Receiver Configuration
140
Start Bit and Noise Detection
141
Table 12-2 Data Sampling over Start Bit and Noise Detection
141
Table 12-3 Data Sampling over Valid Data and Noise Detection
141
Interrupt Requests
142
I/O Pin Control
142
Figure 12-2 USART Interrupt Map Diagram
142
Table 12-4 USART Interrupt Request
142
USART Registers
143
Status Register (USART_STS)
143
Table 12-5 USART Register Map and Reset Value
143
Data Register (USART_DT)
144
Baud Rate Register (USART_BAUDR)
144
Control Register1 (USART_CTRL1)
144
Control Register2 (USART_CTRL2)
146
Control Register3 (USART_CTRL3)
147
Guard Time and Divider Register (USART_GDIV)
148
Serial Peripheral Interface (SPI)
149
SPI Introduction
149
Functional Overview
149
SPI Description
149
Figure 13-1 SPI Block Diagram
149
Full-Duplex/Half-Duplex Selector
150
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
150
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
150
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
151
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
151
Chip Select Controller
152
SPI_SCK Controller
152
Crc
152
DMA Transfer
153
Transmitter
154
Receiver
154
Motorola Mode
155
Figure 13-6 Master Full-Duplex Communications
155
Figure 13-7 Slave Full-Duplex Communications
156
Figure 13-8 Master Half-Duplex Transmit
156
Figure 13-9 Slave Half-Duplex Receive
156
Interrupts
157
Figure 13-10 Slave Half-Duplex Transmit
157
Figure 13-11 Master Half-Duplex Receive
157
Figure 13-12 SPI Interrupts
157
IO Pin Control
158
Precautions
158
SPI Registers
158
SPI Control Register1 (SPI_CTRL1)
158
Table 13-2 SPI Register Map and Reset Value
158
SPI Control Register2 (SPI_CTRL2)
159
SPI Status Register (SPI_STS)
160
SPI Data Register (SPI_DT)
160
SPICRC Register (SPI_CPOLY)
161
Spirxcrc Register (SPI_RCRC)
161
Spitxcrc Register (SPI_TCRC)
161
Timer
162
General-Purpose Timer (TMR2 to TMR5)
162
Tmrx Introduction
162
Table 14-1 TMR Functional Comparison
162
Tmrx Main Features
163
Tmrx Functional Overview
163
Count Clock
163
Figure 14-1 General-Purpose Timer Block Diagram
163
Figure 14-2 Control Circuit with CK_INT Divided by 1
163
Figure 14-3 Block Diagram of External Clock Mode a
164
Figure 14-4 Counting in External Clock Mode a
164
Figure 14-5 Block Diagram of External Clock Mode B
164
Figure 14-6 Counting in External Clock Mode B
164
Counting Mode
165
Figure 14-7 Counter Timing with Prescaler Value Changing from 1 to 4
165
Figure 14-8 Overflow Event When PRBEN=0
165
Table 14-2 Tmrx Internal Trigger Connection
165
Figure 14-9 Overflow Event When PRBEN=1
166
Figure 14-10 Counter Timing Diagram with Internal Clock Divided by 4
166
Figure 14-11 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
166
TMR Input Function
167
Figure 14-12 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
167
Figure 14-13 Input/Output Channel 1 Main Circuit
167
Figure 14-14 Channel 1 Input Stage
167
Table 14-3 Couting Direction Versus Encoder Signals
167
TMR Output Function
168
Figure 14-15 Capture/Compare Channel Output Stage (Channel 1 to 4)
168
Figure 14-16 C1ORAW Toggles When Counter Value Matches the C1DT Value
169
Figure 14-17 Upcounting Mode and PWM Mode a
169
TMR Synchronization
170
Figure 14-18 Up/Down Counting Mode and PWM Mode a
170
Figure 14-19 One-Pulse Mode
170
Figure 14-20 Clearing Cxoraw(PWM Mode A) by EXT Input
170
Figure 14-21 Example of Reset Mode
171
Figure 14-22 Example of Suspend Mode
171
Figure 14-23 Example of Trigger Mode
171
Figure 14-24 Master/Slave Timer Connection
172
Figure 14-25 Using Master Timer to Start Slave Timer
172
Debug Mode
173
Tmrx Registers
173
Figure 14-26 Starting Master and Slave Timers Synchronously by an External Trigger
173
Table 14-4 Tmrx Register Map and Reset Value
173
Control Register1 (Tmrx_Ctrl1)
174
Control Register2 (Tmrx_Ctrl2)
175
Slave Timer Control Register (Tmrx_Stctrl)
175
Dma/Interrupt Enable Register (Tmrx_Iden)
176
Interrupt Status Register (Tmrx_Ists)
177
Software Event Register (Tmrx_Sw EVT)
178
Channel Mode Register1 (Tmrx_Cm1)
178
Channel Mode Register2 (Tmrx_Cm2)
180
Channel Control Register (Tmrx_Cctrl)
181
Table 14-5 Standard Cxout Channel Output Control Bit
181
Counter Value (Tmrx_Cval)
182
Division Value (Tmrx_Div)
182
Period Register (Tmrx_Pr)
182
Channel 1 Data Register (Tmrx_C1Dt)
182
Channel 2 Data Register (Tmrx_C2Dt)
182
Channel 3 Data Register (Tmrx_C3Dt)
183
Channel 4 Data Register (Tmrx_C4Dt)
183
DMA Control Register (Tmrx_ DMACTRL)
183
DMA Data Register (Tmrx_Dmadt)
183
General-Purpose Timer (TMR9 to TMR11)
184
Tmrx Introduction
184
Tmrx Main Features
184
TMR9 Main Features
184
TMR10 and TMR11 Main Features
184
Figure 14-27 Block Diagram of General-Purpose TMR9
184
Tmrx Functional Overview
185
Count Clock
185
Figure 14-28 Block Diagram of General-Purpose TMR10/11
185
Figure 14-29 Control Circuit with CK_INT Divided by 1
185
Figure 14-30 Block Diagram of External Clock Mode a
185
Counting Mode
186
Figure 14-31 Counting in External Clock Mode a
186
Figure 14-32 Counter Timing with Prescaler Value Changing from 1 to 4
186
Table 14-6 Tmrx Internal Trigger Connection
186
TMR Input Function
187
Figure 14-33 Overflow Event When PRBEN=0
187
Figure 14-34 Overflow Event When PRBEN=1
187
Figure 14-35 Input/Output Channel 1 Main Circuit
187
Figure 14-36 Channel 1 Input Stage
187
TMR Output Function
188
Figure 14-37 Capture/Compare Channel Output Stage (Channel 1)
188
TMR Synchronization
189
Figure 14-38 C1ORAW Toggles When Counter Value Matches the C1DT Value
189
Figure 14-39 Upcounting Mode and PWM Mode a
189
Figure 14-40 One-Pulse Mode
189
Debug Mode
190
Figure 14-41 Example of Reset Mode
190
Figure 14-42 Example of Suspend Mode
190
Figure 14-43 Example of Trigger Mode
190
TMR9 Registers
191
Control Register1 (TMR9_CTRL1)
191
Table 14-7 TMR9 Register Map and Reset Value
191
Slave Timer Control Register (TMR9_STCTRL)
192
Dma/Interrupt Enable Register (TMR9_IDEN)
192
Interrupt Status Register (TMR9_ISTS)
193
Software Event Register (TMR9_SW EVT)
194
Channel Mode Register1 (TMR9_CM1)
194
Channel Control Register (TMR9_CCTRL)
196
Counter Value (TMR9_CVAL)
197
Division Value (TMR9_DIV)
197
Period Register (TMR9_PR)
197
Channel 1 Data Register (TMR9_C1DT)
197
Table 14-8 Standard Cxout Channel Output Control Bit
197
Channel 2 Data Register (TMR9_C2DT)
198
TMR10 and TMR11 Registers
198
Control Register1 (Tmrx_Ctrl1)
198
Table 14-9 TMR10 and TMR11 Register Map and Reset Value
198
Dma/Interrupt Enable Register (Tmrx_Iden)
199
Interrupt Status Register (Tmrx_Ists)
199
Software Event Register (Tmrx_Sw EVT)
199
Channel Mode Register1 (Tmrx_Cm1)
200
Channel Control Register (Tmrx_Cctrl)
201
Counter Value (Tmrx_Cval)
202
Division Value (Tmrx_Div)
202
Period Register (Tmrx_Pr)
202
Channel 1 Data Register (Tmrx_C1Dt)
202
Table 14-10 Standard Cxout Channel Output Control Bit
202
Advanced-Control Timers (TMR1)
203
TMR1 Introduction
203
TMR1 Main Features
203
TMR1 Functional Overview
203
Count Clock
203
Figure 14-44 Block Diagram of Advanced-Control Timer
203
Figure 14-45 Control Circuit with CK_INT Divided by 1
204
Figure 14-46 Block Diagram of External Clock Mode a
204
Figure 14-47 Counting in External Clock Mode a
204
Figure 14-48 Block Diagram of External Clock Mode B
204
Counting Mode
205
Figure 14-49 Counting in External Clock Mode B
205
Figure 14-50 Counter Timing with Prescaler Value Changing from 1 to 4
205
Table 14-11 Tmrx Internal Trigger Connection
205
Figure 14-51 Overflow Event When PRBEN=0
206
Figure 14-52 Overflow Event When PRBEN=1
206
Figure 14-53 Counter Timing Diagram with Internal Clock Divided by 4
206
Figure 14-54 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
206
Figure 14-55 OVFIF When RPR=2
207
Figure 14-56 Example of Encoder Interface Mode C
207
Table 14-12 Couting Direction Versus Encoder Signals
207
TMR Input Function
208
Figure 14-57 Input/Output Channel 1 Main Circuit
208
Figure 14-58 Channel 1 Input Stage
208
TMR Output Function
209
Figure 14-59 Channel Output Stage (Channel 1 to 3)
209
Figure 14-60 Channel 4 Output Stage
209
Figure 14-61 C1ORAW Toggles When Counter Value Matches the C1DT Value
210
Figure 14-62 Upcounting Mode and PWM Mode a
210
Figure 14-63 Up/Down Counting Mode and PWM Mode
210
Figure 14-64 One-Pulse Mode
211
Figure 14-65 Clearing Cxoraw(PWM Mode A) by EXT Input
211
Figure 14-66 Complementary Output with Dead-Time Insertion
211
TMR Break Function
212
Figure 14-67 Example of TMR Break Function
212
TMR Synchronization
213
Figure 14-68 Example of Reset Mode
213
Figure 14-69 Example of Suspend Mode
213
Figure 14-70 Example of Trigger Mode
213
Debug Mode
214
TMR1 Registers
214
TMR1 Control Register1 (TMR1_CTRL1)
214
Table 14-13 TMR1 Register Map and Reset Value
214
TMR1 Control Register2 (TMR1_CTRL2)
215
TMR1 Slave Timer Control Register (TMR1_STCTRL)
216
TMR1 Dma/Interrupt Enable Register (TMR1_IDEN)
217
TMR1 Interrupt Status Register (TMR1_ISTS)
218
TMR1 Software Event Register (TMR1_SW EVT)
219
TMR1 Channel Mode Register1 (TMR1_CM1)
219
TMR1 Channel Mode Register2 (TMR1_CM2)
221
TMR1 Channel Control Register (TMR1_CCTRL)
222
Table 14-14 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
223
TMR1 Counter Value (TMR1_CVAL)
224
TMR1 Division Value (TMR1_DIV)
224
TMR1 Period Register (TMR1_PR)
224
TMR1 Repetition Period Register (TMR1_RPR)
224
TMR1 Channel 1 Data Register (TMR1_C1DT)
224
TMR1 Channel 2 Data Register (TMR1_C2DT)
224
TMR1 Channel 3 Data Register (TMR1_C3DT)
225
TMR1 Channel 4 Data Register (Tmrx_C4Dt)
225
TMR1 Break Register (TMR1_BRK)
225
TMR1 DMA Control Register (TMR1_DMACTRL)
226
TMR1 DMA Data Register (TMR1_DM ADT)
226
Window Watchdog Timer (WWDT)
227
WWDT Introduction
227
WWDT Main Features
227
WWDT Functional Overview
227
Figure 15-1 Window Watchdog Block Diagram
227
Debug Mode
228
WWDT Registers
228
Control Register (WWDT_CTRL)
228
Figure 15-2 Window Watchdog Timing Diagram
228
Table 15-1 Minimum and Maximum Timeout Value When PCLK1=72 Mhz
228
Table 15-2 WWDT Register Map and Reset Value
228
Configuration Register (WWDT_CFG)
229
Status Register (WWDT_STS)
229
Watchdog Timer (WDT)
230
WDT Introduction
230
WDT Main Features
230
WDT Functional Overview
230
Figure 16-1 WDT Block Diagram
230
Debug Mode
231
WDT Registers
231
Command Register (WDT_CMD)
231
Divider Register (WDT_DIV)
231
Table 16-1 WDT Timeout Period (Lick=40Khz)
231
Table 16-2 WDT Register and Reset Value
231
Reload Register (WDT_RLD)
232
Status Register (WDT_STS)
232
Enhanced Real-Time Clock (ERTC)
233
ERTC Introduction
233
ERTC Main Features
233
Figure 17-1 ERTC Block Diagram
233
ERTC Function Overview
234
ERTC Clock
234
ERTC Initialization
234
Table 17-1 ERTC Register Map and Reset Values
234
Periodic Automatic Wakeup
236
ERTC Calibration
236
Reference Clock Detection
237
Time Stamp
237
Tamper Detection
238
Multiplexed Function Output
238
ERTC Wakeup
239
ERTC Registers
239
Table 17-2 ERTC Low-Power Mode Wakeup
239
Table 17-3 Interrupt Control Bits
239
Table 17-4 ERTC Register Map and Reset Values
239
ERTC Time Register (ERTC_TIME)
240
ERTC Date Register (ERTC_DATE)
240
ERTC Control Register (ERTC_CTRL)
241
ERTC Initialization and Status Register (ERTC_STS)
242
ERTC Divider Register (ERTC_DIV)
243
ERTC Wakeup Timer Register (ERTC_WAT)
243
ERTC Coarse Calibration Register (ERTC_CCAL)
244
ERTC Alarm Clock a Register (ERTC_ALA)
244
ERTC Alarm Clock B Register (ERTC_ALB)
245
ERTC Write Protection Register (ERTC_WP)
245
ERTC Subsecond Register (ERTC_SBS)
245
ERTC Time Adjustment Register (ERTC_TADJ)
245
ERTC Time Stamp Time Register (ERTC_TSTM)
246
ERTC Time Stamp Date Register (ERTC_TSDT)
246
ERTC Time Stamp Subsecond Register (ERTC_TSSBS)
246
ERTC Smooth Calibration Register (ERTC_SCAL)
246
ERTC Tamper Configuration Register (ERTC_TAMP)
247
ERTC Alarm Clock a Subsecond Register (ERTC_ALASBS)
248
ERTC Alarm Clock B Subsecond Register (ERTC_ALBSBS)
248
ERTC Battery Powered Domain Data Register (Ertc_Bprx)
248
Analog-To-Digital Converter (ADC)
249
ADC Introduction
249
ADC Main Features
249
ADC Structure
249
ADC Functional Overview
250
Channel Management
250
Figure 18-1 ADC1 Block Diagram
250
Internal Temperature Sensor
251
Internal Reference Voltage
251
ADC Operation Process
251
Power-On and Calibration
251
Figure 18-2 ADC Basic Operation Process
251
Trigger
252
Figure 18-3 ADC Power-On and Calibration
252
Table 18-1 Trigger Sources for ADC
252
Sampling and Conversion Sequence
253
Conversion Sequence Management
253
Sequence Mode
253
Figure 18-4 Sequence Mode
253
Automatic Preempted Group Conversion Mode
254
Repetition Mode
254
Partition Mode
254
Figure 18-5 Preempted Group Auto Conversion Mode
254
Figure 18-6 Repetition Mode
254
Data Management
255
Data Alignment
255
Data Read
255
Figure 18-7 Partition Mode
255
Figure 18-8 Data Alignment
255
Voltage Monitoring
256
Status Flag and Interrupts
256
ADC Registers
256
Table 18-2 ADC Register Map and Reset Values
256
ADC Status Register (ADC_STS)
257
ADC Control Register1 (ADC_CTRL1)
257
ADC Control Register2 (ADC_CTRL2)
258
ADC Sampling Time Register 1 (ADC_SPT1)
260
ADC Sampling Time Register 2 (ADC_SPT2)
261
ADC Voltage Monitor High Threshold Register (ADC_VWHB)
262
ADC Voltage Monitor Low Threshold Register (ADC_ VWLB)
262
ADC Ordinary Sequence Register 1 (ADC_ OSQ1)
262
ADC Ordinary Sequence Register 2 (ADC_ OSQ2)
263
ADC Ordinary Sequence Register 3 (ADC_ OSQ3)
263
ADC Preempted Sequence Register (ADC_ PSQ)
263
ADC Preempted Data Register X (ADC_ Pdtx) (X=1
264
ADC Ordinary Data Register (ADC_ ODT)
264
Controller Area Network (CAN)
265
CAN Introduction
265
CAN Main Features
265
Baud Rate
265
Figure 19-1 Bit Timing
265
Figure 19-2 Transmit Interrupt Generation
267
Interrupt Management
268
Figure 19-3 Transmit Interrupt Generation
268
Figure 19-4 Receive Interrupt 0 Generation
268
Figure 19-5 Receive Interrupt 1 Generation
268
Figure 19-6 Status Error Interrupt Generation
268
Design Tips
269
Functional Overview
269
General Description
269
Figure 19-7 CAN Block Diagram
269
Operating Modes
270
Test Modes
270
Message Filtering
271
Figure 19-8 32-Bit Identifier Mask Mode
271
Figure 19-9 32-Bit Identifier List Mode
271
Figure 19-10 16-Bit Identifier Mask Mode
271
Figure 19-11 16-Bit Identifier List Mode
272
Message Transmission
273
Figure 19-12 Transmit Mailbox Status
273
Message Reception
274
Error Management
275
CAN Registers
275
Figure 19-13 Receive FIFO Status
275
Table 19-1 CAN Register Map and Reset Values
275
CAN Control and Status Registers
277
CAN Master Control Register (CAN_MCTRL)
277
CAN Master Status Register (CAN_MSTS)
278
CAN Transmit Status Register (CAN_TSTS)
279
CAN Receive FIFO 0 Register (CAN_RF0)
282
CAN Receive FIFO 1 Register (CAN_RF1)
282
CAN Interrupt Enable Register (CAN_INTEN)
283
CAN Error Status Register (CAN_ESTS)
284
CAN Bit Timing Register (CAN_BTMG)
285
CAN Mailbox Registers
285
Figure 19-14 Transmit and Receive Mailboxes
285
Transmit Mailbox Identifier Register (Can_Tmix) (X=0
286
Transmit Mailbox Data Length and Time Stamp Register
286
(Can_Tmcx) (X=0
286
Transmit Mailbox Data Low Register (Can_Tmdtlx) (X=0
286
Transmit Mailbox Data High Register (Can_Tmdthx) (X=0
287
Receive FIFO Mailbox Identifier Register (Can_Rfix) (X=0
287
Receive FIFO Mailbox Data Length and Time Stamp Register
287
(Can_Rfcx) (X=0
287
Receive FIFO Mailbox Data Low Register
287
(Can_Rfdtlx) (X=0
287
Receive FIFO Mailbox Data High Register
288
(Can_Rfdthx) (X=0
288
CAN Filter Registers
288
CAN Filter Control Register (CAN_FCTRL)
288
CAN Filter Mode Configuration Register (CAN_FMCFG)
288
CAN Filter Bit Width Configuration Register (CAN_ FBWCFG)
288
CAN Filter FIFO Association Register (CAN_ FRF)
288
CAN Filter Activation Control Register (CAN_ FACFG)
289
CAN Filter Bank I Filter Bit Register (CAN_ Fifbx) (I=0
289
Universal Serial Bus Full-Seed Device Interface (OTGFS)
290
USBFS Structure
290
OTGFS Functional Description
290
Figure 20-1 Block Diagram of OTGFS Structure
290
OTGFS Clock and Pin Configuration
291
OTGFS Clock Configuration
291
OTGFS Pin Configuration
291
OTGFS Interrupts
291
Table 20-1 OTGFS Input/Output Pins
291
OTGFS Functional Description
292
OTGFS Initialization
292
Figure 20-2 OTGFS Interrupt Hierarchy
292
OTGFS FIFO Configuration
293
Device Mode
293
Table 20-2 OTGFS Transmit FIFO SRAM Allocation
293
Host Mode
294
Table 20-3 OTGFS Internal Register Storage Space Allocation
294
Refresh Controller Transmit FIFO
295
OTGFS Host Mode
295
Host Initialization
295
OTGFS Channel Initialization
296
Halting a Channel
296
Queue Depth
296
Figure 20-3 Writing the Transmit FIFO
297
Figure 20-4 Reading the Receive FIFO
297
Special Cases
298
Host HFIR Feature
298
Figure 20-5 HFIR Behavior When Hfirrldctrl=0X0
298
Initialize Bulk and Control in Transfers
299
Figure 20-6 HFIR Behavior When Hfirrldctrl=0X1
299
Initialize Bulk and Control OUT/SETUP Transfers
301
Figure 20-7 Example of Common Bulk/Control OUT/SETUP and Bulk/Control in Transfer
302
Initialize Interrupt in Transfers
303
Initialize Interrupt out Transfers
305
Figure 20-8 Shows an Example of Common Interrupt OUT/IN Transfers
306
Initialize Synchronous in Transfers
307
Initialize Synchronous out Transfers
308
Figure 20-9 Example of Common Synchronous OUT/IN Transfers
309
OTGFS Device Mode
310
Device Initialization
310
Endpoint Initialization on USB Reset
310
Endpoint Initialization on Enumeration Completion
311
Endpoint Initialization on Setaddress Command
311
Endpoint Initialization on Setconfiguration/Setinterface Command
311
Endpoint Activation
311
USB Endpoint Deactivation
312
Control Write Transfers (Setup/Data Out/Status IN)
312
Control Read Transfers (Setup/Data In/Status OUT)
312
Control Transfers (Setup/Status IN)
313
Read FIFO Packets
313
OUT Data Transfers
314
Figure 20-10 Read Receive FIFO
314
IN Data Transfers
316
Figure 20-11 SETUP Data Packet Flowchart
316
Non-Periodic (Bulk and Control) in Data Transfers
317
Non-Synchronous out Data Transfers
318
Synchronous out Data Transfers
320
Figure 20-12 BULK out Transfer Block Diagram
320
Enable Synchronous Endpoints
322
Incomplete Synchronous out Data Transfers
323
Incomplete Synchronous in Data Transfers
324
Periodic in (Interrupt and Synchronous) Data Transfers
325
OTGFS Control and Status Registers
326
CSR Register Map
326
Figure 20-13 CSR Memory Map
326
OTGFS Register Address Map
328
Table 20-4 OTGFS Register Map and Reset Values
328
OTGFS Global Registers
330
OTGFS Status and Control Register (OTGFS_GOTGCTL)
330
OTGFS Interrupt Status Control Register (OTGFS_GOTGINT)
331
OTGFS AHB Configuration Register (OTGFS_GAHBCFG)
331
OTGFS USB Configuration Register (OTGFS_GUSBCFG)
332
OTGFS Reset Register (OTGFS_GRSTCTL)
333
OTGFS Interrupt Register (OTGFS_GINTSTS)
335
OTGFS Interrupt Mask Register (OTGFS_GINTMSK)
338
OTGFS Receive Status Debug Read/Otg Status Read and POP Registers (OTGFS_GRXSTSR / OTGFS_GRXSTSP)
339
OTGFS Receive FIFO Size Register (OTGFS_GRXFSIZ)
340
Tx FIFO Size Registers (OTGFS_DIEPTXF0)
341
11OTGFS Non-Periodic Tx FIFO Size/Request Queue Status Register (OTGFS_GNPTXSTS)
341
OTGFS General Controller Configuration Register (OTGFS_GCCFG)
342
OTGFS Controller ID Register (OTGFS_GUID)
342
OTGFS Host Periodic Tx FIFO Size Register (OTGFS_HPTXFSIZ)
342
(X=1
343
Host-Mode Registers
343
OTGFS Host Mode Configuration Register (OTGFS_HCFG)
343
OTGFS Host Frame Interval Register (OTGFS_HFIR)
344
OTGFS Host Frame Number/Frame Time Remaining Register (OTGFS_HFNUM)
344
OTGFS Host Periodic Tx Fifo/Request Queue Register (OTGFS_HPTXSTS)
344
OTGFS Host All Channels Interrupt Register (OTGFS_HAINT)
345
OTGFS Host All Channels Interrupt Mask Register (OTGFS_HAINTMSK)
345
OTGFS Host Port Control and Status Register (OTGFS_HPRT)
345
(X = 0
347
OTGFS Host Channelx Interrupt Register (Otgfs_Hcintx)
348
(X = 0
348
(X = 0
349
OTGFS Host Channelx Transfer Size Register (Otgfs_Hctsizx)
349
Device-Mode Registers
349
OTGFS Device Configure Register (OTGFS_DCFG)
349
OTGFS Device Control Register (OTGFS_DCTL)
350
OTGFS Device Status Register (OTGFS_DSTS)
351
Table 20-5 Minimum Duration for Software Disconnect
351
OTGFS Device OTGFSIN Endpoint Common Interrupt Mask Register (OTGFS_DIEPMSK)
352
OTGFS Device out Endpoint Common Interrupt Mask Register (OTGFS_DOEPMSK)
353
OTGFS Device All Endpoints Interrupt Mask Register (OTGFS_DAINT)
353
OTGFS All Endpoints Interrupt Mask Register (OTGFS_DAINTMSK)
353
OTGFS Device in Endpoint FIFO Empty Interrupt Mask Register (OTGFS_DIEPEMPMSK)
354
OTGFS Device Control in Endpoint 0 Control Register (OTGFS_DIEPCTL0)
354
OTGFS Device in Endpoint -X Control Register (Otgfs_Diepctlx)
355
(X=X=1
355
OTGFS Device Control out Endpoint 0 Control Register (OTGFS_DOEPCTL0)
357
OTGFS Device Control out Endpoint -X Control Register (Otgfs_Doepctlx) (X=1
358
(X=0
360
(X=0
361
OTGFS Device in Endpoint 0 Transfer Size Register (OTGFS_DIEPTSIZ0)
361
OTGFS Device out Endpoint 0 Transfer Size Register (OTGFS_DOEPTSIZ0)
362
OTGFS Device in Endpoint -X Transfer Size Register (Otgfs_Dieptsizx) (X=1
362
OTGFS Device in Endpoint Transmit FIFO Status Register (Otgfs_Dtxfstsx) (X=1
363
OTGFS Device out Endpoint -X Transfer Size Register (Otgfs_Doeptsizx) (X=1
363
Power and Clock Control Registers
364
OTGFS Power and Clock Gating Control Register (OTGFS_PCGCCTL)
364
Comparator (COMP)
365
COMP Introduction
365
Main Features
365
Figure 21-1 Block Diagram of Comparator 1 and Comparator 2
365
Interrupt Management
366
Design Tips
366
Functional Overview
366
Analog Comparator
366
CMP Registers
367
Comparator Control and Status Register 1 (COMP_CTRLSTS1)
367
Table 21-1 CMP Register Map and Reset Values
367
Comparator Control/Status Register 2 (COMP_CTRLSTS2)
369
Debug (DEBUG)
370
Debug Introduction
370
Debug and Trace
370
I/O Pin Control
370
Table 22-1 Trace Function Enable
370
DEGUB Registers
371
DEBUG Device ID (DEBUG_IDCODE)
371
Table 22-2 Trace Function Mode
371
Table 22-3 DEBUG Register Address and Reset Value
371
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