1. Manuals
  2. Brands
  3. ARTERY Manuals
  4. Recording Equipment
  5. AT32WB415 Series
  6. Reference manual

ARTERY AT32WB415 Series Reference Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
®
ARM
-based 32-bit Cortex
timers, ADC, 2 COMPs, 6 communication interfaces
Feature
Wireless Bluetooth module
− Dual core Bluetooth
− 2.4 GHz low-power transceiver
− Clocks: 16 MHz crystal oscillator, 64 MHz PLL,
interal 32 kHz clock
− Peripherals: 8 x GPIOs with 2-channel PWM, 2 x
UARTs (UART21 is connected to MCU USART3)
Core: ARM®32-bit Cortex®-M4F CPU
− 150 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− DSP instructions
Memories
− 256 KBytes of Flash memory
− 18 Kbytes of boot code area used as a Bootloader
or as a general instruction/data memory (one-time-
configured)
− sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
− 32 KBytes of SRAM
Power control (PWC)
− 2.6 V ~ 3.6 V application suppy
− Power-on reset (POR)/ low-voltage reset (LVR), and
power voltage monitor (PVM)
− Low power: Sleep, Deepsleep, and Standby modes,
− VBAT supply for LEXT, ERTC and 42 x 16-bit battery
powered registers (BPR)
Clock and reset management (CRM)
− External master clock input
− Internal 48 MHz factory-trimmed clock (HICK),
accuracy 1% at T
+105 °C, with automatic clock calibration (ACC)
− PLL with configurable frequency multiplication
(31~500) and division factor (1~15)
− 32 kHz crystal oscillator (LEXT)
− Internal 40 kHz RC oscillator (LICK)
1 x 12-bit 0.5 μs A/D converter (up to 16 input
channels)
− Conversion range: 0 V to 3.6 V
2022.04.13
®
-M4 MCU with 256 KB Flash, sLib, USBFS, 11
SIG specification 5.0 compliant
®
=25 °C, 2.5 % at T
=-40 to
A
A
AT32WB415 Series Reference Manual
− Sample and hold capability
− Temperature sensor
2 x COMP
DMA: 12-channel DMA controller
− Peripherals supported: timers, ADC, SPI, I
USART
Debug mode
− Serial wire debug (SWD)
Fast I/O Interfaces
− All mappable to 16 external interrupt vectors
− Almost 5 V-tolerant
− All fast I/Os, registers accessible with f
Up to 11 Timers (TMR)
− 6 x 16-bit and 1 x 32-bit timers, each with 4 IC/OC/PWM
or pulse counter and quadrature (incremental) encoder
input
− 2 x Watchdog timers (WDT and WWDT)
− SysTick timer: 24-bit downcounter
ERTC: enhanced RTC
Up to 6 communication interfaces
− I
2
C interface (SMBus/PMBus)
− Up to 3 x USARTs (ISO7816 interface, LIN, IrDA and
modem control)
− SPI interface
− CAN interface (2.0B Active)
− USB full speed interface/host/OTG controller
− Infrared transmitter (IRTMR)
CRC Calculation Unit
96-bit ID (UID)
Packaging
− QFN48 7 x 7 mm
 List of Models
Internal Flash
AT32WB415CCU7-7
256 KBytes
Page 1
2
C and
speed
AHB
Model
Ver 2.00

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the AT32WB415 Series and is the answer not in the manual?

Questions and answers

Summary of Contents for ARTERY AT32WB415 Series

  • Page 1 AT32WB415 Series Reference Manual ® ® -based 32-bit Cortex -M4 MCU with 256 KB Flash, sLib, USBFS, 11 timers, ADC, 2 COMPs, 6 communication interfaces Feature − Sample and hold capability  Wireless Bluetooth module − Dual core Bluetooth SIG specification 5.0 compliant −...

  • Page 2: Table Of Contents

    AT32WB415 Series Reference Manual Contents System architecture ..............27 System overview ................29 1.1.1 ARM Cortex -M4 processor ............29 1.1.2 Bit band ..................29 1.1.3 Interrupt and exception vectors ............ 31 1.1.4 System Tick (SysTick ) ..............34 1.1.5 Reset ..................34 List of abbreviations for registers ..........
  • Page 3 AT32WB415 Series Reference Manual 4.1.2 System clock ................48 4.1.3 Peripheral clock ................48 4.1.4 Clock fail detector ............... 48 4.1.5 Auto step-by-step system clock switch .......... 48 4.1.6 Internal clock output ..............49 4.1.7 Interrupts ..................49 Reset ..................49 4.2.1 System reset ................
  • Page 4 AT32WB415 Series Reference Manual 5.4.1 Unlock/lock ................. 67 5.4.2 Erase operation ................67 5.4.3 Programming operation..............68 5.4.4 Read operation ................70 Flash memory protection .............. 70 5.5.1 Access protection ................ 70 5.5.2 Erase/program protection............. 70 Special functions ................. 71 5.6.1 Security library settings ...............
  • Page 5 AT32WB415 Series Reference Manual Introduction ................. 80 Functional overview ..............80 6.2.1 GPIO structure ................80 6.2.2 GPIO reset status ................ 80 6.2.3 General-purpose input configuration ..........81 6.2.4 Analog input/output configuration ..........81 6.2.5 General-purpose output configuration ........... 81 6.2.6 GPIO port protection ..............
  • Page 6 AT32WB415 Series Reference Manual 7.3.6 IOMUX external interrupt configuration register4 (IOMUX_EXINTC4) 92 7.3.7 IOMUX remap register2 (IOMUX_REMAP2) ........92 7.3.8 IOMUX remap register3 (IOMUX_REMAP3) ........93 7.3.9 IOMUX remap register4 (IOMUX_REMAP4) ........93 7.3.10 IOMUX remap register5 (IOMUX_REMAP5) ........94 7.3.11 IOMUX remap register6 (IOMUX_REMAP6) ........
  • Page 7 AT32WB415 Series Reference Manual 9.4.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…7) .. 109 9.4.4 DMA channel-x number of data register (DMA_CxDTCNT) (x = 1…7) 110 9.4.5 DMA channel-x peripheral address register (DMA_CxPADDR) (x = 1…7) .................... 110 9.4.6 DMA channel-x memory address register (DMA_CxMADDR) (x = 1…7)111 9.4.7 DMA channel source register (DMA_SRC_SEL0) ......
  • Page 8 AT32WB415 Series Reference Manual 11.5.8 Clock control register (I2C_ CLKCTRL) ........133 Universal synchronous/asynchronous receiver/transmitter (USART) 135 12.1 USART introduction ..............135 12.2 Full-duplex/half-duplex selector ..........137 12.3 Mode selector ................137 12.3.1 Introduction................137 12.3.2 Configuration procedure ............. 137 12.4 USART frame format and configuration ........
  • Page 9 AT32WB415 Series Reference Manual 13.2 Functional overview ..............149 13.2.1 SPI description ................149 13.2.2 Full-duplex/half-duplex selector ..........150 13.2.3 Chip select controller ..............152 13.2.4 SPI_SCK controller ..............152 13.2.5 CRC ..................152 13.2.6 DMA transfer ................153 13.2.7 Transmitter ................154 13.2.8 Receiver ..................
  • Page 10 AT32WB415 Series Reference Manual 14.1.4.3 Slave timer control reg ister (TMRx_STCTRL) ......175 14.1.4.4 DMA/interrupt enable register (TMRx_IDEN) ......176 14.1.4.5 Interrupt status register (TMRx_ISTS) ........177 14.1.4.6 Software event register (TMRx_SW EVT) ......... 178 14.1.4.7 Channel mode register1 (TMRx_CM1) ........178 14.1.4.8 Channel mode register2 (TMRx_CM2) ........
  • Page 11 AT32WB415 Series Reference Manual 14.2.4.10 Period register (TMR9_PR) ..........197 14.2.4.11 Channel 1 data register (TMR9_C1DT) ......... 197 14.2.4.12 Channel 2 data register (TMR9_C2DT) ......... 198 14.2.5 TMR10 and TMR11 registers ............198 14.2.5.1 Control register1 (TMRx_CTRL1) ........... 198 14.2.5.2 DMA/interrupt enable register (TMRx_IDEN) ......199 14.2.5.3 Interrupt status register (TMRx_ISTS) ........
  • Page 12 AT32WB415 Series Reference Manual 14.3.4.13 TMR1 repetition period register (TMR1_RPR) ......224 14.3.4.14 TMR1 channel 1 data register (TMR1_C1DT) ......224 14.3.4.15 TMR1 channel 2 data register (TMR1_C2DT) ......224 14.3.4.16 TMR1 channel 3 data register (TMR1_C3DT) ......225 14.3.4.17 TMR1 channel 4 data register (TMRx_C4DT) ......225 14.3.4.18 TMR1 break register (TMR1_BRK) ........
  • Page 13 AT32WB415 Series Reference Manual 17.3.2 ERTC initialization ..............234 17.3.3 Periodic automatic wakeup ............236 17.3.4 ERTC calibration ................ 236 17.3.5 Reference clock detection ............237 17.3.6 Time stamp ................237 17.3.7 Tamper detection ............... 238 17.3.8 Multiplexed function output ............238 17.3.9 ERTC wakeup ................
  • Page 14 AT32WB415 Series Reference Manual 18.4.1 Channel management ..............250 18.4.1.1 Internal temperature sensor ........... 251 18.4.1.2 Internal reference voltage ............251 18.4.2 ADC operation process ............... 251 18.4.2.1 Power-on and calibration ............251 18.4.2.2 Trigger ................. 252 18.4.2.3 Sampling and conversion sequence ........253 18.4.3 Conversion sequence management ..........
  • Page 15 AT32WB415 Series Reference Manual 19.2 CAN main features ..............265 19.3 Baud rate .................. 265 19.4 Interrupt management ..............268 19.5 Design tips ................269 19.6 Functional overview ..............269 19.6.1 General description ..............269 19.6.2 Operating modes ................ 270 19.6.3 Test modes ................
  • Page 16 AT32WB415 Series Reference Manual 19.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ..... 288 19.7.3.3 CAN filter bit width configuration register (CAN_ FBW CFG) ..288 19.7.3.4 CAN filter FIFO association register (CAN_ FRF) ....288 19.7.3.5 CAN filter activation control register (CAN_ FACFG) ....289 19.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx) (i=0..13;...
  • Page 17 AT32WB415 Series Reference Manual 20.5.4.5 Endpoint initialization on SetConfiguration/SetInterface command 311 20.5.4.6 Endpoint activation ............... 311 20.5.4.7 USB endpoint deactivation ............. 312 20.5.4.8 Control write transfers (SETUP/Data OUT/Status IN) ....312 20.5.4.9 Control read transfers (SETUP/Data IN/Status OUT) ....312 20.5.4.10 Control transfers (SETUP/Status IN) ........
  • Page 18 AT32WB415 Series Reference Manual 20.6.3.15OTGFS device IN endpoint Tx FIFO size register (OTGFS_DIEPTXFn) (x=1…3, where n is the FIFO number) ..........343 20.6.4 Host-mode registers ..............343 20.6.4.1 OTGFS host mode configuration register (OTGFS_HCFG) ..343 20.6.4.2 OTGFS host frame interval register (OTGFS_HFIR) ....344 20.6.4.3 OTGFS host frame number/frame time remaining register...
  • Page 19 AT32WB415 Series Reference Manual 20.6.5.12 OTGFS device control OUT endpoint -x control register (OTGFS_DOEPCTLx) (x=1…3, where x if endpoint number) ....358 20.6.5.13OTGFS device IN endpoint -x interrupt register (OTGFS_DIEPINTx) (x=0…3, where x if endpoint number) ..........360 20.6.5.14OTGFS device OUT endpoint -x interrupt register (OTGFS_DOEPINTx) (x=0…3, where x if endpoint number) ..........
  • Page 20 AT32WB415 Series Reference Manual 22.4.2 DEBUG control register (DEBUG_CTRL) ........371 Revision history ................373 2022.04.13 Page 20 Ver 2.00...
  • Page 21 AT32WB415 Series Reference Manual List of figures Figure 1-1 AT32WB415 Series microcontrollers system architecture ............. 28 Figure 1-2 Internal block diagram of Cortex ® -M4 ..................29 Figure 1-3 Comparison between bit-band region and its alias region: image A ......... 29 Figure 1-4 Comparison between bit-band region and its alias region: image B .........
  • Page 22 AT32WB415 Series Reference Manual Figure 13-8 Master half-duplex transmit ....................156 Figure 13-9 Slave half-duplex receive ....................... 156 Figure 13-10 Slave half-duplex transmit ....................157 Figure 13-11 Master half-duplex receive ....................157 Figure 13-12 SPI interrupts ........................157 Figure 14-1 General-purpose timer block diagram ................... 163 Figure 14-2 Control circuit with CK_INT divided by 1 ................
  • Page 23 AT32WB415 Series Reference Manual Figure 14-41 Example of reset mode ......................190 Figure 14-42 Example of suspend mode ....................190 Figure 14-43 Example of trigger mode ...................... 190 Figure 14-44 Block diagram of advanced-control timer ................203 Figure 14-45 Control circuit with CK_INT divided by 1 ................204 Figure 14-46 Block diagram of external clock mode A ................
  • Page 24 AT32WB415 Series Reference Manual Figure 19-4 Receive interrupt 0 generation ....................268 Figure 19-5 Receive interrupt 1 generation ....................268 Figure 19-6 Status error interrupt generation .................... 268 Figure 19-7 CAN block diagram ........................ 269 Figure 19-8 32-bit identifier mask mode ....................271 Figure 19-9 32-bit identifier list mode ......................
  • Page 25 Table 1-1 Bit-band address mapping in SRAM ................... 30 Table 1-2 Bit-band address mapping in the peripheral area ............... 31 Table 1-3 AT32WB415 series vector table ....................31 Table 1-4 List of abbreviations for registers ....................36 Table 1-5 List of abbreviations for registers ....................36 Table 2-1 Flash memory organization (256 KB) ..................
  • Page 26 AT32WB415 Series Reference Manual Table 15-1 Minimum and maximum timeout value when PCLK1=72 MHz ..........228 Table 15-2 WWDT register map and reset value ..................228 Table 16-1 WDT timeout period (LICK=40kHz) ..................231 Table 16-2 WDT register and reset value ....................231 Table 17-1 ERTC register map and reset values ..................

  • Page 27: System Architecture

    AT32WB415 Series Reference Manual 1 System architecture ® ® AT32WB415 series microcontrollers incorporates a 32-bit ARM Cortex -M4 processor core, multiple 16-bit and 32-bit timers, DMA controller, ERTC, communication interfaces such as SPI, I2C, USART/UART, CAN bus controller, USB2.0 full-speed interface, 12-bit ADC, programmable voltage ®...

  • Page 28: Figure 1-1 At32Wb415 Series Microcontrollers System Architecture

    AT32WB415 Series Reference Manual Figure 1-1 AT32W B415 Series microcontrollers system architecture HEXT 4~25 MHz SWJTAG HICK 48 MHz Max. 150 MHz Cortex-M4F (Freq Max. 150 MHz) FCLK HCLK PCLK1 NVIC PCLK2 DMA1 Flash Flash 7Channel Controller POR/LVR DMA2 SRAM...

  • Page 29: System Overview

    AT32WB415 Series Reference Manual 1.1 System overview 1.1.1 ARM Cortex -M4 processor Cortex ® -M4 processor is a low-power consumption processor featuring low gate count, low interrupt latency, and low-cost debug. It supports DSP instruction set and FPU, and is applicable to deeply-embedded applications that require quicker response to interruption.

  • Page 30: Figure 1-4 Comparison Between Bit-Band Region And Its Alias Region: Image B

    AT32WB415 Series Reference Manual Figure 1-4 Comparison between bit-band region and its alias region: image B bitband alias region (total 32M bytes) 0x23FF_FFFC 0x23FF_FFF8 0x23FF_FFF4 0x23FF_FFF0 0x23FF_FFEC 0x23FF_FFE8 0x23FF_FFE4 0x23FF_FFE0 0x2200_001C 0x2200_0018 0x2200_0014 0x2200_0010 0x2200_000C 0x2200_0008 0x2200_0004 0x2200_0000 bitband region...

  • Page 31: Interrupt And Exception Vectors

    When it comes to multiple taks, it turns the read-modify-write operations into a hardware-supported atomic operation to avoid the scenario where the read-modify-write opearion is disrupted, resulting in disorder. 1.1.3 Interrupt and exception vectors Table 1-3 AT32WB415 series vector table Priority Pos. Priority Name...
  • Page 32 AT32WB415 Series Reference Manual Configu SVCall System service call via SWI instruction 0x0000_002C rable Configu Debug Monitor Debug monitor 0x0000_0030 rable Reserved 0x0000_0034 Configu PendSV Pendable request for system service 0x0000_0038 rable Configu SysTick System tick timer 0x0000_003C rable Configu...
  • Page 33 AT32WB415 Series Reference Manual Configu TMR4 TMR4 global interrupt 0x0000_00B8 rable Configu I2C1_EVT 0x0000_00BC C1 event interrupt rable Configu I2C1_ETR 0x0000_00C0 C1 error interrupt rable Reserved 0x0000_00C4 Reserved 0x0000_00C8 Reserved 0x0000_00CC Configu SPI2 SPI2 global interrupt 0x0000_00D0 rable Configu USART1...

  • Page 34: System Tick (Systick)

    AT32WB415 Series Reference Manual 1.1.4 System Tick (SysTick) The System Tick is a 24-bit downcounter. It will be reloaded with the initial value automatically when it is decremented to zero. It can generate periodic interrupts, so it is often used as multi-task scheduling counter for embedded operating system, and also to call the periodic tasks for non-embedded system.

  • Page 35: Figure 1-6 Example Of Msp And Pc Initialization

    0x0000_0004 0x0000_0000 0x2000_8000 In the AT32WB415 series, the main Flash memory, Boot code or SRAM can be remapped to the code area between 0x0000_0000 and 0x07FF_FFFF. BOOT1 and BOOT0 are used to set the specific memory from which CODE starts.

  • Page 36: List Of Abbreviations For Registers

    AT32WB415 Series Reference Manual 1.2 List of abbreviations for registers Table 1-4 List of abbreviations for registers Register type Description Software can read and write to this bit. Software can only read this bit. Software can only write to the bit. Reading it returns its reset value.

  • Page 37: Memory Resources

    AT32WB415 Series Reference Manual Abbr. Reset value Type Description Bit 31: 0 UID[95: 64] 0xXXXX XXXX UID for bit 95 to bit 64 Note: UID[95:88] is series ID, which is 0x011 for AT32WB415. 2 Memory resources 2.1 Internal memory address map Internal memory contains program memory (Flash), data memory (SRAM), peripheral registers and core registers.

  • Page 38: Flash Memory

    AT32WB415 Series Reference Manual 2.2 Flash memory AT32WB415 series provide up to 256 KB of on-chip Flash memory, supporting a single-cycle 32-bit read operation. Refer to Chapter 4.3.15 for more details about Flash memory controller and register configuration. Flash memory organization (256 KB) The main memory contains bank 1 (256 Kbytes), including 128 pages, 2 Kbytes per page.
  • Page 39 AT32WB415 Series Reference Manual Boundary address Peripherals 0x4001 4C00 - 0x4001 4FFF TMR9 timer 0x4001 3C00 - 0x4001 4BFF Reserved 0x4001 3800 - 0x4001 3BFF USART1 Reserved 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF...
  • Page 40 AT32WB415 Series Reference Manual Boundary address Peripherals Reserved 0x4000 2000 - 0x4000 23FF Reserved 0x4000 1C00 - 0x4000 1FFF Reserved 0x4000 1800 - 0x4000 1BFF Reserved 0x4000 1400 - 0x4000 17FF Reserved 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF...

  • Page 41: Power Control (Pwc)

    3 Power control (PWC) 3.1 Introduction For AT32WB415 series, its operating voltage supply is 2.6 V ~ 3.6 V, with a temperature range of - 40~+105 ℃. To reduce power consumption, this series provides three types of power saving modes, including Sleep, Deepsleep and Standby modes so as to achieve the best trade-off among the conflicting demands of CPU operating time, speed and power consumption.The AT32WB415 series have three...

  • Page 42: Por/Lvr

    AT32WB415 Series Reference Manual 3.3 POR/LVR A POR analog module embedded in the VDD/VDDA domain is used to generate a power reset. The power reset signal is released at V when the VDD is increased from 0 V to the operating voltage, or it is triggered at V when the VDD drops from the operating voltage to 0 V.

  • Page 43: Power Domain

    AT32WB415 Series Reference Manual 3.5 Power domain 1.2 V domain 1.2 V core domain includes a CPU core, SRAM, embedded digital peripherals and Phase Locked Loop (PLL). Such power domain is supplied by LDO (voltage regulator). It can be configured as power-on, low-power or power-off in three power saving modes.
  • Page 44 AT32WB415 Series Reference Manual The wakeup event can be generated by the following: Enabling a peripheral interrupt (it is not enabled in the NVIC) and enabling the SEVONPEND bit.  When the MCU resumes, the peripheral interrupt pending bit and NVIC channel pending bit must be cleared.

  • Page 45: Pwc Registers

    AT32WB415 Series Reference Manual 3.7 PWC registers The peripheral registers must be accessed by words (32 bit) Table 3-1 PW register map and reset values Register abbr. Offset Reset value PWC_CTRL 0x00 0x0000 0000 PWC_CTRLSTS 0x04 0x0000 0000 3.7.1 Power control register (PWC_CTRL)
  • Page 46 AT32WB415 Series Reference Manual 1: Power voltage is lower than the threshold Note: The power voltage monitor is stopped in Standby mode. Standby mode entry flag 0: Device is not in Standby mode Bit 1 1: Device is in Standby mode Note: This bit is set by hardware (enter Standby mode) and cleared by POR/LVR or by setting the CLSEF bit.

  • Page 47: Clock And Reset Manage (Crm)

    AT32WB415 Series Reference Manual 4 Clock and reset manage (CRM) 4.1 Clock AT32WB415 series provide different clock sources: HEXT oscillator clock, HICK oscillator clock, PLL clock, LEXT oscillator and LICK oscillator. Figure 4-1 AT32WB415 clock tree Peripheral 12S1/2 CLK clock enable...

  • Page 48: System Clock

    AT32WB415 Series Reference Manual The LEXT crystal/ceramic resonator provides a 32.768 KHz low-speed clock source. The LEXT clock signal is not released before it becomes stable. LEXT bypass clock: In this mode, an external clock source with a frequency of 32.768 kHzcan be provided. The external clock signal should be connected to the LEXT_IN pin while the LEXT_OUT can be released for GPI control.

  • Page 49: Internal Clock Output

    If a failure is detected on the HEXT clock, the CFD interrupt is generated. Such interrrpt is directly linked to CPU NMI. 4.2 Reset 4.2.1 System reset AT32WB415 series provide the following system reset sources:  NRST reset: on the external NRST pin  WDT reset: watchdog overflow ...

  • Page 50: Crm Registers

    AT32WB415 Series Reference Manual 4.3 CRM registers These peripheral registers have to be accessed by bytes (8 bits), half words (16 bits) or words (32 bits). Table 4-1 CRM register map and reset values Register Offset Reset value CRM_CTRL 0x000...

  • Page 51: Clock Configuration Register (Crm_Cfg)

    AT32WB415 Series Reference Manual 0: OFF. 1: ON High speed internal clock calibration The default value of this field is the initial factory calibration value. When the HICK output frequency is 48 MHz, it needs adjust 240 kHz (design value) based on this frequency for...
  • Page 52 AT32WB415 Series Reference Manual 010010: PLL x 19 010011: PLL x 20 …… 111110: PLL x 63 111111: PLL x 64 Note: The PLLRANGE bit must be programmed based on the PLL multiplication value. HEXT division selection for PLL entry clock）...

  • Page 53: Clock Interrupt Register (Crm_Clkint)

    AT32WB415 Series Reference Manual 4.3.3 Clock interrupt register (CRM_CLKINT) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value. Clock failure detection flag clear Writing 1 by software to clear CFDF.

  • Page 54: Apb2 Peripheral Reset Register (Crm_Apb2Rst)

    AT32WB415 Series Reference Manual LEXT stable flag Set by hardware. Bit 1 LEXTSTBLF 0: LEXT is not ready. 1: LEXT is ready. LICK stable interrupt flag Set by hardware. Bit 0 LICKSTBLF 0: LICK is not ready. 1: LICK is ready.

  • Page 55: Apb1 Peripheral Reset Register1 (Crm_Apb1Rst)

    AT32WB415 Series Reference Manual 4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Bit 31: 29 Reserved resd Kept at its default value. PWC reset Bit 28 PWCRST...

  • Page 56: Apb2 Peripheral Clock Enable Register (Crm_Ahb2En)

    AT32WB415 Series Reference Manual CRC clock enable Bit 6 CRCEN 0: Disabled 1: Enabled Bit 5 Reserved resd Kept at its default value. FLASH clock enable This bit is used to enable Flash clock in Sleep or Bit 4 FLASHEN Deepsleep mode.

  • Page 57: Apb1 Peripheral Clock Enable Register (Crm_Ahb1En)

    AT32WB415 Series Reference Manual IOMUX clock enable Bit 0 IOMUXEN 0: Disabled 1: Enabled 4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN) Access: 0 wait state, accessible by words, half-words and bytes. No-wait states in most cases. However, when accessing to peripherals on APB1, wait-states are inserted until the end of peripheral access on the APB1 bus.

  • Page 58: Battery Powered Domain Control Register (Crm_Bpdc)

    AT32WB415 Series Reference Manual 4.3.9 Battery powered domain control register (CRM_BPDC) Access: 0 to 3 wait states, accessible by words, half-words or bytes. Wait states are inserted in the case of consecutive accesses to this register. Note: LEXTEN, LEXTBYPS, ERTCSEL, and ERTCEN bits of the battery powered domain control register (CRM_BPDC) are in the battery powered domain.

  • Page 59: Apb Peripheral Reset Register (Crm_Apbrst)

    AT32WB415 Series Reference Manual POR/LVR reset flag Sety by hardware. Cleared by writing to the RSTFC bit. Bit 27 PORRSTF 0: No POR/LVR reset occurs 1: POR/LVR reset occurs. NRST pin reset flag Sety by hardware. Cleared by writing to the RSTFC bit.

  • Page 60: Additional Register (Crm_Misc1)

    AT32WB415 Series Reference Manual It should be noted the relationship between the PLL-FR values and post-division factors. 4.3.13 Additional register (CRM_MISC1) Name Reset value Type Description Clock output division 0xxx: Clock output 1000: Clock output divided by 2 1001: Clock output divided by 4...
  • Page 61 AT32WB415 Series Reference Manual recommended to enable the auto step-by-step system clock switch if the operational target is larger than 108 MHz,. Once it is enabled, the AHB bus is halted by hardware till the completion of the switch. During this switch period, the DMA remain working, and the interrupt events are recorded and then handled by NVIC when the AHB bus resumes.

  • Page 62: Flash Memory Controller (Flash)

    AT32WB415 Series Reference Manual 5 Flash memory controller (FLASH) 5.1 FLASH introduction Flash memory is divided into three parts: main Flash memory, information block and Flash memory registers.  Main Flash memory is up to 256 KB Information block consists of 18 KB boot loader and the user system data area. The boot loader ...

  • Page 63: Flash Memory Operation

    AT32WB415 Series Reference Manual Data1[7: 0]: User data 1 (It is stored in the FLASH_USD[25: 18] [23: 16] register) [31: 24] nData1[7: 0]: Inverse code of Data1[7: 0] EPP0[7:0]:Flash erase/write protection byte 0 (in the FLASH_EPPS[7: 0]） This field is used to protect page0~page15 of main Flash memory.

  • Page 64: Erase Operation

    AT32WB415 Series Reference Manual 5.2.2 Erase operation Erase operation must be done before programming. Flash memory erase includes page erase and mass erase. Page erase Any page in the Flash memory and its extension area can be erased with page erase function independently.

  • Page 65: Figure 5-2 Flash Memory Mass Erase Process

    AT32WB415 Series Reference Manual Mass erase Mass erase function can erase all the Flash memory. The following process is recommended:  Check the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress;...

  • Page 66: Programming Operation

    AT32WB415 Series Reference Manual 5.2.3 Programming operation The Flash memory can be programmed with 32 bits, 16 bits or 8 bits at a time. The following process is recommended:  Check the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress;...

  • Page 67: Read Operation

    AT32WB415 Series Reference Manual 5.2.4 Read operation Flash memory can be accessed through AHB bus of the CPU. 5.3 Main Flash memory extension area Bootloader code area can also be programmed as the extension area of the main Flash memory to store user-application code.

  • Page 68: Programming Operation

    AT32WB415 Series Reference Manual Figure 5-4 System data area erase process Start Check the OBF bit in FLASH_STS OBF = 0? Set USDERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read ODF bit in FLASH_STS 5.4.3...

  • Page 69: Figure 5-5 System Data Area Programming Process

    AT32WB415 Series Reference Manual Figure 5-5 System data area programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the USDPRGM bit = 1 in FLASH_CTRL Write word/half-word (32bits/16 bits) data Check the OBF bit in FLASH_STS...

  • Page 70: Read Operation

    AT32WB415 Series Reference Manual 5.4.4 Read operation User system data area can be accessed through AHB bus of the CPU. 5.5 Flash memory protection Flash memory includes access and erase/program protection. 5.5.1 Access protection Flash memory access protection is divided into two parts: high-levela and lowe level.

  • Page 71: Special Functions

    AT32WB415 Series Reference Manual Erase/program operation is not permitted under one of the following events, and the EPPERR bit is set accordingly:  The pages (Flash memory and its extended area) with erase/program protection enabled The sectors (Flash memory and its extended area) with erase/program protection enabled ...

  • Page 72: Bootloader Code Area Used As Flash Memory Extension

    AT32WB415 Series Reference Manual  Program the code to be saved in security library Perform system reset, and then reload security library setting words   Read the SLIB_STS0/STS1 register to verify the security library settings Note: It is not permissible to program the main Flash and its extended area as a security library simultaneously;...

  • Page 73: Flash Memory Registers

    AT32WB415 Series Reference Manual 5.7 Flash memory registers These peripheral registers must be accessed by words (32 bits). Table 5-4 Flash memory interface—Register map and reset value Register Offset Reset value FLASH_PSR 0x00 0x0000 0030 FLASH_UNLOCK 0x04 0xXXXX XXXX FLASH_USD_UNLOCK...

  • Page 74: Flash Unlock Register (Flash_Unlock)

    AT32WB415 Series Reference Manual 5.7.2 Flash unlock register (FLASH_UNLOCK) Abbr. Reset value Type Description Unlock key value This is used to unlock Flash memory bank and its Bit 31: 0 UKVAL 0xXXXX XXXX wo extension area. Note: All these bits are write-only, and return 0 when being read.

  • Page 75: Flash Address Register (Flash_Addr)

    AT32WB415 Series Reference Manual unlocked properly, indicating that erase/program operation to the user system data is allowed. This bit is cleared by writing “0”, which will re-lock the user system data area. Operation lock This bit is set by default, indicating that Flash memory is protected against operations.

  • Page 76: Erase/Program Protection Status Register (Flas H_Epps)

    AT32WB415 Series Reference Manual match its inverse code in the user system data area. At this point, this byte and its inverse code will be forced to0xFF when being read. 5.7.8 Erase/program protection status register (FLASH_EPPS) Register Reset value Type...

  • Page 77: Security Library Password Clear Register (Slib_Pwd_Clr)

    AT32WB415 Series Reference Manual 5.7.11 Security library password clear register (SLIB_PWD_CLR) For Flash memory security library only. Register Reset value Type Description Security library password clear value This register is used to key in a correct sLib password in order to unlock sLib function.

  • Page 78: Flash Crc Check Result Register (Flash_Crc_Chkr)

    AT32WB415 Series Reference Manual 5.7.15 Flash CRC check result register (FLASH_CRC_CHKR) For Flash memory and its extension area only. Register Reset value Type Description CRC check result Bit 31: 0 CRC_CHKR 0x0000 0000 Note: All these bits are write-only, and return no response when being read.

  • Page 79: (Em_Slib_Set)

    AT32WB415 Series Reference Manual 5.7.18 Flash extension memory security library setting register (EM_SLIB_SET) For Flash extension area only. Register Reset value Type Description Kept at its default value Bit 31: 24 Reserved 0x00 resd Extension memory sLib instruction start page...

  • Page 80: General-Purpose I/Os (Gpios)

    AT32WB415 Series Reference Manual 6 General-purpose I/Os (GPIOs) 6.1 Introduction AT32WB415 series supports up to 28 bidirectional I/O pins. Each of these pins features communication, control and data collection.  Supports general-purpose I/O (GPIO) or multiplexed function I/O (IOMUX) Each pin can be configured by software as floating input, pull-up/pull-down input, analog ...

  • Page 81: General-Purpose Input Configuration

    AT32WB415 Series Reference Manual 6.2.3 General-purpose input configuration Mode IOFC HDRV IOMC[1] IOMC[0] ODT register Floating input Unused Pull-down input Pull-up input When I/O port is configured as input:  Get I/O states by reading the input data register. ...

  • Page 82: Gpio Configuration Register Low (Gpiox_Cfglr) (X=A

    AT32WB415 Series Reference Manual Register Offset Reset value GPIOx_ODT 0x0C 0x0000 0000 GPIOx_SCR 0x10 0x0000 0000 GPIOx_CLR 0x14 0x0000 0000 GPIOx_WPR 0x18 0x0000 0000 6.3.1 GPIO configuration register low (GPIOx_CFGLR) (x=A…F) Register Reset value Type Description GPIOx function configuration (y=0~7)

  • Page 83: Gpio Output Register (Gpiox_Odt) (X= A

    AT32WB415 Series Reference Manual 6.3.4 GPIO output register (GPIOx_ODT) (x= A…F) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Always 0. GPIOx output data Each bit represents an I/O port. As output: it indicates the output status of I/O port.

  • Page 84: Multiplexed Function I/Os (Iomux)

    AT32WB415 Series Reference Manual 7 Multiplexed function I/Os (IOMUX) 7.1 Introduction AT32WB415 series support up to 28 bi-directional I/O pins. Each of the I/O pins feature communication, control and data collection. In addition, their main features also include:  Supports general-purpose I/O (GPIO) or multiplexed I/O (IOMUX), which will be detailed in this chapter.

  • Page 85: Mux Input Configuration

    AT32WB415 Series Reference Manual 7.2.2 MUX Input configuration When I/O ports are configured as multiplexed function input:  Get I/O pin state by reading input data registers  The pin be configured as floating input, pull-up or pull-down input ...

  • Page 86: Hardware Preemption

    AT32WB415 Series Reference Manual 7.2.5.1 Hardware preemption Certain pins are occupied by specific hardware functions regardless of the GPIO configuration. Table 7- 2 Hardware preemption Enable bit Description PWC_CTRLSTS[8] =1 Once enabled, PA0 pin acts as WKUP function of PWC.

  • Page 87: Iomux Registers

    AT32WB415 Series Reference Manual 7.3 IOMUX registers Table 7-5 shows IOMUX register map and their reset values, These peripheral registers must be accessed by words (32 bits). Note: MCU PA9, PA10, PA15, PB0, PB1, PB3~5, PB10~12, PC0~11, PD2, PF4~7 are disconnected.

  • Page 88: Iomux Remap Register (Iomux_Remap)

    AT32WB415 Series Reference Manual 7.3.2 IOMUX remap register (IOMUX_REMAP) Register Reset value Type Description Kept at its default value. Bit 31 Reserved resd Kept at its default value.. Bit 30: 27 Reserved resd SWD JTAG mutiplexing These bits are used to configure SWJTGA-related I/Os as GPIOs.

  • Page 89: Iomux External Interrupt Configuration Register1 (Iomux_Exintc1)

    AT32WB415 Series Reference Manual 01: EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 10: Unused 11: Unused USART3 IO multiplexing Select IO multiplexing for USART3. 00: TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 Bit 5: 4 USART3_MUX 01: TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14...

  • Page 90: Iomux External Interrupt Configuration Register2 (Iomux_Exintc2)

    AT32WB415 Series Reference Manual 0010: GPIOC pin0 0011: GPIOD pin0 0100: GPIOF pin0 Others: Reserved. 7.3.4 IOMUX external interrupt configuration register2 (IOMUX_EXINTC2) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. EXINT7 input source configuration Select the input source for EXINT7 external interrupt.

  • Page 91: Iomux External Interrupt Configuration Register3 (Iomux_Exintc3)

    AT32WB415 Series Reference Manual 7.3.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. EXINT11 input source configuration Select the input source for EXINT11 external interrupt. 0000: GPIOA pin11...

  • Page 92: Iomux External Interrupt Configuration Register4 (Iomux_Exintc4)

    AT32WB415 Series Reference Manual 7.3.6 IOMUX external interrupt configuration register4 (IOMUX_EXINTC4) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. EXINT15 input source configuration Select the input source for EXINT15 external interrupt. 0000: GPIOA pin15...

  • Page 93: Iomux Remap Register3 (Iomux_Remap3)

    AT32WB415 Series Reference Manual 7.3.8 IOMUX remap register3 (IOMUX_REMAP3) Register Reset value Type Description Bit 31: 12 Reserved 0x0000000 resd Kept at its default value. TMR11 IO general multiplexing Select IO multiplexing for TMR11. Bit 11: 8 TMR11_GMUX 0000: CH1/PB9...

  • Page 94: Iomux Remap Register5 (Iomux_Remap5)

    AT32WB415 Series Reference Manual 7.3.10 IOMUX remap register5 (IOMUX_REMAP5) Register Reset value Type Description Bit 31: 24 Reserved resd Kept at its default value. SPI2 IO general multiplexing Select IO multiplexing for SPI2. 0000: CS/PB12, SCK/PB13, MISO/PB14, MOSI/PB15 MCK/PC6 .

  • Page 95: Iomux Remap Register7 (Iomux_Remap7)

    AT32WB415 Series Reference Manual 7.3.12 IOMUX remap register7 (IOMUX_REMAP7) Register Reset value Type Description Bit 31: 21 Reserved resd Kept at its default value. PD0/PD1 mapped onto HEXT_IN / HEXT_OUT Select GPIO mapping for PD0 and PD1. This is applied to only 48-pin and 64-pin packages.

  • Page 96: Iomux Remap Register8 (Iomux_Remap8)

    AT32WB415 Series Reference Manual 7.3.13 IOMUX remap register8 (IOMUX_REMAP8) Register Reset value Type Description Keep at its default value. Bit 31: 8 Reserved resd Keep at its default value. Bit 7: 6 Reserved resd TMR2 channel 4 internal mapping 00, 01: TMR3_GMUX IO signal is connected to TMR2...

  • Page 97: External Interrupt/Event Controller (Exint)

    AT32WB415 Series Reference Manual 8 External interrupt/Event controller (EXINT) 8.1 EXINT introduction EXINT consists of 23 interrupt lines EXINT_LINE[22:0], each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT can enable or disable an interrupt or event...

  • Page 98: Exint Registers

    AT32WB415 Series Reference Manual Interrupt initialization procedure Select an interrupt source by setting IOMUX_EXINTCx register (This is required if GPIO is used  as an interrupt source) Select a trigger mode by setting EXINT_POLCFG1 and EXINT_POLCFG2 registers   Enable interrupt or event by setting EXINT_INTEN and EXINT_EVTEN registers Generate software trigger by setting EXINT_SWTRG register (This is applied to only software ...

  • Page 99: Polarity Configuration Register2 (Exint_ Polcfg2)

    AT32WB415 Series Reference Manual 8.3.4 Polarity configuration register2 (EXINT_ POLCFG2) Register Reset value Type Description Bit 31: 23 Reserved 0x000 resd Forced to be 0 by hardware. Falling polarity configuration bit on line x These bits are used to select a falling edge to trigger an interrupt and event on line x.

  • Page 100: Dma Controller (Dma)

    AT32WB415 Series Reference Manual 9 DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for 32-bit MCU applications with the aim of enhancing system performance and reducing the generation of interrupts. Two DMA controllers are available in the microcontroller. Each controller contains 7 DMA channels. Each channel manages memory access requests from one or more peripherals.

  • Page 101: Function Overview

    AT32WB415 Series Reference Manual 9.3 Function overview 9.3.1 DMA configuration 1. Set the peripheral address in the DMA_CxPADDR register The initial peripheral address for data transfer remains unchanged during transmission. 2. Set the memory address in the DMA_CxMADDR register The initial memory address for data transfer remains unchanged during transmission.

  • Page 102: Programmable Data Transfer Width

    AT32WB415 Series Reference Manual 9.3.4 Programmable data transfer width Transfer width of the source data and destination data is programmable through the PWIDTH and MWIDTH bits in the DMA_CxCTRL register. When PWIDTH is not equal to MWIDTH, it can be aligned according to the settings of PWIDTH/ MWIDTH.

  • Page 103: Errors

    AT32WB415 Series Reference Manual 9.3.5 Errors Table 9-1 DMA error event Error event Transfer error AHB response error occurred during DMA read/write access 9.3.6 Interrupts An interrupt can be generated on a DMA half-transfer, transfer complete and transfer error. Each channel has its specific interrupt flag, clear and enable bits, as shown in the table below.

  • Page 104: Table 9-5 Dma Flexible Request Sources

    AT32WB415 Series Reference Manual Table 9-5 DMA flexible request sources Request CHx_SRC Request source CHx_SRC DMA source CHx_SRC CHx_SRC Request source source No select ADC1 reserved reserved reserved reserved reserved reserved reserved reserved reserved SPI2_RX SPI2_TX reserved reserved reserved reserved...

  • Page 105: Dma Registers

    AT32WB415 Series Reference Manual 9.4 DMA registers Table 9-6 shows DMA register map and their reset values. These peripheral registers must be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). Table 9-6 DMA register map and reset value...

  • Page 106: Dma Interrupt Status Register (Dma_Sts)

    AT32WB415 Series Reference Manual 9.4.1 DMA interrupt status register (DMA_STS) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description 31: 28 Reserved resd Kept at its default value. Channel 7 data transfer error event flag...

  • Page 107: Dma Interrupt Flag Clear Register (Dma_Clr)

    AT32WB415 Series Reference Manual Channel 4 global event flag 0: No transfer error, half transfer or transfer complete event Bit 12 occurred. 1: Transfer error, half transfer or transfer complete event Channel 3 data transfer error event flag Bit 11 DTERRF3 0: No transfer error occurred.
  • Page 108 AT32WB415 Series Reference Manual Channel 7 transfer complete flag clear Bit 25 FDTFC7 rw1c 0: No effect 1: Clear the FDTF7 flag in the DMA_STS register Channel 7 global interrupt flag clear 0: No effect Bit 24 GFC7 rw1c 1: Clear the DTERRF7, HDTF7, FDTF7 and GF7 flag in...

  • Page 109: Dma Channel-X Configuration Register (Dma_Cxctrl) (X = 1

    AT32WB415 Series Reference Manual Channel 3 global interrupt flag clear 0: No effect Bit 8 GFC3 rw1c 1: Clear the DTERRF3, HDTF3, FDTF3 and GF3 flag in the DMA_STS register Channel 2 data transfer error flag clear Bit 7 DTERRFC2...

  • Page 110: Dma Channel-X Number Of Data Register (Dma_Cxdtcnt) (X = 1

    AT32WB415 Series Reference Manual Memory address increment mode Bit 7 MINCM 0: Disabled 1: Enabled. Peripheral address increment mode Bit 6 PINCM 0: Disabled 1: Enabled. Circular mode Bit 5 0: Disabled 1: Enabled. Data transfer direction Bit 4 0: Read from peripherals...

  • Page 111: Dma Channel-X Memory Address Register (Dma_Cxmaddr

    AT32WB415 Series Reference Manual 9.4.6 DMA channel-x memory address register (DMA_CxMADDR) (x = 1… 7) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Memory base address Memory address is the source or destination of data...

  • Page 112: Crc Calculation Unit (Crc)

    AT32WB415 Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC32 standard. The CRC_CTRL register is used to select input data toggle (word, REVOD=1) or output data toggle (byte, REVID=01;...

  • Page 113: Control Register (Crc_Ctrl)

    AT32WB415 Series Reference Manual 10.2.3 Control register (CRC_CTRL) Register Reset value Type Description Bit 31: 8 Reserved 0x000000 resd Kept at its default value. Reverse output data Set and cleared by software. This bit is used to control Bit 7...

  • Page 114: C Interface

    AT32WB415 Series Reference Manual 11 I C interface 11.1 I C introduction C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 400 kbit/s of communication speed.

  • Page 115: I 2 C Interface

    AT32WB415 Series Reference Manual 11.4 I C interface Figure 11-2 shows the block diagram of I C function Figure 11-2 I2C function block diagram Comparator Data Control Shift Register APB Interface Control register Data Clock OADDR Register Control Status I2C_DMA_req_tx...
  • Page 116 AT32WB415 Series Reference Manual  In 10-bit mode ― Only matches OADDR1 Support special slave address:  Broadcast call address (0b0000000x): This address is enabled when GCAEN=1.  SMBus device default address (0b1100001x): This address is enabled for SMBus address resolution protocol in SMBus device mode.

  • Page 117: C Slave Communication Flow

    AT32WB415 Series Reference Manual 11.4.1 I C slave communication flow Initialization Enable I C peripheral clock, and configure the clock-related bits in the I2C_CTRL2 register for a correct timing, and then wait for I C master to send a Start condition.

  • Page 118: C Master Communication Flow

    AT32WB415 Series Reference Manual is set 1 by hardware. EV2: When the data is written to DT register, it is directly moved to the shift register, and SCL bus is released. The TDBE is still set 1 at this time.

  • Page 119: Figure 11-5 Transfer Sequence Of Master Transmitter

    AT32WB415 Series Reference Manual Receiver: First send slave address head 0b11110xx0 (where xx refers to address [9:8]) and then address [7: 0], followed by the address head 0b11110xx1 (where xx refers to address [9: 8]), the master enters receiver mode.

  • Page 120: Figure 11-6 Transfer Sequence Of Master Receiver

    AT32WB415 Series Reference Manual EV3: When the data is written to the DT register, it is directly moved to the shift register and the SCL bus is released. The TDBE bit is still set 1 at this time. EV4: At this point, the DT register is empty but the shift register is full. Writing to the DT register will clear the TDBE bit.

  • Page 121: Figure 11-7 Transfer Sequence Of Master Receiver When N>2

    AT32WB415 Series Reference Manual  10-bit address mode: Generate Start condition (GENSTART=1) EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register. EV5: 10-bit address head sequence is sent. Read STS1 and write to DT register can clear the ADDRHF bit.

  • Page 122: Figure 11-8 Transfer Sequence Of Master Receiver When N=2

    AT32WB415 Series Reference Manual EV3: The RDBF bit is set 1 after receiving the byte, and it is cleared when the I2C_DT register is read. End of communication. 10-bit address mode:  Generate Start condition (GENSTART=1) EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register.

  • Page 123: Figure 11-9 Transfer Sequence Of Master Receiver When N=1

    AT32WB415 Series Reference Manual  7-bit address mode: Set MACKCTRL=1 in the I2C_CTRL1 register Generate Start condition (GENSTART=1) EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register. EV2: Address is matched successfully (ADDR7F=1). Clear the ACKEN bit and read STS1 before reading STS2 and clearing ADDR7F bit, the master enters receive state at this time.

  • Page 124: Data Transfer Using Dma

    AT32WB415 Series Reference Manual  7-bit address mode: Generate a Start condition (GENSTART=1) EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register. EV2: Address is matched successfully (ADDR7F=1). Clear the ACKEN bit, read STS1 and then STS2 will clear the ADDR7F bit.

  • Page 125: Smbus

    AT32WB415 Series Reference Manual Configure other parameters such as priority, memory data width, peripheral data width, interrupts, etc in the DMA_CHCTRL register Enable the DMA channel by setting CHEN=1 in the DMA_CxCTRL register I2C_CTRL2 register. Once the RDBE Enable DMA request by setting DMAEN=1 in the...
  • Page 126 AT32WB415 Series Reference Manual SMBus Alert SMBALERT is an optional signal that connects the ALERT pin between the host and the salve. With this signal, the slave notifies the host to access the slave. SMBALERT is a wired-AND signal. For more information about SMBus Alert, refer to SMBus2.0 protocol.

  • Page 127: C Interrupt Requests

    AT32WB415 Series Reference Manual 11.4.5 I C interrupt requests The following table lists all the I C interrupt requests. Interrupt event Event flag Enable control bit Start condition sent (Host) STARTF Address sent (host) or address matched (slave) ADDR7F 10-bit address head sent (host)

  • Page 128: Control Register1 (I2C_Ctrl1)

    AT32WB415 Series Reference Manual 11.5.1 Control register1 (I2C_CTRL1) Register Reset value Type Description C peripheral reset 0: I C peripheral is not at reset state. Bit 15 RESET 1: I C peripheral is at reset state. Note: This bit can be used only when the BUSYF bit is “1”, and no Stop condition is detected on the bus.

  • Page 129: Control Register2 (I2C_Ctrl2)

    AT32WB415 Series Reference Manual 0: Disabled 1: Enabled SMBus host: response to host address 0001000x SMBus slave: response to default device address 0001100x SMBus device mode 0: SMBus slave Bit 3 SMBMODE 1: SMBus host Forced to be 0 by hardware.

  • Page 130: Own Address Register1 (I2C_Oaddr1)

    AT32WB415 Series Reference Manual – OVER = 1 – PECERR = 1 – TMOUT = 1 – ALERTF = 1 C input clock frequency Correct input clock frequency must be set to generate correct timings. The range allowed is between 2 MHz and 120 MHz.

  • Page 131: Status Register1 (I2C_Sts1)

    AT32WB415 Series Reference Manual 11.5.6 Status register1 (I2C_STS1) Register Reset value Type Description SMBus alert flag In SMBus host mode: 0: No SMBus alert 1: SMBus alert event is received. In SMBus slave mode: Bit 15 ALERTF rw0c It indicates the receiving status of the default device address (0001100x) 0: Default device address is not received.
  • Page 132 AT32WB415 Series Reference Manual 0: The data is being transferred from the DT register to the shift register (the data is still loaded with the data at this point.) 1: The data has been moved from the DT register to the shift register.

  • Page 133: Status Register2 (I2C_Sts2)

    AT32WB415 Series Reference Manual software reads the STS1 register. 11.5.7 Status register2 (I2C_STS2) Register Reset value Type Description PEC value Bit 15: 8 PECVAL 0x00 Cleared when PECEN is reset. Received address 2 flag 0: Received address matches the contents of OADDR1...
  • Page 134 AT32WB415 Series Reference Manual C bus speed config In standard mode: High level= SPEED x T I2C_CLK Low level= SPEED x T I2C_CLK In fast mode: DUTYMODE = 0: High level= SPEED x T I2C_CLK Bit 11: 0 SPEED 0x000...

  • Page 135: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)

    AT32WB415 Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) serves an interface for communication by means of various configurations and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. With a programmable baud rate generator, USART offers up to 9.375 MBits/s of baud rate by setting the system...
  • Page 136 AT32WB415 Series Reference Manual  Programmable communication modes ─ NRZ standard format (Mark/Space) ─ LIN (Local Interconnection Network): LIN master with break generation capability and LIN slave with break detection capability ─ IrDA SIR: Support 3/16 bit duration in normal mode, and configurable duration in infrared low- power mode ─Asynchronous SmartCard protocol defined in ISO7816-3 standard: Support 0.5 or 1.5 stop bits in...

  • Page 137: Full-Duplex/Half-Duplex Selector

    AT32WB415 Series Reference Manual 12.2 Full-duplex/half-duplex selector The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in full-duplex or half-duplex mode, which is achieved by setting the corresponding registers. In two-wire unindirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin is used for data input.

  • Page 138: Usart Frame Format And Configuration

    AT32WB415 Series Reference Manual 12.4 USART frame format and configuration USART data frame consists of start bit, data bit and stop bit, with the last data bit being as a parity bit. USART idle frame size is equal to that of the data frame under current configuration, but all bits are 1.

  • Page 139: Baud Rate Generation

    AT32WB415 Series Reference Manual 12.6 Baud rate generation 12.6.1 Introduction USART baud rate generator uses an internal counter based on PCLK. The DIV (USART_BAUDR [15:0] register) represents the overflow value of the counter. Each time the counter is full, it denotes one-bit data.

  • Page 140: Receiver

    AT32WB415 Series Reference Manual register will clear the TDC bit; This bit can also be cleared by writing “0”, but this is valid only in DMA mode. 12.8 Receiver 12.8.1 Receiver introduction USART receiver has its individual REN control bit (bit 2 in the USART_CTRL1 register). The transmitter and receiver share the same baud rate that is programmable.

  • Page 141: Start Bit And Noise Detection

    AT32WB415 Series Reference Manual  The FERR bit is set. The USART receiver moves the invalid data from the receive shift register to the receive data  buffer.  In non-DMA mode, both FERR and RDBF are set at the same time. The latter will generate an interrupt.

  • Page 142: Interrupt Requests

    AT32WB415 Series Reference Manual When noise is detected in a data frame: The NERR bit is set at the same time as the RDBF bit   The invalid data is transferred from the receive shift register to the receive data buffer.

  • Page 143: Usart Registers

    AT32WB415 Series Reference Manual 12.11 USART registers These peripheral registers must be accessed by words (32 bits). Table 12-4 USART register map and reset value Register Offset Reset value USART_STS 0x00 0x0000 00C0 USART_DT 0x04 0x0000 0000 USART_BAUDR 0x08 0x0000 0000...

  • Page 144: Data Register (Usart_Dt)

    AT32WB415 Series Reference Manual 1: Overflow error is detected. Note: When this bit iset, the DT regiter content will not be lost, but the subsequent data will be overwritten. Noise error This bit is set by hardware when noise is detect on a received frame.
  • Page 145 AT32WB415 Series Reference Manual the transmitted data is replaced with the parity bit; Check whether the parity bit of the received data is correct. 0: Parity control is disabled. 1: Parity control is enabled. Parity selection This bit selects the odd or even parity after the parity control is enabled.

  • Page 146: Control Register2 (Usart_Ctrl2)

    AT32WB415 Series Reference Manual 12.11.5 Control register2 (USART_CTRL2) Register Reset value Type Description Bit 31: 15 Reserved 0x00000 resd Forced to be 0 by hardware. LIN mode enable 0: LIN mode is disabled. Bit 14 LINEN 1: LIN mode is enabled.

  • Page 147: Control Register3 (Usart_Ctrl3)

    AT32WB415 Series Reference Manual 12.11.6 Control register3 (USART_CTRL3) Register Reset value Type Description Forced to be 0 by hardware. Bit 31: 11 Reserved 0x000000 resd CTSCF interrupt enable 0: Interrupt is disabled. Bit 10 CTSCFIEN 1: Interrupt is enabled. CTS enable 0: CTS is disabled.

  • Page 148: Guard Time And Divider Register (Usart_Gdiv)

    AT32WB415 Series Reference Manual 12.11.7 Guard time and divider register (USART_GDIV) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Forced 0 by hardware. Smartcard guard time value This field specifies the guard time value. The transmission Bit 15: 8...

  • Page 149: Serial Peripheral Interface (Spi)

    AT32WB415 Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interace supports either the SPI protocol or the I S protocoal, depending on software configuration. This chapter gives an introduction of the main features and congiruation procedure of SPI used as SPI or I 13.2 Functional overview...

  • Page 150: Full-Duplex/Half-Duplex Selector

    AT32WB415 Series Reference Manual  Programmable data transfer order (MSB-first or LSB-first) Programmable error interrupt flags (receiver overflow error, master mode error and CRC error)   Programmable transmit data buffer empty interrupt and receive data buffer full interrupt ...

  • Page 151: Figure 13-4 Single-Wire Unidirectional Receive Only In Spi Slave Mode

    AT32WB415 Series Reference Manual Figure 13-4 Single-wire unidirectional receive only in SPI slave mode SPI master SPI slave MISO MISO MOSI MOSI In master mode, it is necessary to wait until the second-to-last RDBF bit is set and then another SPI_CPK period before disabling the SPI.

  • Page 152: Chip Select Controller

    AT32WB415 Series Reference Manual 13.2.3 Chip select controller The Chip select controller (CS) is used to enable hardware or software control for chip select signals through software configuration. This controller is used to select master/slave device in multi-processor mode, and to avoid conflicts on the data lines by enabling the SCK signal output followed by CS signal.

  • Page 153: Dma Transfer

    AT32WB415 Series Reference Manual  CRC calculation polynominal is configured by setting the SPI_CPOLY register. CRC enable: The CRC calculation is enabled by setting the CCEN bit. This operation will reset  the SPI_RCRC and SPI_TCRC registers. Select if or when the NTC bit is set, depending on DMA or CPU data register. See the following ...

  • Page 154: Transmitter

    AT32WB415 Series Reference Manual  Configure the destination of DMA transfer: Configure the memory address as the destination of DMA transfer in the DMA control register. Data will be loaded from the SPI_DT register to the programmed destination after reception request is received by DMA.

  • Page 155: Motorola Mode

    AT32WB415 Series Reference Manual generated if the RDBFIE bit is set. When the next received data is ready to be moved to the SPI_DT register, if the previous received data is still not read (RDBF=1), then the data overflow occurs. The previous receive data is not lost, but the next received data will do.

  • Page 156: Figure 13-7 Slave Full-Duplex Communications

    AT32WB415 Series Reference Manual Figure 13-7 Slave full-duplex communications Sampling Drive MISO MOSI TDBE flag Transmit buffer empty and RDBF flag software can write data BF flag Software needs to read the received data Half-duplex communication – master transmit Configured as follows:...

  • Page 157: Interrupts

    AT32WB415 Series Reference Manual FBN=0: 8-bit frame Slave transmit: 0xaa, 0xcc, 0xaa Figure 13-10 Slave half-duplex transmit Drive MISO Transmit buffer empty and TDBE flag software can write data BF flag Half-duplex communication – master receive Configured as follows: MSTEN=1: Master enable...

  • Page 158: Io Pin Control

    AT32WB415 Series Reference Manual 13.2.11 IO pin control Usually, the SPI is connected to external devices through four pins.  MISO: Master In/Slave Out. The pin receives data in master mode, and transmits data in slave mode.  MOSI: Master Out/Slave In. The pin transmits data in master mode, and receives data in slave mode.

  • Page 159: Spi Control Register2 (Spi_Ctrl2)

    AT32WB415 Series Reference Manual 1: Receive-only mode Software CS enable When this bit is set, the CS pin level is determined by the Bit 9 SWCSEN SWCSIL bit. The status of I/O level on the CK pin is invalid. 0: Disabled...

  • Page 160: Spi Status Register (Spi_Sts)

    AT32WB415 Series Reference Manual the I/O output on the CS pin is low; when this bit is 0, the I/O input on the CS pin must be set high. 0: Disabled 1: Enabled DMA transmit enable 0: Disabled Bit 1 DMATEN 1: Enabled。...

  • Page 161: Spicrc Register (Spi_Cpoly)

    AT32WB415 Series Reference Manual 13.3.5 SPICRC register (SPI_CPOLY) Register Reset value Type Description CRC polynomial This register contains the polynomial used for CRC Bit 15: 0 CPOLY 0x0007 calculation. Note: This register is valid only in SPI mode. 13.3.6 SPIRxCRC register (SPI_RCRC)

  • Page 162: Timer

    AT32WB415 Series Reference Manual 14 Timer AT32WB415 timers include basic timers, general-purpose timers, and advanced timers. Please refer to Section 14.1 Section 14.3 for the detailed function modes. All functions of different timers are shown in the following tables. Table 14-1 TMR functional comparison...

  • Page 163: Tmrx Main Features

    AT32WB415 Series Reference Manual 14.1.2 TMRx main features  Source of count clock is selectable : internal clock, external clock and internal trigger  16-bit up, down, up/down and encoder mode counter (TMR2/5 can be extended to 32-bit)  4 independent channels for input capture, output compare, PWM generation and one-pulse mode output ...

  • Page 164: Figure 14-3 Block Diagram Of External Clock Mode A

    AT32WB415 Series Reference Manual Figure 14-3 Block diagram of external clock mode A Note: The delay between the signal on the input side and the actual clock of the counter is due to the synchronization circuit. Figure 14-4 Counting in external clock mode A...

  • Page 165: Counting Mode

    AT32WB415 Series Reference Manual Each timer (TMR2 to TMR5) consists of a 16-bit prescaler, which is used to generate the CK_CNT that enables the counter to count. The frequency division relationship between the CK_CNT and TMR_CLK can be adjusted by setting the value of the TMRx_DIV register. The prescaler value can be modified at any time, but it takes effect only when the next overflow event occurs.

  • Page 166: Figure 14-9 Overflow Event When Prben=1

    AT32WB415 Series Reference Manual Figure 14-9 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event.

  • Page 167: Tmr Input Function

    AT32WB415 Series Reference Manual Table 14-3 Couting direction versus encoder signals C1INFP1 signal C2INFP2 signal Level on opposite signal Active edge (C1INFP1 to C2IN, C2INFP2 to C1IN) Rising Falling Rising Falling High Down No count No count Count on C1IN only...

  • Page 168: Tmr Output Function

    AT32WB415 Series Reference Manual Input mode In input mode, the TMRx_CxDT registers latch the current counter values after the selected triggle signal is detected, and the capture compare interrupt flag bit (CxIF) is set. An interrupt or a DMA request will be generated if the CxIEN and CxDEN bits are enabled.

  • Page 169: Figure 14-16 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32WB415 Series Reference Manual  Output compare mode: Set CxOCTRL=3’b001/010/011 to enable output compare mode. In this case, when the counter value matches the value of the CxDT register, the CxORAW is forced high, low or toggling.  One-pulse mode：This is a particular case of PWM mode. Set OCMEN=1 to enable one-pulse mode.

  • Page 170: Tmr Synchronization

    AT32WB415 Series Reference Manual Figure 14-18 Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW ≥32 C1DT[15：0] C1ORAW Figure 14-19 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT CxORAW clear When the CxOSEN bit is set, the CxORAW signal for a given channel is cleared by applying a high level to the EXT input.

  • Page 171: Figure 14-21 Example Of Reset Mode

    AT32WB415 Series Reference Manual Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal. An overflow event is generated when OVFS=0. Figure 14-21 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0]...

  • Page 172: Figure 14-24 Master/Slave Timer Connection

    AT32WB415 Series Reference Manual Master/slave timer interconnection Both Master and slave timer can be configured in different master and slave modes respectively. The combination of both them can be used for various purposes. Figure 14-24 provides an example of interconnection between master timer and slave timer.

  • Page 173: Debug Mode

    AT32WB415 Series Reference Manual Starting master and slave timers synchronously by an external trigger: In this example, configure the master timer as master/slave mode synchronously and enable its slave timer synchronization function. This mode is used for synchronization between master timer and slave timer.

  • Page 174: Control Register1 (Tmrx_Ctrl1)

    AT32WB415 Series Reference Manual TMRx_PR 0x2C 0x0000 0000 TMRx_C1DT 0x34 0x0000 0000 TMRx_C2DT 0x38 0x0000 0000 TMRx_C3DT 0x3C 0x0000 0000 TMRx_C4DT 0x40 0x0000 0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 14.1.4.1 Control register1 (TMRx_CTRL1) Register Reset value Type Description Bit 15: 11...

  • Page 175: Control Register2 (Tmrx_Ctrl2)

    AT32WB415 Series Reference Manual 14.1.4.2 Control register2 (TMRx_CTRL2) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value. C1IN selection 0: CH1 pin is connected to C1IRAW input Bit 7 C1INSEL 1: The XOR result of CH1, CH2 and CH3 pins is connected...

  • Page 176: Dma/Interrupt Enable Register (Tmrx_Iden)

    AT32WB415 Series Reference Manual 1: Enabled Subordinate TMR input selection This field is used to select the subordinate TMR input. 000: Internal selection 0 (IS0) 001: Internal selection 1 (IS1) 010: Internal selection 2 (IS2) 011: Internal selection 3 (IS3)

  • Page 177: Interrupt Status Register (Tmrx_Ists)

    AT32WB415 Series Reference Manual Channel 2 interrupt enable Bit 2 C2IEN 0: Disabled 1: Enabled Channel 1 interrupt enable Bit 1 C1IEN 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 14.1.4.5 Interrupt status register (TMRx_ISTS)

  • Page 178: Software Event Register (Tmrx_Sw Evt)

    AT32WB415 Series Reference Manual 14.1.4.6 Software event register (TMRx_SWEVT) Register Reset value Type Description Kept at its default value. Bit 15: 7 Reserved 0x000 resd Trigger event triggered by software This bit is set by software to generate a trigger event.
  • Page 179 AT32WB415 Series Reference Manual －OWCDIR=1, C1ORAW is high once TMRx_ C1DT <TMRx_CVAL, else low. Note: In the configurations othern than 000’, the C1OUT is connected to C1ORAW. The C1OUT output level is not only subject to the changes of C1ORAW, but also the output polarity set by CCTRL.

  • Page 180: Channel Mode Register2 (Tmrx_Cm2)

    AT32WB415 Series Reference Manual Channel 1 input divider This field defines Channel 1 input divider. 00: No divider. An input capture is generated at each active edge. Bit 3: 2 C1IDIV 01: An input compare is generated every 2 active edges...

  • Page 181: Channel Control Register (Tmrx_Cctrl)

    AT32WB415 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: 00: Output 01: Input, C3IN is mapped on C3IRAW 10: Input, C3IN is mapped on C4IRAW 11: Input, C3IN is mapped on STCI.

  • Page 182: Counter Value (Tmrx_Cval)

    AT32WB415 Series Reference Manual 14.1.4.10 Counter value (TMRx_CVAL) Register Reset value Type Description Counter value When TMR2 or TMR5 enables plus mode (the PMEN bit Bit 31: 16 CVAL 0x0000 in the TMR_CTRL1 register), the CVAL is expanded to 32 bits.

  • Page 183: Channel 3 Data Register (Tmrx_C3Dt)

    AT32WB415 Series Reference Manual 14.1.4.15 Channel 3 data register (TMRx_C3DT) Register Reset value Type Description Channel 3 data register When TMR2 or TMR5 enables plus mode (the PMEN bit Bit 31: 16 C3DT 0x0000 in the TMR_CTRL1 register), the C3DT is expanded to 32 bits.

  • Page 184: General-Purpose Timer (Tmr9 To Tmr11)

    AT32WB415 Series Reference Manual 14.2 General-purpose timer (TMR9 to TMR11) 14.2.1 TMRx introduction The general-purpose timer (TMR9 to TMR11) consists of a 16-bit counter supporting upcounting mode. These timers can be synchronized. 14.2.2 TMRx main features 14.2.2.1 TMR9 main features ...

  • Page 185: Tmrx Functional Overview

    AT32WB415 Series Reference Manual Figure 14-28 Block diagram of general-purpose TMR10/11 CxDT Edge detector input C1IRAW C1IFP1 C1ORAW Output C1OUT TMRX_CH1 TMRx_CH1 prescaler control Input filter CxDT output Stop, clear Trigger TMRxCLK from RCC CNT Counter Period register controller DIV prescaler...

  • Page 186: Counting Mode

    AT32WB415 Series Reference Manual Figure 14-31 Counting in external clock mode A Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer. Set the STIS[2: 0] bit to select internal trigger signal to enable counting.

  • Page 187: Tmr Input Function

    AT32WB415 Series Reference Manual Figure 14-33 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-34 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear 14.2.3.3 TMR input function TMR9 has two independent channels. Each timer of TMR10 and TMR11 has an independent channel.

  • Page 188: Tmr Output Function

    AT32WB415 Series Reference Manual  Set the filter bandwidth of C1IN signal (CxDF[3: 0]) Set the active edge on the C1IN channel by writing C1P=0 (rising edge) in the TMRx_CCTR  register  Program the capture frequency of C1IN signal (C1DIV[1: 0]) ...

  • Page 189: Tmr Synchronization

    AT32WB415 Series Reference Manual output signal behaves when PR=0x32 but CxDT is configured with a different value. gives an example of the combination between upcounting mode and one-pulse PWM Figure 14-40 mode B. The counter only counts only one cycle, and the output signal sents only one pulse.

  • Page 190: Debug Mode

    AT32WB415 Series Reference Manual Figure 14-41 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] CI1F1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low.

  • Page 191: Tmr9 Registers

    AT32WB415 Series Reference Manual 14.2.4 TMR9 registers These peripheral registers must be accessed by word (32 bits). TMR9 registers are mapped into a 16-bit addressable space. Table 14-7 TMR9 register map and reset value Register name Register Reset value TMR9_CTRL1...

  • Page 192: Slave Timer Control Register (Tmr9_Stctrl)

    AT32WB415 Series Reference Manual 14.2.4.2 Slave timer control register (TMR9_STCTRL) Register Reset value Type Description Bit 15:7 Reserved 0x000 resd Kept at its default value Subordinate TMR input selection This field is used to select the subordinate TMR input. 000: Internal selection 0 (IS0)

  • Page 193: Interrupt Status Register (Tmr9_Ists)

    AT32WB415 Series Reference Manual 14.2.4.4 Interrupt status register (TMR9_ISTS) Register Reset value Type Description Kept at its default value. Bit 15: 11 Reserved resd Channel 2 recapture flag Bit 10 C2RF rw0c Please refer to C1RF description. Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF=1.

  • Page 194: Software Event Register (Tmr9_Sw Evt)

    AT32WB415 Series Reference Manual 14.2.4.5 Software event register (TMR9_SWEVT) Register Reset value Type Description Kept at its default value. Bit 15: 7 Reserved 0x000 resd Trigger event triggered by software This bit is set by software to generate a trigger event.
  • Page 195 AT32WB415 Series Reference Manual – OWCDIR=0, C1ORAW is high once TMRx_C1DT>TMRx_CVAL, else low; － OWCDIR=1, C1ORAW is low once TMRx_ C1DT <TMRx_CVAL, else high; 111: PWM mode B － OWCDIR=0, C1ORAW is low once TMRx_ C1DT >TMRx_CVAL, else high; － OWCDIR=1, C1ORAW is high once TMRx_ C1DT <TMRx_CVAL, else low.

  • Page 196: Channel Control Register (Tmr9_Cctrl)

    AT32WB415 Series Reference Manual 0001: f , N=2 ���������������� ����_������ 1001: f /8, N=8 ���������������� ������ 0010: f , N=4 ���������������� ����_������ 1010: f /16, N=5 ���������������� ������ 0011: f , N=8 ���������������� ����_������ 1011: f /16, N=6 ���������������� ������...

  • Page 197: Counter Value (Tmr9_Cval)

    AT32WB415 Series Reference Manual 1: C1IN active edge is on its falling edge. When used as external trigger, C1IN is inverted. Channel 1 enable 0: Input or output is disabled Bit0 C1EN 1: Input or output is enabled Table 14-8 Standard CxOUT channel output control bit...

  • Page 198: Channel 2 Data Register (Tmr9_C2Dt)

    AT32WB415 Series Reference Manual 14.2.4.12 Channel 2 data register (TMR9_C2DT) Register Reset value Type Description Bit 31: 16 C2DT 0x0000 resd Kept at its default value. Channel 2 data register When the channel 2 is configured as input mode: The C2DT is the CVAL value stored by the last channel...

  • Page 199: Dma/Interrupt Enable Register (Tmrx_Iden)

    AT32WB415 Series Reference Manual 1: Disabled TMR enable 0: Enabled Bit 0 TMREN 1: Disabled 14.2.5.2 DMA/interrupt enable register (TMRx_IDEN) Register Reset value Type Description Kept at its default value Bit 15:2 Reserved 0x0000 resd Channel 1 interrupt enable 0: Disabled...

  • Page 200: Channel Mode Register1 (Tmrx_Cm1)

    AT32WB415 Series Reference Manual 14.2.5.5 Channel mode register1 (TMRx_CM1) The channel can be used in input (capture mode) or output (compare mode). The direction of a channel is defined by the corresponding CxC bits. All the other bits of this register have different functons in input and output modes.

  • Page 201: Channel Control Register (Tmrx_Cctrl)

    AT32WB415 Series Reference Manual 11: Input, C1IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS. Input capture mode: Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value.

  • Page 202: Counter Value (Tmrx_Cval)

    AT32WB415 Series Reference Manual 0: C1IN active edge is on its rising edge. When used as external trigger, C1IN is not inverted. 1: C1IN active edge is on its falling edge. When used as external trigger, C1IN is inverted. Channel 1 enable...

  • Page 203: Advanced-Control Timers (Tmr1)

    AT32WB415 Series Reference Manual 14.3 Advanced-control timers (TMR1) 14.3.1 TMR1 introduction The advanced-control timer TMR1 consists of a 16-bit counter supporting up and down counting modes, four capture/compare registers, and four independent channels to achieve embedded dead-time, input capture and programmable PWM output.

  • Page 204: Figure 14-45 Control Circuit With Ck_Int Divided By 1

    AT32WB415 Series Reference Manual Figure 14-45 Control circuit with CK_INT divided by 1 CK_INT TMREN COUNTER External clock (TRGIN/EXT) The counter clock can be provided by two external clock sources, namely, TRGIN and EXT signals. When SMSEL=3’111, external clock mode A is selected. Set the STIS[2: 0] bit to select TRGIN signal to drive the counter to start counting.

  • Page 205: Counting Mode

    AT32WB415 Series Reference Manual Figure 14-49 Counting in external clock mode B TMR_CLK CNT_CLK COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer. Set the STIS[2: 0] bit to select internal trigger signal to enable counting.

  • Page 206: Figure 14-51 Overflow Event When Prben=0

    AT32WB415 Series Reference Manual Figure 14-51 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-52 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed in the TMRx_PR register, and generates a counter underflow event.

  • Page 207: Figure 14-55 Ovfif When Rpr=2

    AT32WB415 Series Reference Manual Repetition counter mode: The repletion counter mode is enabled when the repetition counter value is not equal to 0. In this mode, the repetition counter is decremented at each counter overflow. An overflow event is generated when the repetition counter reaches 0.

  • Page 208: Tmr Input Function

    AT32WB415 Series Reference Manual 14.3.3.3 TMR input function The TMR1 has four independent channels. Each channel can be configured as input or output. As input, the channel can be used for the filtering, selection, division and input capture of the input signals.

  • Page 209: Tmr Output Function

    AT32WB415 Series Reference Manual 14.3.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. The advanced-control timer output function varies from one channel to one channel.

  • Page 210: Figure 14-61 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32WB415 Series Reference Manual gives an example of the combination between upcounting mode and PWM mode A. The Figure 14-62 output signal behaves when PR=0x32 but CxDT is configured with a different value. gives an example of the combination between up/down counting mode and PWM mode Figure 14-63 A.

  • Page 211: Figure 14-64 One-Pulse Mode

    AT32WB415 Series Reference Manual Figure 14-64 One-pulse mode CxORAW clear When the CxOSEN bit is set, the CxORAW signal for a given channel is cleared by applying a high level to the EXT input. The CxORAW signal remains unchanged until the next overflow event.

  • Page 212: Tmr Break Function

    AT32WB415 Series Reference Manual 14.3.3.5 TMR break function When the break function is enabled (BRKEN=1), the CxOUT 和 CxCOUT are jointly controlled by OEN, FCSODIS, FCSOEN, CxIOS and CxCIOS. But, CxOUT and CxCOUT cannot be set both to active level at the same time.

  • Page 213: Tmr Synchronization

    AT32WB415 Series Reference Manual 14.3.3.6 TMR synchronization The timers are linked together internnaly for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit; Slave timer is selected by setting the SMSEL[2: 0] bit. Slave modes include: Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal.

  • Page 214: Debug Mode

    AT32WB415 Series Reference Manual 14.3.3.7 Debug mode When the microcontroller enters debug mode (Cortex -M4 core halted), the TMRx counter stops counting by setting the TMRx_PAUSE in the DEBUG module. Refer to Chapter 30.2 for more information. 14.3.4 TMR1 registers These peripheral registers must be accessed by word (32 bits).

  • Page 215: Tmr1 Control Register2 (Tmr1_Ctrl2)

    AT32WB415 Series Reference Manual counts up 11: Two-way counting mode3, count up and down alternately, the output flag bit is set when the counter counts up / down One-way count direction Bit 4 OWCDIR 0: Up； 1: Down One cycle mode enable...

  • Page 216: Tmr1 Slave Timer Control Register (Tmr1_Stctrl)

    AT32WB415 Series Reference Manual 0: Control bits are updated by setting the HALL bit 1: Control bits are updated by setting the HALL bit or a rising edge on TRGIN. Bit 1 Reserved resd Kept at its default value. Channel buffer control...

  • Page 217: Tmr1 Dma/Interrupt Enable Register (Tmr1_Iden)

    AT32WB415 Series Reference Manual 000: Slave mode is disabled 001: Encoder mode A 010: Encoder mode B 011: Encoder mode C 100: Reset mode - Rising edge of the TRGIN input reinitializes the counter 101: Suspend mode - The counter starts counting when...

  • Page 218: Tmr1 Interrupt Status Register (Tmr1_Ists)

    AT32WB415 Series Reference Manual 14.3.4.5 TMR1 interrupt status register (TMR1_ISTS) Register Reset value Type Description Bit 15: 13 Reserved resd Kept at its default value. Channel 4 recapture flag C4RF rw0c Bit 12 Please refer to C1RF description. Channel 3 recapture flag...

  • Page 219: Tmr1 Software Event Register (Tmr1_Sw Evt)

    AT32WB415 Series Reference Manual 14.3.4.6 TMR1 software event register (TMR1_SWEVT) Register Reset value Type Description Bit 15: 8 Reserved 0x000 resd Kept at its default value. Break event triggered by software This bit is set by software to generate a break event.
  • Page 220 AT32WB415 Series Reference Manual 000: Disconnected. C1ORAW is disconnected from C1OUT; 001: C1ORAW is high when TMRx_CVAL=TMRx_C1DT 010: C1ORAW is low when TMRx_CVAL=TMRx_C1DT 011: Switch C1ORAW level when TMRx_CVAL=TMRx_C1DT 100: C1ORAW is forced low 101: C1ORAW is forced high. 110: PWM mode A －OWCDIR=0, C1ORAW is high once...

  • Page 221: Tmr1 Channel Mode Register2 (Tmr1_Cm2)

    AT32WB415 Series Reference Manual 0000: No filter, sampling is done at f ������ 1000: f /8, N=6 ���������������� ������ 0001: f , N=2 ���������������� ����_������ 1001: f /8, N=8 ���������������� ������ 0010: f , N=4 ���������������� ����_������ 1010: f /16, N=5 ����������������...

  • Page 222: Tmr1 Channel Control Register (Tmr1_Cctrl)

    AT32WB415 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: 00: Output 01: Input, C3IN is mapped on C3IRAW 10: Input, C3IN is mapped on C4IRAW 11: Input, C3IN is mapped on STCI.

  • Page 223: Table 14-14 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function

    AT32WB415 Series Reference Manual When the channel 1 is configured as output mode: 0: C1OUT is active high 1: C1OUT is active low When the channel 1 is configured as input mode: 0: C1IN active edge is on its rising edge. When used as external trigger, C1IN is not inverted.

  • Page 224: Tmr1 Counter Value (Tmr1_Cval)

    AT32WB415 Series Reference Manual Note: If the two outputs of a channel are not used (CxEN = CxCEN = 0), CxIOS, CxCIOS, CxP and CxCP must be cleared. Note: The state of the external I/O pins connected to the complementary CxOUT and CxCOUT channels depends on the CxOUT and CxCOUT channel state and the GPIO and the IOMUX registers.

  • Page 225: Tmr1 Channel 3 Data Register (Tmr1_C3Dt)

    AT32WB415 Series Reference Manual 14.3.4.16 TMR1 channel 3 data register (TMR1_C3DT) Register Reset value Type Description Channel 3 data register When the channel 3 is configured as input mode: The C3DT is the CVAL value stored by the last channel...

  • Page 226: Tmr1 Dma Control Register (Tmr1_Dmactrl)

    AT32WB415 Series Reference Manual TMRx_BRK: DTC, BRKEN, BRKV and AOEN TMRx_CTRL2: CxIOS and CxCIOS 10: Write protection level 2. The following bits and all bits in leve 3 are write protected: TMRx_CCTRL: CxP and CxCP TMRx_BRK: FCSODIS and FCSOEN 11: Write protection level 1. The following bits and all bits...

  • Page 227: Window Watchdog Timer (Wwdt)

    AT32WB415 Series Reference Manual 15 Window watchdog timer (WWDT) 15.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from generating a system reset. The window watch dog is used to detect the occurrence of system malfunctions.

  • Page 228: Debug Mode

    AT32WB415 Series Reference Manual Table 15-1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 15-2 Window watchdog timing diagram CNT[6：0] 55 54 52 51 50...

  • Page 229: Configuration Register (Wwdt_Cfg)

    AT32WB415 Series Reference Manual 15.5.2 Configuration register (WWDT_CFG) Register Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Kept at its default value. Reload counter interrupt Bit 9 RLDIEN 0: Disabled 1: Enabled Clock division value 00: PCLK1 divided by 4096...

  • Page 230: Watchdog Timer (Wdt)

    AT32WB415 Series Reference Manual 16 Watchdog timer (WDT) 16.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application.

  • Page 231: Debug Mode

    AT32WB415 Series Reference Manual Table 16-1 WDT timeout period (LICK=40kHz) Min.timeout (ms) Max. timeout (ms) Prescaler divider DIV[2: 0] bits RLD[11: 0] = 0x000 RLD[11: 0] = 0xFFF 409.6 819.2 1638.4 3276.8 6553.6 /128 13107.2 /256 (6 or 7) 26214.4 16.4 Debug mode...

  • Page 232: Reload Register (Wdt_Rld)

    AT32WB415 Series Reference Manual 16.5.3 Reload register (WDT_RLD) (Reset in Standby mode) Register Reset value Type Description Bit 31: 12 Reserved 0x00000 resd Kept at its default value. Reload value The write protection must be unlocked in order to enable...

  • Page 233: Enhanced Real-Time Clock (Ertc)

    AT32WB415 Series Reference Manual 17 Enhanced real-time clock (ERTC) 17.1 ERTC introduction The real-time clock provides a calendar clock function. The time and date can be modified by modifying the ERTC_TIME and ERTC_DATE register. The ERTC module is in battery powered domain, which means that it keeps running and free from the influence of system reset and VDD power off as long as VBAT is powered.

  • Page 234: Ertc Function Overview

    AT32WB415 Series Reference Manual 17.3 ERTC function overview 17.3.1 ERTC clock ERTC clock source (ERTC_CLK) is selected via clock controller from a LEXT, LICK, and divided HEXT (selected through the ERTCSEL[1: 0] bit in the CRM_BPDC register). The ERTC embeds two dividers: A and B, programmed by the DIVA[6: 0] and DIVB[14: 0] respectively.
  • Page 235 AT32WB415 Series Reference Manual ERTC_TSTM ERTC_TSDT ERTC_TSSBS Configurable ERTC_SCAL when CALUPDF=0 ERTC_TAMP Configurable ERTC_ALASBS when ALAWF =1 Configurable ERTC_ALASBS when ALBWF =1 ERTC_BPRx Clock and calendar initialization After the register write protection is unlocked, follow the procedure below for clock and calendar initialization: 1.

  • Page 236: Periodic Automatic Wakeup

    AT32WB415 Series Reference Manual Note: In Standby and Deepsleep modes, the current calendar values are not copied into the shadow registers. When waking up from these two modes, UPDF=0 must be asserted, and then wait until UPDF=1, to ensure that the latest calendar value can be read. In synchronous read (DREN=0) mode, the frequency of the PCLK1 must be at least seven times the ERTC_CLK frequency.

  • Page 237: Reference Clock Detection

    AT32WB415 Series Reference Manual Note: Coarse digital calibration can work correctly only when the DIVA is 6 or above. Smooth digital calibration: Smooth digital calibration has a higher and well-distributed performance than the coarse digital calibration. The calibration is performed by increasing or decreasing ERTC_CLK in an evenly manner.

  • Page 238: Tamper Detection

    AT32WB415 Series Reference Manual  Select a rising edge or falling edge to trigger time stamp by setting the TSEDG bit Enable time stamp by setting TSEN=1  How to save time stamp on a tamper event  Configure tamper detection registers ...

  • Page 239: Ertc Wakeup

    AT32WB415 Series Reference Manual 17.3.9 ERTC wakeup ERTC can be woken up by alarm clocks, periodic auto wakeup, time stamps or tamper events. To enable an ERTC interrupt, configure as follows: 1. Configure the EXINT line corresponding to ERTC interrupts as an interrupt mode and enable it, and select a rising edge 2.

  • Page 240: Ertc Time Register (Ertc_Time)

    AT32WB415 Series Reference Manual ERTC_ALB 0x20 0x0000 0000 ERTC_WP 0x24 0x0000 0000 ERTC_SBS 0x28 0x0000 0000 ERTC_TADJ 0x2C 0x0000 0000 ERTC_TSTM 0x30 0x0000 0000 ERTC_TSDT 0x34 0x0000 000D ERTC_TSSBS 0x38 0x0000 0000 ERTC_SCAL 0x3C 0x0000 0000 ERTC_TAMP 0x40 0x0000 0000...

  • Page 241: Ertc Control Register (Ertc_Ctrl)

    AT32WB415 Series Reference Manual 17.4.3 ERTC control register (ERTC_CTRL) Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value. Calibration output enable Bit 23 CALOEN 0: Calibration output disabled 1: Calibration output enabled Output source selection...

  • Page 242: Ertc Initialization And Status Register (Ertc_Sts)

    AT32WB415 Series Reference Manual 0: Date/time register direct read disabled. ERTC_TIME, ERTC_DATE and ERTC_SBS values are taken from the synchronized registers, which are updated once every two ERTC_CLK cycles 1: Date/time register direct read enabled. ERTC_TIME, ERTC_DATE and ERTC_SBS values are taken from the battery powered domain.

  • Page 243: Ertc Divider Register (Ertc_Div)

    AT32WB415 Series Reference Manual 1: Alarm clock event occurs Note: The clearing operation of this bit takes effect after two APB_CLK cycles. Initialization mode enable 0: Initialization mode disabled Bit 7 IMEN 1: Initialization mode enabled When an intitalization mode is entered, the calendar stops running.

  • Page 244: Ertc Coarse Calibration Register (Ertc_Ccal)

    AT32WB415 Series Reference Manual 17.4.7 ERTC coarse calibration register (ERTC_CCAL) Register Reset value Type Description Bit 31: 8 Reserved 0x000000 resd Kept at its default value. Calibration direction Bit 7 CALDIR 0: Positive calibration 1: Negative calibration Bit 6: 5...

  • Page 245: Ertc Alarm Clock B Register (Ertc_Alb)

    AT32WB415 Series Reference Manual 17.4.9 ERTC alarm clock B register (ERTC_ALB) Register Reset value Type Description Date/week day mask Bit 31 MASK4 0: Date/week day is not masked 1: Alarm clock doesn’t care about date/week day Date/week day select 0: Date...

  • Page 246: Ertc Time Stamp Time Register (Ertc_Tstm)

    AT32WB415 Series Reference Manual 17.4.13 ERTC time stamp time register (ERTC_TSTM) Register Reset value Type Description Bit 31: 23 Reserved 0x000 resd Kept at its default value AM/PM 0: AM Bit 22 AMPM 1: PM Note: This bit is applicable for 12-hour format only. It is 0 for 24-hour format.

  • Page 247: Ertc Tamper Configuration Register (Ertc_Tamp)

    AT32WB415 Series Reference Manual When the ADD is set, the actual number of ERTC_CLK is equal to 2 +512-DEC during the 2 ERTC_CLK periods. 17.4.17 ERTC tamper configuration register (ERTC_TAMP) Register Reset value Type Description Bit 31: 19 Reserved 0x0000...

  • Page 248: Ertc Alarm Clock A Subsecond Register (Ertc_Alasbs)

    AT32WB415 Series Reference Manual 17.4.18 ERTC alarm clock A subsecond register (ERTC_ ALASBS) Register Reset value Type Description Bit 31: 28 Reserved resd Kept at its default value Sub-second mask 0: No comparison. Alarm A doesn’t care about subseconds. 1: SBS[0] is compared...

  • Page 249: Analog-To-Digital Converter (Adc)

    AT32WB415 Series Reference Manual 18 Analog-to-digital converter (ADC) 18.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit digital signal. Its sampling rate is as high as 2 MSPS. It has up to 10 channels for sampling and conversion.

  • Page 250: Adc Functional Overview

    AT32WB415 Series Reference Manual Figure 18-1 ADC1 block diagram ADCDIV OCTESEL ADC prescaler PCLK2 ADCCLK TMR1_CH1 TMR1_CH2 TMR1_CH3 OCTEN TMR2_CH2 TMR4_CH4 ADC_IN1 EXINT11 ADC_IN0 Trigger TMR1_TRGOUT detection GPIO ADC_IN5 ADC_IN10 Ordinary ADCx_ETO_MUX conversion start ADC_IN11 OCSWTRG Temp.sensor TMR1_TRGOUT INTRV Channel...

  • Page 251: Internal Temperature Sensor

    AT32WB415 Series Reference Manual continues its conversion at the end of the preempted channel conversion. If the ordinary channel trigger occurs during the preempted channel conversion, the ordinary channel conversion won’t start until the end of the preempted channel conversion.

  • Page 252: Trigger

    AT32WB415 Series Reference Manual Calibration After power-on, the calibration is enabled by setting the ADCAL bit in the ADC_CTRL2 register. When the calibration is complete, the ADCAL bit is cleared by hardware and the conversion is performed by software trigger.

  • Page 253: Sampling And Conversion Sequence

    AT32WB415 Series Reference Manual Reserved Reserved 1001 1001 Reserved Reserved 1010 1010 Reserved Reserved 1011 1011 Reserved Reserved 1100 1100 1101 TMR1_TRGOUT event 1101 TMR1_CH1 event Reserved Reserved 1110 1110 Reserved Reserved 1111 1111 18.4.2.3 Sampling and conversion sequence The sampling period can be configured by setting the CSPTx bit in the ADC_SPT1 and ADC_SPT2 registers.

  • Page 254: Automatic Preempted Group Conversion Mode

    AT32WB415 Series Reference Manual 18.4.3.2 Automatic preempted group conversion mode The automatic preempted group conversion mode is enabled by setting the PCAUTOEN bit in the ADC_CTRL1 register. Once the ordinary channel conversion is over, the preempted group will automatically continue its conversion. This mode can work with the sequence mode. The preempted group conversion starts automatically at the end of the conversion of the ordinary group.

  • Page 255: Data Management

    AT32WB415 Series Reference Manual Figure 18-7 Partition mode OCLEN=4, OCPCNT=1, OSN1=ADC_IN5, OSN2=ADC_IN0, OSN3=ADC_IN2, OSN4=ADC_IN1, OSN5=ADC_IN17 Ordinary channel Ordinary channel Ordinary channel Ordinary channel trigger trigger trigger trigger ADC_IN5 ADC_IN0 ADC_IN2 ADC_IN1 ADC_IN17 ADC_IN5 ADC_IN0 CCE flag set CCE flag set...

  • Page 256: Voltage Monitoring

    AT32WB415 Series Reference Manual 18.4.5 Voltage monitoring The OCVMEN bit or PCVMEN bit in the ADC_CTRL1 register is used to enable voltage monitoring based on the converted data. The VMOR bit will be set if the converted result is outside the high threshold (ADC_VMHB register) or less than the low threshold (ADC_VMLB register).

  • Page 257: Adc Status Register (Adc_Sts)

    AT32WB415 Series Reference Manual 18.5.1 ADC status register (ADC_STS) Accessed by words. Register Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value. Ordinary channel conversion start flag This bit is set by hardware and cleared by software (writing...

  • Page 258: Adc Control Register2 (Adc_Ctrl2)

    AT32WB415 Series Reference Manual partitioned mode on ordinary channels. 0: Partitioned mode disabled on ordinary channels 1: Partitioned mode enabled on ordinary channels Preempted group automatic conversion enable after ordinary group Bit 10 PCAUTOEN 0: Preempted group automatic conversion disabled...
  • Page 259 AT32WB415 Series Reference Manual 0: Disabled 1: Enabled Trigger event select for ordinary channel conversion Bit 25 OCTESEL Bit 19: 17 Refer to Section 18.4.2.2 Kept at its default value Bit 16 Reserved resd Trigger mode enable for preempted channels conversion...

  • Page 260: Adc Sampling Time Register 1 (Adc_Spt1)

    AT32WB415 Series Reference Manual 18.5.4 ADC sampling time register 1 (ADC_SPT1) Accessed by words. Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value. Sample time selection of channel ADC_IN17 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles...

  • Page 261: Adc Sampling Time Register 2 (Adc_Spt2)

    AT32WB415 Series Reference Manual 18.5.5 ADC sampling time register 2 (ADC_SPT2) Accessed by words. Register Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value Bit 29: 27 Reserved resd Kept at its default value Bit 26: 24...

  • Page 262: Adc Voltage Monitor High Threshold Register (Adc_Vwhb)

    AT32WB415 Series Reference Manual Sample time selection of channel ADC_IN0 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 2: 0 CSPT0 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles 18.5.6 ADC preempted channel data offset register x ( ADC_ PCDTOx) (x=1..4)

  • Page 263: Adc Ordinary Sequence Register 2 (Adc_ Osq2)

    AT32WB415 Series Reference Manual 18.5.10 ADC ordinary sequence register 2 ( ADC_ OSQ2) Accessed by words. Register Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value Bit 29: 25 OSN12 0x00 Number of 12th conversion in ordinary sequence...

  • Page 264: Adc Preempted Data Register X (Adc_ Pdtx) (X=1

    AT32WB415 Series Reference Manual 18.5.13 ADC preempted data register x ( ADC_ PDTx) (x=1..4) Accessed by words. Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value Bit 15: 0 PDTx 0x0000 Conversion data from preempted channel 18.5.14 ADC ordinary data register (ADC_ ODT)

  • Page 265: Controller Area Network (Can)

    AT32WB415 Series Reference Manual 19 Controller area network (CAN) 19.1 CAN introduction CAN (Controller Area Network) is a distributed serial communication protocol for real-time and reliable data communication among various nodes. It supports the CAN protocol version 2.0A and 2.0B.
  • Page 266 AT32WB415 Series Reference Manual Baud rate formula: ���������������� = Nomal Bit Timimg ���������� ������ ������������ = t ��������_������ ��������1 ��������2 where = 1 x t ��������_������ �� = (1 + BTS1[3: 0]) x t ��������1 �� = (1 + BTS2[2: 0]) x t ��������2...

  • Page 267: Figure 19-2 Transmit Interrupt Generation

    AT32WB415 Series Reference Manual Figure 19-2 Transmit interrupt generation Inter-frame Inter-frame space or Data frame (standard identifier) space overload frame 44 + 8* N Ack field Data field Arbitration field Control field CRC field 8* N Inter-frame Inter-frame space or...

  • Page 268: Interrupt Management

    AT32WB415 Series Reference Manual 19.4 Interrupt management The CAN controller contains four interrupt vectors that can be used to enable or disable interrups by setting the CAN_INTEN register. Figure 19-3 Transmit interrupt generation Figure 19-4 Receive interrupt 0 generation RF0MN != 00...

  • Page 269: Design Tips

    AT32WB415 Series Reference Manual 19.5 Design tips The following information can be used as reference for CAN application development:  Debug control When the system enters the debug mode, the CAN controller stops or continues to work normally, depending on the CANx_PAUSE bit in the DEBUG_CTRL register or the PTD bit in the CAN_MCTRL register.

  • Page 270: Operating Modes

    AT32WB415 Series Reference Manual 19.6.2 Operating modes The CAN controller has three operating modes:  Sleep mode After a system reset, the CAN controller is in Sleep mode. In this mode, the CAN clock is stopped to reduce power consumption and an internal pull-up resistance is disabled. However, the software can still access to the mailbox registers.

  • Page 271: Message Filtering

    AT32WB415 Series Reference Manual 19.6.4 Message filtering The received message has to go through filtering by its identifier. If passed,the message will be stored in the correspoinding FIFOs. If not, the message will be discarded. The whole operation is done by hardware without using CPU resources.

  • Page 272: Figure 19-11 16-Bit Identifier List Mode

    AT32WB415 Series Reference Manual Figure 19-11 16-bit identifier list mode CAN_FiFB1[15:8] CAN_FiFB1[7:0] CAN_FiFB1[31:24] CAN_FiFB1[23:16] CAN_FiFB2[15:8] CAN_FiFB2[7:0] CAN_FiFB2[31:24] CAN_FiFB2[23:16] SID[10:0] EID[17:15] Mapping Filter match number 14 filter banks have different filtering effects dependent on the bit width mode. For example, 32-bit identifier mask mode contains the filters numbered n while 16-bit identifier list mode contains the filters numbered n, n+1, n+2 and n+3.

  • Page 273: Message Transmission

    AT32WB415 Series Reference Manual Priority rules When the CAN controller receives a frame of message, the message may pass through several filters. In this case, the filter match number stored in the receive mailbox is determined according to the following priority rules: ...

  • Page 274: Message Reception

    AT32WB415 Series Reference Manual Transmit priority configuration When two or more transmit boxes are in PENDING state, their transmit priority must be given. By identifier: When MMSSR=0 in the CAN_MCTRL register, the transmit order is defined by the identifier of the message in the mailbox. The message with lower identifier value has the highest priority. If the identifier values are the same, the message with lower mailbox number will be transmitted first.

  • Page 275: Error Management

    AT32WB415 Series Reference Manual Figure 19-13 Receive FIFO status Read Read Read Addr Addr Addr Address Address Address Address Address Address Address Address Address Write Write Write Addr Addr Addr （a）Receive a valid frame （b）Receive a valid frame （c）Receive a valid frame...
  • Page 276 AT32WB415 Series Reference Manual Register name Offset Reset value TMC1 194h 0xXXXX XXXX TMDTL1 198h 0xXXXX XXXX TMDTH1 19Ch 0xXXXX XXXX TMI2 1A0h 0xXXXX XXXX TMC2 1A4h 0xXXXX XXXX TMDTL2 1A8h 0xXXXX XXXX TMDTH2 1ACh 0xXXXX XXXX RFI0 1B0h 0xXXXX XXXX...

  • Page 277: Can Control And Status Registers

    AT32WB415 Series Reference Manual 19.7.1 CAN control and status registers 19.7.1.1 CAN master control register (CAN_MCTRL) Register Reset value Type Description Bit 31: 17 Reserved 0x0000 resd Kept at its default value. Prohibit trans when debug 0: Transmission works during debug 1: Transmission is prohibited during debug.

  • Page 278: Can Master Status Register (Can_Msts)

    AT32WB415 Series Reference Manual to be set by hardware, that is, the CAN will keep in sleep mode, by default. Freeze mode enable 0: Freeze mode disabled 1: Freeze mode enabled Note: The CAN leaves Freeze mode once 11 consecutive recessive bits have been detected on the RX pin.

  • Page 279: Can Transmit Status Register (Can_Tsts)

    AT32WB415 Series Reference Manual 0: The CAN is not in Sleep mode. 1: CAN is in Sleep mode. Note: This bit is used to decide whether the CAN is in Sleep mode or not. This bit acknowledges the Sleep mode request generated by software.
  • Page 280 AT32WB415 Series Reference Manual For example, when there are three messages are pending for transmission, the identifiers of mailbox 0, mailbox 1 and mailbox 2 are 0x400, 0x433 and 0x411 respectively, and the value of these two bits becomes 01.
  • Page 281 AT32WB415 Series Reference Manual This bit is set when the mailbox 1 transmission failed due to an arbitration lost. It is cleared by software writing 1 or by hardware at the start of the next transmission Transmit mailbox 1 transmission success flag 0: Transmission failed 1: Transmission was successful.

  • Page 282: Can Receive Fifo 0 Register (Can_Rf0)

    AT32WB415 Series Reference Manual 19.7.1.4 CAN receive FIFO 0 register (CAN_RF0) Register Reset value Type Description Bit 31: 6 Reserved 0x0000000 resd Kept at its default value. Receive FIFO 0 release 0: No effect 1: Release FIFO Note: This bit is set by software to release FIFO 0. It is cleared...

  • Page 283: Can Interrupt Enable Register (Can_Inten)

    AT32WB415 Series Reference Manual Note: This bit is set by hardware when three messages are pending in the FIFO 1. It is cleared by software by writing 1. Bit 2 Reserved resd Kept at its default value. Receive FIFO 1 message num...

  • Page 284: Can Error Status Register (Can_Ests)

    AT32WB415 Series Reference Manual 0: Receive FIFO 1 full interrupt disabled 1: Receive FIFO 1 full interrupt enabled Note: The flag bit of this interrupt is the RF1FF bit. An interrupt is generated when this bit and RF1FF bit are set.

  • Page 285: Can Bit Timing Register (Can_Btmg)

    AT32WB415 Series Reference Manual 0: Error passive state is not entered 1: Error passive state is entered Note: This bit is set by hardware when the current error times has reached the Error passive state limit (Receive Error Counter or Transmit Error Counter >127)

  • Page 286: Transmit Mailbox Identifier Register (Can_Tmix) (X=0

    AT32WB415 Series Reference Manual 19.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) Note: 1. This register is write protected when its mailboxes are pending for transmission. 2.This register implements the Transmit Request control (bit 0) — reset value 0. Register Reset value...

  • Page 287: Transmit Mailbox Data High Register (Can_Tmdthx) (X=0

    AT32WB415 Series Reference Manual 19.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) All the bits in the register are write protected when the mailbox is not in empty state. Register Reset value Type Description Bit 31: 24 TMDT7 0xXX Transmit mailbox data byte 7...

  • Page 288: Receive Fifo Mailbox Data High Register

    AT32WB415 Series Reference Manual 19.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1) Note: All the receive mailbox registers are read only. Register Reset value Type Description Bit 31: 24 RFDT7 0xXX Receive FIFO data byte 7 Bit 23: 16...

  • Page 289: Can Filter Activation Control Register (Can_ Facfg)

    AT32WB415 Series Reference Manual 19.7.3.5 CAN filter activation control register (CAN_ FACFG) Register Reset value Type Description Bit 31: 14 Reserved 0x00000 resd Kept at its default value Filter active enable Each bit corresponds to a filter bank. Bit 13: 0...

  • Page 290: Universal Serial Bus Full-Seed Device Interface (Otgfs)

    AT32WB415 Series Reference Manual 20 Universal serial bus full-seed device interface (OTGFS) The OTGFS software copyright is owned by Synopsys, Inc. All rights reserved. Used with permission. As a full-speed dual-role device, the OTGFS is fully compliant with the Universal Serial Bus Specification Revision2.0.

  • Page 291: Otgfs Clock And Pin Configuration

    AT32WB415 Series Reference Manual The OTGFS supports SOF pulse feature: a SOF pulse generates at a SOF packet, the pulse can output to the timer 2; Suspend mode is supported. The OTGFS goes into power-saving mode after Suspend mode is entered.

  • Page 292: Otgfs Functional Description

    AT32WB415 Series Reference Manual Figure 20-2 OTGFS interrupt hierarchy CORE Interrupt Global Interrupt Mask (Bit 0) AHB Configuration Register 7 6 5 4 3 2 1 0 Core interruput Core Interrupt Mask Register register Device All Interrupt Endpoints Interrupt Register...

  • Page 293: Otgfs Fifo Configuration

    AT32WB415 Series Reference Manual  Full-speed timeout standard bit USB turnaround time bit  4. The software must unmask the following bits in the OTGFS_GINTMSK register:  OTG interrupt mask  Mode mismatch interrupt mask 5. The software can read the CURMOD bit in the OTGFS_GINTSTS register to determine whether the OTGFS controller is operating in host or device mode.

  • Page 294: Host Mode

    AT32WB415 Series Reference Manual 3. Device IN endpoint transmit FIFO#1 size register (OTGFS_DIEPTXF1) OTGFS_DIEPTXF1.INEPTXFSTADDR=OTGFS_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0]  4. Device IN endpoint transmit FIFO#2 size register (OTGFS_DIEPTXF2)  OTGFS_DIEPTXF2.INEPTXFSTADDR=OTGFS_DIEPTXF1.INEPTXFSTADDR + tx_fifo_size[1] 5. Device IN endpoint transmit FIFO#i size register (OTGFS_DIEPTXFi) ...

  • Page 295: Refresh Controller Transmit Fifo

    AT32WB415 Series Reference Manual  OTGFS_GNPTXFSIZ.NPTXFDEP = tx_fifo_size[0] OTGFS_GNPTXFSIZ. NPTXFSTADDR = rx_fifo_size  3. OTGFS host periodic transmit FIFO size register (OTGFS_HPTXFSIZ)  OTGFS_HPTXFSIZ.PTXFSIZE = tx_fifo_size[1]  OTGFS_HPTXFSIZ.PTXFSTADDR = OTGFS_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0] 4. After SRAM allocation, refresh transmit FIFO and receive FIFO to ensure normal FIFO running.

  • Page 296: Otgfs Channel Initialization

    AT32WB415 Series Reference Manual 20.5.3.2 OTGFS channel initialization To communicate with the device, the application must enable and initialize at least one channel according to the following steps: 1. Unmask the following interrupts by setting the OTGFS_GINTMSK register:  Non-periodic transmit FIFO empty for OUT transfers ...

  • Page 297: Figure 20-3 Writing The Transmit Fifo

    AT32WB415 Series Reference Manual request queue before starting to write to the the transmit FIFO. The application must always write to the transmit FIFO in DWORDs. If the packet size is not aligned with DWORD, the application must use padding. The OTGFS host determines the actual packet size according to the programmed maximum packet size and transfer size.

  • Page 298: Special Cases

    AT32WB415 Series Reference Manual 20.5.3.5 Special cases (1) Handling babble conditions The OTGFS controller handles two cases of babble: packet babble and port babble. Packet babble occurs if the device sends more than the largest packet size for the channel. Port babble occurs if the...

  • Page 299: Initialize Bulk And Control In Transfers

    AT32WB415 Series Reference Manual 5. The HFIR register receives a new programmed value 6. Obtain SOF synchronization again after the first SOF is generated using the HFIR new feature Figure 20-6 shows the HFIR behavior when HFIRRLDCTRL=0x1 in the OTGFS_HFIR register.
  • Page 300 AT32WB415 Series Reference Manual determine the number of bytes received, and then read the receive FIFO. Following this step to unmask the RXFLVL interrupt 6. The controller generates the RXFLVL interrupt when the transfer complete status is written into the receive FIFO 7.

  • Page 301: Initialize Bulk And Control Out/Setup Transfers

    AT32WB415 Series Reference Manual else if (ACK) Reset Error Count Mask ACK else if (DATATGLERR) Reset Error Count 20.5.3.8 Initialize bulk and control OUT/SETUP transfers Figure 20-7 shows a typical bulk or control transfer OUT/SETUP transfer operation. Refer to channel 1 (ch_1) for more information.

  • Page 302: Figure 20-7 Example Of Common Bulk/Control Out/Setup And Bulk/Control In Transfer

    AT32WB415 Series Reference Manual Figure 20-7 Example of common Bulk/Control OUT/SETUP and Bulk/Control IN transfer Application Host Device init_reg(ch_1) init_reg(ch_2) Non-periodic Request Queue write_tx_fifo Assume that this queue (ch_1) can hold 4 entries. set_ch_en(ch_2) write_tx_fifo (ch_1) ch_1 set_ch_en(ch_2) ch_2 ch_1...

  • Page 303: Initialize Interrupt In Transfers

    AT32WB415 Series Reference Manual Unmask CHHLTD Disable Channel if (XactErr) Increment Error Count Unmask ACK else Reset Error Count else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (Do ping protocol for HS)
  • Page 304 AT32WB415 Series Reference Manual the OTGFS_HCCHAR2 register 4. The OTGFS host attempts to send an IN token in the next frame (odd) The OTGFS host generates a RXFLVL interrupt as soon as an IN packet is received and written to...

  • Page 305: Initialize Interrupt Out Transfers

    AT32WB415 Series Reference Manual Increment Error Count Unmask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count...

  • Page 306: Figure 20-8 Shows An Example Of Common Interrupt Out/In Transfers

    AT32WB415 Series Reference Manual Figure 20-8 shows an example of common interrupt OUT/IN transfers Application Host Device init_reg(ch_1) Periodic Request Queue init_reg(ch_2) Assume that this queue can hold 4 entries. write_tx_fifo(ch_1) set_ch_en(ch_2) ch_1 ch_2 Odd (micro) frame DATA0 XFERC init_reg(ch_1)

  • Page 307: Initialize Synchronous In Transfers

    AT32WB415 Series Reference Manual Reset Error Count Mask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count...

  • Page 308: Initialize Synchronous Out Transfers

    AT32WB415 Series Reference Manual not an IN packet (GRXSTSR.PKTSTS!= 0x0010) The controller generates an XFERC interrupt as soon as the receive packet is read To handle the XFERC interrupt, read the PKTCN bit in the OTGFS_HCTSIZ2 register. If the PKTCNT bit in the OTGFS_HCTSIZ2 is not equal to 0, disable the channel before re-initializing the channel for the next transfer.

  • Page 309: Figure 20-9 Example Of Common Synchronous Out/In Transfers

    AT32WB415 Series Reference Manual 1. Initialize channel 1 (according to OTGFS channel initialization requirements). The application must set the ODDFRM bit in the OTGFS_HCCHAR2 register 2. Write the first packet to the channel 1 3. Along with the last DWORD write of each packet, the host writes a reques to the periodic request queue 4.

  • Page 310: Otgfs Device Mode

    AT32WB415 Series Reference Manual else if (CHHLTD) Mask CHHLTD De-allocate Channel 20.5.4 OTGFS device mode 20.5.4.1 Device initialization The application must perform the following steps to initialize the controller during power-on or after switching a mode from host to device: 1.

  • Page 311: Endpoint Initialization On Enumeration Completion

    AT32WB415 Series Reference Manual  Program the OTGFS_DIEPTXF0 register to be able to transmit control IN data. The allocated SRAM is equal to at least 1 largest-packet-size of control endpoint 0 5. Reset the device addres in the device configuration register 6.

  • Page 312: Usb Endpoint Deactivation

    AT32WB415 Series Reference Manual  Largest packet size USB valid endpoint = 0x1   Endpoint start data toggle (for interrupt and bulk endpoints  Endpoint type  Transmit FIFO number 2. Once the endpoint is activated, the controller starts deconding the tokens issued to this endpoint and sends out a valid handshake for each valid token received for the endpoint 20.5.4.7 USB endpoint deactivation...

  • Page 313: Control Transfers (Setup/Status In)

    AT32WB415 Series Reference Manual end of the SETUP stage, the application must rewrite 3 to the SUPCNT bit in the OTGFS_DOEPTSIZx register to receive the subsequent SETUP packet  If the last SETUP packet received before the generation of the SETUP interrupt indicates data IN...

  • Page 314: Out Data Transfers

    AT32WB415 Series Reference Manual  SETUP packet mode: PKTSTS = SETUP, BCnt = 0x008, EPNUM = Control EP Num and DPID = D0, indicating that a SETUP packet for the specified endpoint is now available for reading from the receive FIFO ...
  • Page 315 AT32WB415 Series Reference Manual endpoints based on Device Initialization, and refer to Read FIFO packets for more information. 【Application requirements】 1. To receive a SETUP packet, the SUPCNT bit (OTGFS_DOEPTSIZx) on a control OUT endpoint must be programmed to be a non-zero value. When the application sets the SUPCNT bit to a non- zero value, the controller receives SETUP packets and writes them to the receive FIFO, irrespective of the NAK status bit and EPENA bit in the OTGFS_DOEPCTLx register.

  • Page 316: In Data Transfers

    AT32WB415 Series Reference Manual Figure 20-11 SETUP data packet flowchart Waiting for DOEPINTn.SETUP B2BSTUP Interrupt bit set? rem_supcnt = setup_addr = rd_reg(DOEPTSIZn) rd_reg(DOEPDMAn) setup_cmd[31:0] = mem[4-2* rem_supcnt] setup_cmd[31:0] = mem[setup_addr-8] setup_cmd[63:32] = mem[5-2* rem_supcnt] setup_cmd[63:32] = mem[setup_addr-4] Find setup cmd type...

  • Page 317: Non-Periodic (Bulk And Control) In Data Transfers

    AT32WB415 Series Reference Manual application can first write into the endpoint control register before writing the data into the data FIFO. Normally, except for setting the endpoint enable bit, the application must do a read modify write on the OTGFS_DIEPCTLx register to avoid modifying the contents of the register. If the space is enough, the application can write multiple data packets for the same endpoint into the transmit FIFO.

  • Page 318: Non-Synchronous Out Data Transfers

    AT32WB415 Series Reference Manual length packets according to the IN token, and the packet count is decremented automatically. 6. If there are no data in the FIFO on a received IN token and the packet count for the endpoint is 0, the controller generates an “IN token received when FIFO is empty”...
  • Page 319 AT32WB415 Series Reference Manual not detect multiple consecutive OUT data packets on the same endpoint with the same data PID. In this case, the packet count is not decremented.  If there is no space in the receive FIFO, synchronous or non-synchronous data packets are ignored and not written to the receive FIFO.

  • Page 320: Synchronous Out Data Transfers

    AT32WB415 Series Reference Manual Figure 20-12 BULK OUT transfer block diagram Host Device Application XFERSIZE = 512bytes int_out_ep PKTCNT = 1 wr_reg(DOEPTSIZn) EPENA = 1 CNAK = 1 wr_reg(DOEPCTLn) 512 bytes xact_1 idle until intr On new xfer or RXFIFO not...
  • Page 321 AT32WB415 Series Reference Manual 1. All the application requirements are the same as that of non-synchronous OUT data transfers. 2. For synchronous OUT data transfers, the transfer size and packet count must be set to the number of the largest-packet-size packets that can be received in a single frame and not exceed this size.

  • Page 322: Enable Synchronous Endpoints

    AT32WB415 Series Reference Manual 20.5.4.17 Enable synchronous endpoints After sending a Set interface control command to the device, a host enables the synchronous endpoints. Then the host can send the initial synchronous IN token in any frame before transmission in the sequence of BInterval.

  • Page 323: Incomplete Synchronous Out Data Transfers

    AT32WB415 Series Reference Manual  When an interrupt is generated (XFERC bit in OTGFS_DIEPINTx register), clear the XFERC interrupt; For the following transaction, repeat step 3-5 until the completion of data transfers.  When an interrupt is generated (INCOMPISOIN bit in OTGFS_GINTSTS register), clear the INCOMPISOIN interrupt;...

  • Page 324: Incomplete Synchronous In Data Transfers

    AT32WB415 Series Reference Manual receive the synchronous OUT data in the enxt frame by following the steps listed in “SETUP/Data IN/Status OUT” 3. When it receives an incomplete synchronous OUT data interrupt, the application must read the control registers of all synchronous OUT endpoints to determine which one of the endpoints has an incomplete data transfer in the current frame.

  • Page 325: Periodic In (Interrupt And Synchronous) Data Transfers

    AT32WB415 Series Reference Manual 20.5.4.20 Periodic IN (interrupt and synchronous) data transfers This section describes a typical periodic IN data transfer. To initialize the controller after power-on reset, the application must perform the steps list in OTGFS Initializtion. Before communicating with a host, the controller must follow the steps defined in Endpoint Initializtion to initialize endpoints.

  • Page 326: Otgfs Control And Status Registers

    AT32WB415 Series Reference Manual empty, the controller generates an INCOMPISOIN interrupt in the OTGFS_GINTSTS register. 【Application programming sequence (frame transfers)】 1. Program the OTGFS_DIEPTSIZx register 2. Program the OTGFS_DIEPCTLx register based on endpoint characteristics, and set the CNAK and endpoint enable bits 3.
  • Page 327 AT32WB415 Series Reference Manual 0000h The overall situation of the core CSRs(1024 byte) 0400h Host mode CSRs (1024 byte) 0800h Device mode CSRs (1024 byte) 0E00h Power and clock control CSRs (512 byte) 1000h Equipment EP 0/host channel 0 FIFO (4096 byte)

  • Page 328: Otgfs Register Address Map

    AT32WB415 Series Reference Manual 20.6.2 OTGFS register address map Table 20-4 shows the USB OTG register map and their reset values. These peripheral registers must be accessed by words (32-bit) Table 20-4 OTGFS register map and reset values Register name...
  • Page 329 AT32WB415 Series Reference Manual OTGFS_HCINTMSK2 0x54C 0x0000 0000 OTGFS_HCTSIZ2 0x550 0x0000 0000 OTGFS_HCCHAR3 0x560 0x0000 0000 OTGFS_HCINT3 0x568 0x0000 0000 OTGFS_HCINTMSK3 0x56C 0x0000 0000 OTGFS_HCTSIZ3 0x570 0x0000 0000 OTGFS_HCCHAR4 0x580 0x0000 0000 OTGFS_HCINT4 0x588 0x0000 0000 OTGFS_HCINTMSK4 0x58C 0x0000 0000...

  • Page 330: Otgfs Global Registers

    AT32WB415 Series Reference Manual OTGFS_DTXFSTS1 0x938 0x0000 0200 OTGFS_DIEPCTL2 0x940 0x0000 0000 OTGFS_DIEPINT2 0x948 0x0000 0080 OTGFS_DIEPTSIZ2 0x950 0x0000 0000 OTGFS_DTXFSTS2 0x958 0x0000 0200 OTGFS_DIEPCTL3 0x960 0x0000 0000 OTGFS_DIEPINT3 0x968 0x0000 0080 OTGFS_DIEPTSIZ3 0x970 0x0000 0000 OTGFS_DTXFSTS3 0x978 0x0000 0200...

  • Page 331: Otgfs Interrupt Status Control Register (Otgfs_Gotgint)

    AT32WB415 Series Reference Manual 20.6.3.2 OTGFS interrupt status control register ( OTGFS_GOTGINT) The application reads this register to know about which kind of OTG interrupt is generated, and writes this register to clear the OTG interrupt. Register Reset value Type...

  • Page 332: Otgfs Usb Configuration Register (Otgfs_Gusbcfg)

    AT32WB415 Series Reference Manual 20.6.3.4 OTGFS USB configuration register (OTGFS_GUSBCFG) This register is used to configure the controller after power-on or a change between host mode and device mode. This register contains USB and USB-PHY related parameters. The application must program the register before handling any transaction on either the AHB or USB.

  • Page 333: Otgfs Reset Register (Otgfs_Grstctl)

    AT32WB415 Series Reference Manual 20.6.3.5 OTGFS reset register (OTGFS_GRSTCTL) The application resets various hardware modules in the controller through this register. Register Reset value Type Description Accesible in both host mode and device modes AHB master Idle Bit 31 AHBIDLE This bit indicates that the AHB master state machine is in idle condition.
  • Page 334 AT32WB415 Series Reference Manual frame number of 0. If the application writes 1 to this bit, it may not be able to read the value, because this bit is cleared after a few clock cycles by the controller Accesible in both host mode and device modes...

  • Page 335: Otgfs Interrupt Register (Otgfs_Gintsts)

    AT32WB415 Series Reference Manual 20.6.3.6 OTGFS interrupt register (OTGFS_GINTSTS) This register interrupts the application due to system-level events in the current mode (device or host mode), as shown in Figure 20-2. Some of the bits in this register are valid only in host mode, while others are valid in device mode only.
  • Page 336 AT32WB415 Series Reference Manual indicate that there is at least one synchronous OUT endpoint with incomplete transfers in the current frame. This interrupt is generated along with the End of Periodic Frame Interrupt interrupt bit in this register. Accesible in device mode only...
  • Page 337 AT32WB415 Series Reference Manual Accesible in device mode only Early suspend Bit 10 ERLYSUSP rw1c The controller sets this bit to indicate that the idle state has been detected on the USB bus for 3 ms. Bit 9: 8 Reserved resd Kept at its default value.

  • Page 338: Otgfs Interrupt Mask Register (Otgfs_Gintmsk)

    AT32WB415 Series Reference Manual Mode mismatch interrupt The controller sets this bit when the application is attempting to access: A host-mode register, when the controller is running in device mode A device-mode register, when the controller is running in host mode...

  • Page 339: Otgfs Receive Status Debug Read/Otg Status Read And Pop Registers (Otgfs_Grxstsr / Otgfs_Grxstsp)

    AT32WB415 Series Reference Manual USB suspend interrupt mask Accesible in device mode only Bit 10 ERLYSUSPMSK Early suspend interrupt mask Bit 9: 8 Reserved resd Kept at its default value. Accesible in device mode only Bit 7 GOUTNAKEFFMSK Global OUT NAK effective mask...

  • Page 340: Otgfs Receive Fifo Size Register (Otgfs_Grxfsiz)

    AT32WB415 Series Reference Manual Device mode: Register Reset value Type Description Bit 31: 25 Reserved 0x00 resd Kept at its defaut value. Frame number Indicates the least significant 4 bits of the frame number of Bit 24: 21 the data packet received on the USB bus. This field is applicable only when the synchronous OUT endpoints are supported.

  • Page 341: Tx Fifo Size Registers (Otgfs_Dieptxf0)

    AT32WB415 Series Reference Manual 20.6.3.10 OTGFS non-periodic Tx FIFO size (OTGFS_GNPTXFSIZ)/Endpoint 0 Tx FIFO size registers (OTGFS_DIEPTXF0) The application can program the SRAM size and start address of the non-periodic transmit FIFO. The fields of this register varies with host mode or device mode.

  • Page 342: Otgfs General Controller Configuration Register (Otgfs_Gccfg)

    AT32WB415 Series Reference Manual 20.6.3.12 OTGFS general controller configuration register (OTGFS_GCCFG) Register Reset value Type Description Bit 31: 22 Reserved 0x000 resd Kept at its default value. VBUS ignored When this bit is set, the OTGFS controller does not monitor...

  • Page 343: (X=1

    AT32WB415 Series Reference Manual 20.6.3.15 OTGFS device IN endpoint Tx FIFO size register (OTGFS_DIEPTXFn) (x=1… 3, where n is the FIFO number) This register holds the depth and memory start address of the IN endpoint transmit FIFO in device mode.

  • Page 344: Otgfs Host Frame Interval Register (Otgfs_Hfir)

    AT32WB415 Series Reference Manual 20.6.4.2 OTGFS host frame interval register (OTGFS_HFIR) This register is used to program the frame interval at current enumeration speed. Register Reset value Type Description Bit 31: 17 Reserved 0x0000 resd Kept at its default value.

  • Page 345: Otgfs Host All Channels Interrupt Register (Otgfs_Haint)

    AT32WB415 Series Reference Manual endpoint) Periodic transmit request queue space available Indicates the number of free space available to be written in the periodic transmit request queue. This queue contains both IN and OUT requests. Bit 23: 16 PTXQSPCAVAIL 0x08...
  • Page 346 AT32WB415 Series Reference Manual the port into test mode, and the port gives a corresponding signal. 0000: Test mode disabled 0001: Test_J mode 0010: Test_K mode 0011: Test_SE0_NAK mode 0100: Test_Packet mode 0101: Test_Force_Enable Others: Reserved Port power The application uses this bit to control power supply to this...

  • Page 347: (X = 0

    AT32WB415 Series Reference Manual Port overcurrent change The controller sets this bit when the status of the port Bit 5 PRTOVRCCHNG rw1c overcurrent active bit (bit 4) in this register changes. This bit can only be set by the controller. The application must write 1 to clear this bit.

  • Page 348: Otgfs Host Channelx Interrupt Register (Otgfs_Hcintx)

    AT32WB415 Series Reference Manual This field must be set to at least 0x01. Endpoint type Indicates the transfer type selected. 00: Control transfer Bit 19: 18 EPTYPE 01: Synchronous transfer 10: Bulk transfer 11: Interrupt transfer Low-speed device Bit 17...

  • Page 349: (X = 0

    AT32WB415 Series Reference Manual must write 1 to clear this bit. Bit 2 Reserved resd Kept at its default value. Channel hated Indicates that the transfer completed abnorammly either Bit 1 CHHLTD rw1c because of any transfer error or in response to a disable request by the applicaton.

  • Page 350: Otgfs Device Control Register (Otgfs_Dctl)

    AT32WB415 Series Reference Manual This register configures the controller in device mode after power-on or after certain control commands or enumeration. Do not change this register after initial programming. Register Reset value Type Description Bit 31: 13 Reserved 0x0110 resd Kept at its default value.

  • Page 351: Otgfs Device Status Register (Otgfs_Dsts)

    AT32WB415 Series Reference Manual Test control 000: Test mode disabled 001: Test_J mode 010: Test_K mode Bit 6: 4 TSTCTL 011: Test_SE0_NAK mode 100: Test_Packet mode 101: Test_Force_Enable； Others: Reserved Global OUT NAK status 0: A handshake is sent based on the FIFO status, NAK and STALL bit settings.

  • Page 352: Otgfs Device Otgfsin Endpoint Common Interrupt Mask Register (Otgfs_Diepmsk)

    AT32WB415 Series Reference Manual connected to the device. Bit 7: 4 Reserved resd Kept at its default value. Erratic error This error causes the controller to enter suspend mode, and interrupt is generated with the early suspend bit of the...

  • Page 353: Otgfs Device Out Endpoint Common Interrupt Mask Register (Otgfs_Doepmsk)

    AT32WB415 Series Reference Manual 20.6.5.5 OTGFS device OUT endpoint common interrupt mask register (OTGFS_DOEPMSK) This register works with each of the OTGFS_DOEPINTx registers for all endpoints to generate an OUT endpoint interrupt. Each of the bits in the OTGFS_DOEPINTx registers can be masked by writing to the register.

  • Page 354: Otgfs Device In Endpoint Fifo Empty Interrupt Mask Register (Otgfs_Diepempmsk)

    AT32WB415 Series Reference Manual 0: Interrupt masked 1: Interrupt unmasked Bit 15: 8 Reserved 0x0000 resd Kept at its defaut value. IN EP interrupt mask bits One IN endpoint per bit. Bit 0 for IN endpoint 0, bit 7 for IN...

  • Page 355: Otgfs Device In Endpoint -X Control Register (Otgfs_Diepctlx)

    AT32WB415 Series Reference Manual 0: The controller is transmitting non-NAK handshakes based on the FIFO status 1: The controller is transmitting NAK handshakes on this endpoint When this bit is set, either by the application or controller, the controller stops transmitting data, even if there are space available in the receive FIFO.
  • Page 356 AT32WB415 Series Reference Manual handshakes on an endpoint. The controller sets this bit on a Transfer completed interrupt or after receiving a SETUP packet. Values: 0: Do not set NAK 1: Set NAK Clear NAK A write to this bit clears the NAK bit for this endpoint.

  • Page 357: Otgfs Device Control Out Endpoint 0 Control Register (Otgfs_Doepctl0)

    AT32WB415 Series Reference Manual through the SETEVNFR and SETODDFR bits in this register. 0: Even frame 1: Odd frame USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The controller clears this bit for...

  • Page 358: Otgfs Device Control Out Endpoint -X Control Register (Otgfs_Doepctlx) (X=1

    AT32WB415 Series Reference Manual – When this bit is set (either by the application or the controller), the controller stops receiving any data on an OUT endpoint, even if there is space in the receive FIFO. The controller always responds to SETUP data packets with an ACK handshake, regardless of whether this bit is set or not.
  • Page 359 AT32WB415 Series Reference Manual handshakes on an endpoint. The controller sets this bit on a Transfer completed interrupt or after receiving a SETUP packet. Values: 0: Do not set NAK 1: Set NAK Clear NAK A write to this bit clears the NAK bit for the endpoint.

  • Page 360: (X=0

    AT32WB415 Series Reference Manual 0: Even frame 1: Odd frame USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The controller clears this bit for all endpoints except for endpoint 0 after detecting a USB...

  • Page 361: (X=0

    AT32WB415 Series Reference Manual 20.6.5.14 OTGFS device OUT endpoint-x interrupt register (OTGFS_DOEPINTx) (x=0… 3, where x if endpoint number) This register indicates the status of an endpoint with repect to USB and AHB-related events, as shown in Figure 20-2. When the OEPINT bit of the OTGFS_GINTSTS register is set, the application must first read the OTGFS_DAINT register to get the exact endpoint number in which the event occurs, before reading the endpoint interrupt registers.

  • Page 362: Otgfs Device Out Endpoint 0 Transfer Size Register (Otgfs_Doeptsiz0)

    AT32WB415 Series Reference Manual 20.6.5.16 OTGFS device OUT endpoint 0 transfer size register (OTGFS_DOEPTSIZ0) The application must set this register before enabling endpoint 0. Once the endpoint 0 is enabled using the endpoint enable pin in the device endpoint 0 control register, the controller modifies this register. The application can only read this register as long as the controller clears the endpoint enable bit.

  • Page 363: Otgfs Device In Endpoint Transmit Fifo Status Register (Otgfs_Dtxfstsx) (X=1

    AT32WB415 Series Reference Manual 20.6.5.18 OTGFS device IN endpoint transmit FIFO status register (OTGFS_DTXFSTSx) (x=1… 3, where x is endpoint number) This is a ready-only register containing the free space information for the device IN endpoint transmit FIFO. Register Reset value...

  • Page 364: Power And Clock Control Registers

    AT32WB415 Series Reference Manual 20.6.6 Power and clock control registers 20.6.6.1 OTGFS power and clock gating control register (OTGFS_PCGCCTL) This register is available in host and device modes. Register Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value.

  • Page 365: Comparator (Comp)

    AT32WB415 Series Reference Manual 21 Comparator (COMP) 21.1 COMP introduction AT32WB415 has two embedded ultra-low-power comparators, COMP1 and COMP2. They can be used for various purposes, such as, external analog signal monitor/control and wakeup from low-power mode, and working with other timers for pulse width measurement and PWM signal control.

  • Page 366: Interrupt Management

    AT32WB415 Series Reference Manual 21.3 Interrupt management Comparator 1 generates an external interrupt or event via EXTI line 19 to wakeup device from low-power mode; Comparator 2 generates an external interrupt or event via EXTI line 20 to wakeup device from low-power mode.

  • Page 367: Cmp Registers

    AT32WB415 Series Reference Manual 21.6 CMP registers These registers must be accessed by words (32 bits). Table 21-1 CMP register map and reset values Register name Offset Reset value CMP_CTRLSTS1 0x00 0x0000 0080 CMP_CTRLSTS2 0x04 0x0001 0001 21.6.1 Comparator control and status register 1 (COMP_CTRLSTS1)
  • Page 368 AT32WB415 Series Reference Manual Comparator 1 write protect 0: Disabled 1: Enabled Bit 15 CMP1WP rw0c Note: The COMP_CTRLSTS1[15:0] and COMP_CTRLSTS2[15:0] bits are write-protected through this bit. This bit is cleared only by system reset. Comparator 1 output value Bit 14...

  • Page 369: Comparator Control/Status Register 2 (Comp_Ctrlsts2)

    AT32WB415 Series Reference Manual 21.6.2 Comparator Control/Status Register 2 (COMP_CTRLSTS2) Register Reset value Type Description Bit 31: 18 Reserved 0x0000 resd Kept at its default value. Comparator2 non-inverting input selection 00: PA7 01: PA3 (default) Bit 17: 16 COMP2NINVSEL 10: PA2 11: Reserved Note: This field is read-only when CMP2WP=1.

  • Page 370: Debug (Debug)

    AT32WB415 Series Reference Manual 22 Debug (DEBUG) 22.1 Debug introduction Cortex™-M4 core provides poweful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with a serial wire debug interface.

  • Page 371: Degub Registers

    AT32WB415 Series Reference Manual Table 22-2 Trace function mode TRACE PB3/JTDO/TR PE2/TRAC PE3/TRAC PE4/TRAC PE5/TRACE PE6/TRAC _MODE[1: 0] ACESWO ED[0] ED[1] D[2] ED[3] Asynchronous TRACES Released (can be used as general-puspose I/Os) trace Synchronous TRAC TRAC Released (can be used as general-...
  • Page 372 AT32WB415 Series Reference Manual Kept at its default value. Bit 16 Reserved resd C1 pause control bit 0: Work normally Bit 15 I2C1_SMBUS_TIMEOUT 0x0 1: I C1 SMBUS timeout control is disabled CAN1 pause control bit 0: CAN1 works normally...
  • Page 373 AT32WB415 Series Reference Manual 23 Revision history Document Revision History Date Version Revision Note Initial release. 2022.04.13 2.00 2022.04.13 Page 373 Ver 2.00...
  • Page 374 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third party’s products or services...

Table of Contents