ARTERY AT32F413 Series Manuals

Manuals and User Guides for ARTERY AT32F413 Series. We have 3 ARTERY AT32F413 Series manuals available for free PDF download: Reference Manual, Application Note

ARTERY AT32F413 Series Reference Manual (369 pages)

ARM-based 32-bit Cortex-M4F MCU+FPU with 64 to 25 KB Flash, sLib, USB, 2 CANs, 12 timers, 3 ADCs, 13 communication interfaces

Brand: ARTERY | Category: Computer Hardware | Size: 5 MB

Table of Contents
2
System Architecture
26
Figure 1-1 AT32F413A Series Microcontrollers System Architecture
26
System Overview
27
ARM Cortex
27
TM -M4F Processor
27
Figure 1-2 Internal Block Diagram of Cortex ® -M4F
27
Bit Band
28
Figure 1-3 Comparison between Bit-Band Region and Its Alias Region: Image a
28
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image B
28
Table 1-1 Bit-Band Address Mapping in SRAM
29
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
29
Interrupt and Exception Vectors
30
Table 1-3 AT32F413 Series Vector Table
30
System Tick (Systick)
33
Reset
33
Figure 1-5 Reset Process
33
Figure 1-6 Example of MSP and PC Initialization
34
List of Abbreviations for Registers
35
Device Characteristics Information
35
Flash Memory Size Register
35
Device Electronic Signature
35
Table 1-4 List of Abbreviations for Registers
35
Table 1-5 List of Abbreviations for Registers
35
Memory Resources
36
Internal Memory Address Map
36
Figure 2-1 AT32F413 Address Mapping
36
Flash Memory
37
SRAM Memory
38
Peripheral Address Map
38
Table 2-1 Peripheral Boundary Address
38
Power Control (PWC)
40
Introduction
40
Main Features
40
Figure 3-1 Block Diagram of each Power Supply
40
Por/Lvr
41
Power Voltage Monitor (PVM)
41
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
41
Figure 3-3 PVM Threshold and Output
41
Power Domain
42
Power Saving Modes
42
PWC Registers
44
Power Control Register (PWC_CTRL)
44
Table 3-1 PW Register Map and Reset Values
44
Power Control/Status Register (PWC_CTRLSTS)
45
Clock and Reset Management (CRM)
46
Clock
46
Clock Sources
46
Figure 4-1 AT32F413 Clock Tree
46
System Clock
47
Peripheral Clock
47
Clock Fail Detector
48
Auto Step-By-Step System Clock Switch
48
Internal Clock Output
48
Interrupts
48
Reset
48
System Reset
48
Battery Powered Domain Reset
49
CRM Registers
49
Figure 4-2 System Reset Circuit
49
Table 4-1 CRM Register Map and Reset Values
49
Clock Control Register (CRM_CTRL)
50
Clock Configuration Register (CRM_CFG)
51
Clock Interrupt Register (CRM_CLKINT)
53
APB2 Peripheral Reset Register (CRM_APB2RST)
54
APB1 Peripheral Reset Register (CRM_APB1RST)
55
APB Peripheral Clock Enable Register (CRM_AHBEN)
56
APB2 Peripheral Clock Enable Register (CRM_AHB2EN)
57
APB1 Peripheral Clock Enable Register (CRM_AHB1EN)
58
Battery Powered Domain Control Register (CRM_BPDC)
59
Control/Status Register (CRM_CTRLSTS)
60
Additional Register1 (CRM_MISC1)
61
Additional Register2 (CRM_MISC2)
61
Additional Register3 (CRM_MISC3)
62
Interrupt Map Register (CRM_INTMAP)
62
Flash Memory Controller (FLASH)
63
Flash Memory Introduction
63
Table 5-1 Flash Memory Architecture(256 K)
63
Table 5-2 Flash Memory Architecture(128 K)
63
Figure 5-1 External Memory Ciphertext Protection
64
Table 5-3 Flash Memory Architecture(64 K)
64
Figure 5-2 Reference Circuit for External Memory
65
Table 5-4 Instruction Set Supported by External Memory
65
Table 5-5 User System Data Area
66
Flash Memory Operation
67
Unlock/Lock
67
Erase Operation
67
Figure 5-3 Flash Memory Page Erase Process
68
Figure 5-4 Flash Memory Mass Erase Process
69
Programming Operation
70
Figure 5-5 Flash Memory Programming Process
70
Read Operation
71
External Memory Operation
71
User System Data Area Operation
71
Unlock/Lock
71
Erase Operation
71
Programming Operation
72
Figure 5-6 System Data Area Erase Process
72
Read Operation
73
Flash Memory Protection
73
Figure 5-7 System Data Area Programming Process
73
Access Protection
74
Erase/Program Protection
74
Table 5-6 Flash Memory Access Limit
74
Special Functions
75
Security Library Settings
75
Flash Memory Registers
76
Flash Performance Select Register (FLASH_PSR)
76
Table 5-7 Flash Memory Interface-Register Map and Reset Value
76
Flash Unlock Register (FLASH_UNLOCK)
77
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
77
Flash Status Register (FLASH_STS)
77
Flash Control Register (FLASH_CTRL)
77
Flash Address Register (FLASH_ADDR)
78
User System Data Register (FLASH_USD)
78
Erase/Program Protection Status Register (FLASH_EPPS)
78
Flash Unlock Register3 (FLASH_UNLOCK3)
79
Flash Select Register (FLASH_SELECT)
79
Flash Status Register3 (FLASH_STS3)
79
Flash Control Register3 (FLASH_CTRL3)
79
Flash Address Register3 (FLASH_ADDR3)
80
Flash Decrption Address Register (FLASH_DA)
80
Flash Security Library Status Register 0 (SLIB_STS0)
80
Flash Security Library Status Register 1 (SLIB_STS1)
81
Flash Security Library Password Clear Register (SLIB_PWD_CLR)
81
Security Library Additional Status Register (SLIB_MISC_STS)
81
Security Library Password Setting Register (SLIB_SET_PWD)
82
Security Library Address Setting Register (SLIB_SET_RANGE)
82
Security Library Unlock Register (SLIB_UNLOCK)
82
Flash CRC Check Control Register (FLASH_CRC_CTRL)
83
Flash CRC Check Result Register (FLASH_CRC_CHKR)
83
General-Purpose I/Os (Gpios)
84
Introduction
84
Function Overview
84
GPIO Structure
84
Figure 6-1 GPIO Basic Structure
84
GPIO Reset Status
85
General-Purpose Input Configuration
85
Analog Input/Output Configuration
85
General-Purpose Output Configuration
85
I/O Port Protection
85
GPIO Registers
86
GPIO Configuration Register Low (Gpiox_Cfglr) (X=A
86
Table 6-1 GPIO Register Map and Reset Values
86
GPIO Configuration Register High (Gpiox_Cfghr) (a
87
GPIO Input Data Register (Gpiox_Idt) (X=A
87
GPIO Output Data Register (Gpiox_Odt) (X=A
87
GPIO Set/Clear Register (Gpiox_Scr) (X=A..f
88
GPIO Clear Register (Gpiox_Clr) (X=A..f
88
GPIO Write Protection Register (Gpiox_Wpr) (X=A..f
88
Multiplexed Function I/Os (IOMUX)
89
Introduction
89
Function Overview
89
IOMUX Structure
89
Figure 7-1 Basic Structure of IOMUX Basic Structure
89
Multiplexed Input Configuration
90
Multiplexed Output or Bidirectional Multiplexed Configuration
90
Peripheral Multiplexed Function Configuration
90
IOMUX Map Priority
90
Table 7-1 IOMUX Input Configuration
90
Table 7-2 IOMUX Output Configuration
90
Hardware Preemption
91
Debug Port Priority
91
Other Peripheral Output Priority
91
External Interrupt/Wake-Up Lines
91
Table 7-3 Hardware Preemption
91
Table 7-4 Debug Port Map
91
IOMUX Registers
92
Event Output Control Register (IOMUX_EVTOUT)
92
Table 7-5 IOMUX Register Map and Reset Value
92
IOMUX Remap Register (IOMUX_REMAP)
93
IOMUX External Interrupt Configuration Register1 (IOMUX_EXINTC1)
95
IOMUX External Interrupt Configuration Register2 (IOMUX_EXINTC2)
96
IOMUX External Interrupt Configuration Register3 (IOMUX_EXINTC3)
96
IOMUX External Interrupt Configuration Register4 (IOMUX_EXINTC4)
97
IOMUX Remap Register2 (IOMUX_REMAP2)
98
IOMUX Remap Register3 (IOMUX_REMAP3)
98
IOMUX Remap Register4 (IOMUX_REMAP4)
98
IOMUX Remap Register5 (IOMUX_REMAP5)
99
IOMUX Remap Register6 (IOMUX_REMAP6)
99
IOMUX Remap Register7 (IOMUX_REMAP7)
100
External Interrupt/Event Controller (EXINT)
102
EXINT Introduction
102
Function Overview and Configuration Procedure
102
Figure 8-1 External Interrupt/Event Controller Block Diagram
102
EXINT Registers
103
Interrupt Enable Register (EXINT_INTEN)
103
Event Enable Register (EXINT_EVTEN)
103
Polarity Configuration Register1 (EXINT_ POLCFG1)
103
Polarity Configuration Register2 (EXINT_ POLCFG2)
103
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
103
Software Trigger Register (EXINT_ SWTRG)
104
Interrupt Status Register (EXINT_ INTSTS)
104
DMA Controller (DMA)
105
Introduction
105
Main Features
105
Figure 9-1 DMA Block Diagram
105
Function Overview
106
DMA Configuration
106
Handshake Mechanism
106
Arbiter
106
Programmable Data Transfer Width
107
Figure 9-2 Re-Arbitrae after Request/Acknowledge
107
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
107
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
107
Errors
108
Interrupts
108
Fixed DMA Request Mapping
108
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
108
Table 9-1 DMA Error Event
108
Table 9-2 DMA Interrupt Requests
108
Table 9-3 DMA1 Requests for each Channel
108
Flexible DMA Request Mapping
109
Table 9-4 DMA2 Requests for each Channel
109
Table 9-5 Flexible DMA Requests for each Channel
109
DMA Registers
110
Table 9-6 DMA Register Map and Reset Value
110
DMA Interrupt Status Register (DMA_STS)
111
DMA Interrupt Flag Clear Register (DMA_CLR)
113
DMA Channelx Configuration Register (Dma_Cxctrl) (X = 1
115
DMA Channelx Number of Data Register (Dma_Cxdtcnt) (X = 1
116
DMA Channelx Peripheral Address Register (Dma_Cxpaddr)
116
DMA Channelx Memory Address Register (Dma_Cxmaddr)
116
Channel Source Register (DMA_SRC_SEL0)
116
Channel Source Register1 (DMA_SRC_SEL1)
117
CRC Calculation Unit (CRC)
118
CRC Introduction
118
CRC Registers
118
Data Register (CRC_DT)
118
Common Data Register (CRC_CDT)
118
Table 10-1 CRC Register Map and Reset Value
118
Control Register (CRC_CTRL)
119
Initialization Register (CRC_IDT)
119
C Interface
120
I 2 C Introduction
120
I 2 C Main Features
120
I 2 C Function Overview
120
Figure 11-1 I2C Bus Protocol
120
I 2 C Interface
121
Figure 11-2 I2C Function Block Diagram
121
C Slave Communication Flow
123
Figure 11-3 Transfer Sequence of Slave Transmitter
123
Figure 11-4 Transfer Sequence of Slave Receiver
124
C Master Communication Flow
125
Figure 11-5 Transfer Sequence of Master Transmitter
125
Figure 11-6 Transfer Sequence of Master Receiver
127
Figure 11-7 Transfer Sequence of Master Receiver When N>2
128
Figure 11-8 Transfer Sequence of Master Receiver When N=2
129
Figure 11-9 Transfer Sequence of Master Receiver When N=1
130
Utilize DMA for Data Transfer
131
Smbus
132
C Interrupt Requests
133
C Debug Mode
134
I 2 C Registers
134
Control Register1 (I2C_CTRL1)
134
Table 11-1 I 2 C Register Map and Reset Value
134
Control Register2 (I2C_CTRL2)
136
Own Address Register1 (I2C_OADDR1)
136
Own Address Register2 (I2C_OADDR2)
137
Data Register (I2C_DT)
137
Status Register1 (I2C_STS1)
137
Status Register2 (I2C_STS2)
139
Clock Control Register (I2C_ CLKCTRL)
140
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
142
USART Introduction
142
Figure 12-1 USART Block Diagram
142
Full-Duplex/Half-Duplex Selector
144
Mode Selector
144
Introduction
144
Configuration Procedure
144
USART Frame Format and Configuration
145
Figure 12-2 Irda DATA(3/16) - Normal Mode
145
Figure 12-3 Word Length
146
Figure 12-4 Stop Bit Configuration
146
DMA Transfer Introduction
147
Transmission Using DMA
147
Reception Using DMA
147
Baud Rate Generation
148
Introduction
148
Configuration
148
Transmitter
148
Transmitter Introduction
148
Transmitter Configuration
149
Receiver
149
Receiver Introduction
149
Figure 12-5 TDC/TDBE Behavior When Transmitting
149
Receiver Configuration
150
Start Bit and Noise Detection
151
Table 12-1 Data Sampling over Start Bit and Noise Detection
151
Table 12-2 Data Sampling over Valid Data and Noise Detection
151
Interrupt Requests
152
I/O Pin Control
152
Figure 12-6 Data Sampling for Noise Detection
152
Figure 12-7 USART Interrupt Map Diagram
152
Table 12-3 USART Interrupt Request
152
USART Registers
153
Status Register (USART_STS)
153
Table 12-4 USART Register Map and Reset Value
153
Data Register (USART_DT)
154
Baud Rate Register (USART_BAUDR)
154
Control Register1 (USART_CTRL1)
154
Control Register2 (USART_CTRL2)
156
Control Register3 (USART_CTRL3)
157
Guard Time and Divider Register (GDIV)
158
Serial Peripheral Interface (SPI)
159
SPI Introduction
159
Function Overview
159
SPI Description
159
Figure 13-1 SPI Block Diagram
159
Full-Duplex/Half-Duplex Selector
160
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
160
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
160
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
161
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
161
Chip Select Controller
162
SPI_SCK Controller
162
Crc
162
DMA Transfer
163
Transmitter
164
Receiver
164
Motorola Mode
165
Figure 13-6 Master Full-Duplex Communications
165
Figure 13-7 Slave Full-Duplex Communications
166
Figure 13-8 Slave Full-Duplex Communications
166
Figure 13-9 Slave Half-Duplex Receive
166
Interrrupts
167
IO Pin Control
167
Figure 13-10 Slave Half-Duplex Transmit
167
Figure 13-11 Master Half-Duplex Receive
167
Figure 13-12 SPI Interrupts
167
Precautions
168
I 2 S Functional Description
168
S Introduction
168
Figure 13-13 I 2 S Block Diagram
168
Operation Mode Selector
169
Figure 13-14 I S Slave Device Transmission
169
Figure 13-15 I 2 S Slave Device Reception
169
Audio Protocol Selector
170
Figure 13-16 I S Master Device Transmission
170
Figure 13-17 I S Master Device Reception
170
I2S_CLK Controller
171
Figure 13-18 CK & MCK Source in Master Mode
172
Table 13-1 Audio Frequency Precision Using System Clock
172
DMA Transfer
174
Transmitter/Receiver
174
I2S Communication Timings
175
Figure 13-19 Audio Standard Timings
175
Interrupts
176
IO Pin Control
176
Figure 13-20 I 2 S Interrupts
176
SPI Registers
177
SPI Control Register1 (SPI_CTRL1)
177
Mode)
177
Table 13-2 SPI Register Map and Reset Value
177
SPI Control Register2 (SPI_CTRL2)
178
SPI Status Register (SPI_STS)
179
SPI Data Register (SPI_DT)
180
SPICRC Register (SPI_CPOLY)
180
Mode)
180
Spirxcrc Register (SPI_RCRC) (Not Used in I2S Mode)
180
Spitxcrc Register (SPI_TCRC)
180
SPI_I2S Register (SPI_I2SCTRL)
180
SPI_I2S Prescaler Register (SPI_I2SCLKP)
181
Timer
182
General-Purpose Timer (TMR2 to TMR5)
182
Tmrx Introduction
182
Table 14-1 TMR Functional Comparison
182
Tmrx Main Features
183
Tmrx Functional Overview
183
Count Clock
183
Figure 14-1 General-Purpose Timer Block Diagram
183
Figure 14-2 Control Circuit with CK_INT Divided by 1
183
Figure 14-3 Block Diagram of External Clock Mode a
184
Figure 14-4 Counting in External Clock Mode a
184
Figure 14-5 Block Diagram of External Clock Mode B
184
Figure 14-6 Counting in External Clock Mode B
184
Counting Mode
185
Figure 14-7 Counter Timing with Prescaler Value Changing from 1 to 4
185
Table 14-2 Tmrx Internal Trigger Connection
185
Figure 14-8 Overflow Event When PRBEN=0
186
Figure 14-9 Overflow Event When PRBEN=1
186
Figure 14-10 Counter Timing Diagram with Internal Clock Divided by 4
186
Figure 14-11 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
186
TMR Input Function
187
Figure 14-12 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
187
Figure 14-13 Input/Output Channel 1 Main Circuit
187
Table 14-3 Couting Direction Versus Encoder Signals
187
TMR Output Function
188
Figure 14-14 Channel 1 Input Stage
188
Figure 14-15 Capture/Compare Channel Output Stage (Channel 1 to 4)
188
Figure 14-16 C1ORAW Toggles When Counter Value Matches the C1DT Value
189
Figure 14-17 Upcounting Mode and PWM Mode a
190
Figure 14-18 Up/Down Counting Mode and PWM Mode a
190
Figure 14-19 One-Pulse Mode
190
TMR Synchronization
191
Figure 14-20 Clearing Cxoraw(PWM Mode A) by EXT Input
191
Figure 14-21 Example of Reset Mode
191
Figure 14-22 Example of Suspend Mode
192
Figure 14-23 Example of Trigger Mode
192
Figure 14-24 Master/Slave Timer Connection
192
Figure 14-25 Using Master Timer to Start Slave Timer
193
Debug Mode
194
Tmrx Registers
194
Figure 14-26 Starting Master and Slave Timers Synchronously by an External Trigger
194
Table 14-4 Tmrx Register Map and Reset Value
194
Control Register1 (Tmrx_Ctrl1)
195
Control Register2 (Tmrx_Ctrl2)
196
Slave Timer Control Register (Tmrx_Stctrl)
196
Dma/Interrupt Enable Register (Tmrx_Iden)
197
Interrupt Status Register (Tmrx_Ists)
198
Software Event Register (Tmrx_Sw EVT)
199
Channel Mode Register1 (Tmrx_Cm1)
200
Channel Mode Register2 (Tmrx_Cm2)
202
Channel Control Register (Tmrx_Cctrl)
203
Table 14-5 Standard Cxout Channel Output Control Bit
203
Counter Value (Tmrx_Cval)
204
Division Value (Tmrx_Div)
204
Period Register (Tmrx_Pr)
204
Channel 1 Data Register (Tmrx_C1Dt)
204
Channel 2 Data Register (Tmrx_C2Dt)
204
Channel 3 Data Register (Tmrx_C3Dt)
205
Channel 4 Data Register (Tmrx_C4Dt)
205
DMA Control Register (Tmrx_Dmactrl)
205
DMA Data Register (Tmrx_Dmadt)
206
General-Purpose Timer (TMR9 to TMR11)
206
Tmrx Introduction
206
Tmrx Main Features
206
TMR9 Main Features
206
TMR10 and TMR11 Main Features
206
Figure 14-27 Block Diagram of General-Purpose TMR9/12
206
Tmrx Functional Overview
207
Count Clock
207
Figure 14-28 Block Diagram of General-Purpose TMR10/11
207
Figure 14-29 Control Circuit with CK_INT Divided by 1
207
Figure 14-30 Block Diagram of External Clock Mode a
207
Counting Mode
208
Figure 14-31 Counting in External Clock Mode a
208
Figure 14-32 Counter Timing with Prescaler Value Changing from 1 to 4
208
Table 14-6 Tmrx Internal Trigger Connection
208
TMR Input Function
209
Figure 14-35 Input/Output Channel 1 Main Circuit
209
Figure 14-36 Channel 1 Input Stage
209
TMR Output Function
210
Figure 14-37 Capture/Compare Channel Output Stage (Channel 1)
210
Figure 14-38 C1ORAW Toggles When Counter Value Matches the C1DT Value
211
Figure 14-39 Upcounting Mode and PWM Mode a
211
Figure 14-40 One-Pulse Mode
211
TMR Synchronization
212
Figure 14-41 Example of Reset Mode
212
Figure 14-42 Example of Suspend Mode
212
Figure 14-43 Example of Trigger Mode
212
Debug Mode
213
TMR9 Registers
213
Control Register1 (TMR9_CTRL1)
213
Table 14-7 Tmrx Register Map and Reset Value
213
Slave Timer Control Register (TMR9_STCTRL)
214
Dma/Interrupt Enable Register (TMR9_IDEN)
214
Interrupt Status Register (TMR9_ISTS)
215
Software Event Register (TMR9_SW EVT)
215
Channel Mode Register1 (TMR9_CM1)
216
Channel Control Register (TMR9_CCTRL)
218
Table 14-8 Standard Cxout Channel Output Control Bit
218
Counter Value (TMR9_CVAL)
219
Division Value (TMR9_DIV)
219
Period Register (TMR9_PR)
219
Channel 1 Data Register (TMR9_C1DT)
219
Channel 2 Data Register (TMR9_C2DT)
219
TMR10 and TMR11 Registers
220
Control Register1 (Tmrx_Ctrl1)
220
Table 14-9 Tmrx Register Map and Reset Value
220
Dma/Interrupt Enable Register (Tmrx_Iden)
221
Interrupt Status Register (Tmrx_Ists)
221
Software Event Register (Tmrx_Sw EVT)
221
Channel Mode Register1 (Tmrx_Cm1)
222
Channel Control Register (Tmrx_Cctrl)
224
Counter Value (Tmrx_Cval)
224
Division Value (Tmrx_Div)
224
Period Register (Tmrx_Pr)
224
Channel 1 Data Register (Tmrx_C1Dt)
224
Table 14-10 Standard Cxout Channel Output Control Bit
224
Advanced-Control Timers (TMR1 and TMR8)
225
TMR1 and TMR8 Introduction
225
TMR1 and TMR8 Main Features
225
TMR1 and TMR8 Functional Overview
225
Count Clock
225
Figure 14-44 Block Diagram of Advanced-Control Timer
225
Figure 14-45 Control Circuit with CK_INT Divided by 1
226
Figure 14-46 Block Diagram of External Clock Mode a
226
Figure 14-47 Counting in External Clock Mode a
226
Figure 14-48 Block Diagram of External Clock Mode B
226
Counting Mode
227
Figure 14-49 Counting in External Clock Mode B
227
Figure 14-50 Counter Timing with Prescaler Value Changing from 1 to 4
227
Table 14-11 Tmrx Internal Trigger Connection
227
Figure 14-33 Overflow Event When PRBEN=0
228
Figure 14-34 Overflow Event When PRBEN=1
228
Figure 14-51 Overflow Event When PRBEN=0
228
Figure 14-52 Overflow Event When PRBEN=1
228
Figure 14-53 Counter Timing Diagram with Internal Clock Divided by 4
228
Figure 14-54 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
228
TMR Input Function
229
Figure 14-55 OVFIF When RPR=2
229
Figure 14-56 Example of Encoder Interface Mode C
229
Table 14-12 Counting Direction Versus Encoder Signals
229
Figure 14-57 Input/Output Channel 1 Main Circuit
230
Figure 14-58 Channel 1 Input Stage
230
TMR Output Function
231
Figure 14-59 Channel Output Stage (Channel 1 to 3)
231
Figure 14-60 Channel 4 Output Stage
231
Figure 14-61 C1ORAW Toggles When Counter Value Matches the C1DT Value
232
Figure 14-62 Upcounting Mode and PWM Mode a
232
Figure 14-63 Up/Down Counting Mode and PWM Mode a
232
Figure 14-64 One-Pulse Mode
233
Figure 14-65 Clearing Cxoraw(PWM Mode A) by EXT Input
233
TMR Break Function
234
Figure 14-66 Complementary Output with Dead-Time Insertion
234
TMR Synchronization
235
Figure 14-67 Example of TMR Break Function
235
Figure 14-68 Example of Reset Mode
235
Debug Mode
236
TMR1 and TMR8 Registers
236
Figure 14-69 Example of Suspend Mode
236
Figure 14-70 Example of Trigger Mode
236
Table 14-13 TMR1 and TMR8 Register Map and Reset Value
236
TMR1 and TMR8 Control Register1 (Tmrx_Ctrl1)
237
TMR1 and TMR8 Control Register2 (Tmrx_Ctrl2)
238
TMR1 and TMR8 Slave Timer Control Register (Tmrx_Stctrl)
239
TMR1 and TMR8 Dma/Interrupt Enable Register (Tmrx_Iden)
240
TMR1 and TMR8 Interrupt Status Register (Tmrx_Ists)
241
Software Event Register (Tmrx_Sw EVT)
242
TMR1 and TMR8 Channel Mode Register1 (Tmrx_Cm1)
243
Channel Mode Register2 (Tmrx_Cm2)
245
Channel Control Register (Tmrx_Cctrl)
246
Table 14-14 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
247
TMR1 and TMR8 Counter Value (Tmrx_Cval)
248
TMR1 and TMR8 Division Value (Tmrx_Div)
248
TMR1 and TMR8 Period Register (Tmrx_Pr)
248
TMR1 and TMR8 Repetition Period Register (Tmrx_Rpr)
248
TMR1 and TMR8 Channel 1 Data Register (Tmrx_C1Dt)
248
TMR1 and TMR8 Channel 2 Data Register (Tmrx_C2Dt)
249
TMR1 and TMR8 Channel 3 Data Register (Tmrx_C3Dt)
249
TMR1 and TMR8 Channel 4 Data Register (Tmrx_C4Dt)
249
TMR1 and TMR8 Break Register (Tmrx_Brk)
249
TMR1 and TMR8 DMA Control Register (Tmrx_ DMACTRL)
251
TMR1 and TMR8 DMA Data Register (Tmrx_ DMADT)
251
Window Watchdog Timer (WWDT)
252
WWDT Introduction
252
WWDT Main Features
252
WWDT Functional Overview
252
Figure 15-1 Window Watchdog Block Diagram
252
Debug Mode
253
WWDT Registers
253
Control Register (WWDT_CTRL)
253
Figure 15-2 Window Watchdog Timing Diagram
253
Table 15-1 Minimum and Maximum Timeout Value When PCLK1=72 Mhz
253
Table 15-2 WWDT Register Map and Reset Value
253
Configuration Register (WWDT_CFG)
254
Status Register (WWDT_STS)
254
Watchdog Timer (WDT)
255
WDT Introduction
255
WDT Main Features
255
WDT Functional Overview
255
Debug Mode
256
WDT Registers
256
Figure 16-1 WDT Block Diagram
256
Table 16-1 WDT Timeout Period (Lick=40Khz)
256
Table 16-2 WDT Register and Reset Value
256
Command Register (WDT_CMD)
257
Divider Register (WDT_DIV)
257
Reload Register (WDT_RLD)
257
Status Register (WDT_STS)
257
Real-Time Clock (RTC)
258
RTC Introduction
258
RTC Main Features
258
RTC Structure
258
RTC Functional Overview
259
Configuring RTC Registers
259
Figure 17-1 Simplified RTC Block Diagram
259
Reading RTC Registers
260
RTC Interrupts
260
Figure 17-2 RTC Second and Alarm Waveform Example with DIV=0004 and TA=00004
260
RTC Registers
261
RTC Control Register High (RTC_CTRLH)
261
Figure 17-3 RTC Overflow Waveform Example with DIV=0004
261
Table 17-1 RTC Register Map and Reset Values
261
RTC Control Register Low (RTC_CTRLL)
262
RTC Divider Register (RTC_ DIVH/RTC_DIVL)
262
RTC Divider Counter Register (RTC_ DIVCNTH/RTC_DIVCNTL)
263
RTC Counter Value Register (RTC_CNTH/RTC_CNTL)
263
RTC Alarm Register (RTC_TAH/RTC_TAL)
263
Battery Powered Registers (BPR)
264
BPR Introduction
264
BPR Main Features
264
BPR Functional Overview
264
BPR Registers
264
Table 18-1 BPR Register Map and Reset Values
264
Battery Powered Data Register X (Bpr_Dtx) (X = 1
265
RTC Calibration Register (BPR_ RTCCAL)
266
BPR Control Register (BPR_ CTRL)
266
BPR Control/Status Register (BPR_ CTRLSTS)
267
Analog-To-Digital Converter (ADC)
268
ADC Introduction
268
ADC Main Features
268
ADC Structure
268
Figure 19-1 ADC1 Block Diagram
269
ADC Functional Overview
270
Channel Management
270
Internal Temperature Sensor
270
Internal Reference Voltage
270
ADC Operation Process
271
Power-On and Calibration
271
Figure 19-2 ADC Basic Operation Process
271
Trigger
272
Figure 19-3 ADC Power-On and Calibration
272
Sampling and Conversion Sequence
273
Conversion Sequence Management
273
Sequence Mode
273
Table 19-1 Trigger Sources for ADC1 and ADC2
273
Automatic Preempted Group Conversion Mode
274
Repetition Mode
274
Figure 19-4 Sequence Mode
274
Figure 19-5 Preempted Group Auto Conversion Mode
274
Partition Mode
275
Figure 19-6 Repetition Mode
275
Figure 19-7 Partition Mode
275
Data Management
276
Data Alignment
276
Data Read
276
Voltage Monitor
276
Status Flag and Interrupts
276
Figure 19-8 Data Alignment
276
Master/Slave Mode
277
Data Management
277
Regular Simultaneous Mode
277
Figure 19-9 Block Diagram of Master/Salve Mode
277
Interleaved Trigger Mode of Preempted Group
278
Figure 19-10 Simultaneous Conversion Mode on Regular Group
278
Figure 19-11 Simultaneous Conversion Mode on Regular Group
278
Figure 19-12 Alternate Preempted Trigger Mode
278
Shift Mode of Regular Group
279
Figure 19-13 Fast Shift Mode on Regular Group
279
ADC Registers
280
Figure 19-14 Slow Shift Mode on Regular Group
280
Table 19-2 ADC Register Map and Reset Values
280
ADC Status Register (ADC_STS)
281
ADC Control Register1 (ADC_CTRL1)
281
ADC Control Register2 (ADC_CTRL2)
283
ADC Sampling Time Register 1 (ADC_SPT1)
285
ADC Sampling Time Register 2 (ADC_SPT2)
286
ADC Preempted Channel Data Offset Register
288
(Adc_Pcdtox) (X=1
288
ADC Voltage Monitor High Threshold Register (ADC_VWHB)
288
ADC Voltage Monitor Low Threshold Register (ADC_VWLB)
288
ADC Ordinary Sequence Register 1 (ADC_OSQ1)
288
ADC Ordinary Sequence Register 2 (ADC_OSQ2)
289
ADC Ordinary Sequence Register 3 (ADC_OSQ3)
289
ADC Preempted Sequence Register (ADC_PSQ)
289
ADC Preempted Data Register X (Adc_Pdtx) (X=1
290
ADC Ordinary Data Register (ADC_ODT)
290
Can
291
CAN Introduction
291
CAN Main Features
291
Baud Rate Configuration
291
Figure 20-1 Bit Timing
291
Figure 20-2 Transmit Interrupt Generation
293
Interrupt Management
294
Figure 20-3 Transmit Interrupt Generation
294
Figure 20-4 Receive Interrupt 0 Generation
294
Figure 20-5 Receive Interrupt 1 Generation
294
Figure 20-6 Status Error Interrupt Generation
294
Design Tips
295
Function Overview
295
General Functional Description
295
Figure 20-7 CAN Block Diagram
295
Operating Modes
296
Test Modes
296
Message Filtering
297
Figure 20-8 32-Bit Identifier Mask Mode
297
Figure 20-9 32-Bit Identifier List Mode
297
Figure 20-10 16-Bit Identifier Mask Mode
298
Figure 20-11 16-Bit Identifier List Mode
298
Message Transmission
299
Figure 20-12 Transmit Mailbox Status
300
Message Reception
301
Figure 20-13 Receive FIFO Status
301
Error Management
302
CAN Registers
302
Table 20-1 CAN Register Map and Reset Values
302
CAN Control and Status Registers
303
CAN Master Control Register (CAN_MCTRL)
303
CAN Master Status Register (CAN_MSTS)
305
CAN Transmit Status Register (CAN_TSTS)
306
CAN Receive FIFO 0 Register (CAN_RF0)
310
CAN Receive FIFO 1 Register (CAN_RF1)
310
CAN Interrupt Enable Register (CAN_INTEN)
311
CAN Error Status Register (CAN_ESTS)
313
CAN Bit Timing Register (CAN_BTMG)
314
CAN Mailbox Registers
314
Figure 20-14 Transmit and Receive Mailboxes
314
Transmit Mailbox Identifier Register (Can_Tmix) (X=0
315
Transmit Mailbox Data Length and Time Stamp Register
315
(Can_Tmcx) (X=0
315
Transmit Mailbox Data Low Register (Can_Tmdtlx) (X=0
316
Transmit Mailbox Data High Register (Can_Tmdthx) (X=0
316
Receive FIFO Mailbox Identifier Register (Can_Rfix) (X=0
316
Receive FIFO Mailbox Data Length and Time Stamp Register
316
(Can_Rfcx) (X=0
316
Receive FIFO Mailbox Data Low Register (Can_Rfdtlx) (X=0
317
Receive FIFO Mailbox Data High Register (Can_Rfdthx) (X=0
317
CAN Filter Registers
317
CAN Filter Control Register (CAN_FCTRL)
317
CAN Filter Mode Configuration Register (CAN_FMCFG)
317
CAN Filter Bit Width Configuration Register (CAN_ FBW CFG)
317
CAN Filter FIFO Association Register (CAN_ FRF)
318
CAN Filter Activation Control Register (CAN_ FACFG)
318
CAN Filter Bank I Filter Bit Register (CAN_ Fifbx
318
Universal Serial Bus Full-Seed Device Interface (USBFS)
319
USBFS Introduction
319
USBFS Clock and Pin Configuration
319
USB Clock Configuration
319
USB Pin Configuration
319
USBFS Functional Description
319
USB Initialization
319
Endpoint Configuration
320
USB Buffer
320
Table 21-1 Buffer Size Configuration Table
320
Double-Buffered Endpoints
321
Figure 21-1 Buffer Description Table of Regular Endpoint Vs. Double-Buffered Endpoint
321
SOF Output
322
Suspend/Resume
322
USB Interrupts
322
USBFS Registers
322
Table 21-2 USBFS Register Map and Reset Values
322
USBFS Endpoint N Register (Usbfs_Eptn), N=[0
323
USBFS Control Register (USBFS_CTRL)
324
USBFS Interrupt Status Register (USBFS_INTSTS)
325
USBFS SOF Frame Number Register (USBFS_SOFRNUM)
326
USBFS Device Address Register (USBFS_DEVADDR)
326
USBFS Buffer Table Address Register (USBFS_BUFTBL)
326
USBFS CFG Control Register (USBFS_CFG)
326
USBFS Transmission Buffer First Address Register (USBFS_ Tnaddr)327
327
USBFS Transmission Data Length Register (Usbfs_Tnlen)
327
USBFS Reception Buffer First Address Register (Usbfs_Rnaddr)
327
USBFS Reception Data Length Register (Usbfs_Rnlen)
327
HICK Auto Clock Calibration (ACC)
328
ACC Introduction
328
Main Features
328
Interrupt Requests
328
Figure 22-1 ACC Interrupt Mapping Diagram
328
Table 22-1 ACC Interrupt Requests
328
Functional Description
329
Principle
330
Figure 22-2 ACC Block Diagram
330
Figure 22-3 Cross-Return Algorithm
330
Register Description
331
Status Register (ACC_STS)
331
Table 22-2 ACC Register Map and Reset Values
331
Control Register 1 (ACC_CTRL1)
332
Control Register 2 (ACC_CTRL2)
333
Compare Value 1 (ACC_C1)
333
Compare Value 2 (ACC_C2)
333
Compare Value 3 (ACC_C3)
333
SDIO Interface
334
SDIO Introduction
334
SDIO Main Features
334
Figure 23-1 SDIO "No Response" and "No Data" Operations
335
Figure 23-2 SDIO Multiple Data Block Read Operation
335
Figure 23-3 SDIO Multiple Data Block Write Operation
335
SDIO Main Features
336
Card Functional Description
336
Card Identification Mode
336
Figure 23-4 SDIO Sequential Read Operation
336
Figure 23-5 SDIO Sequential Write Operation
336
Data Transfer Mode
337
Erase
338
Protection Management
338
Table 23-1 Lock/Unlock Command Structure
339
Commands and Responses
341
Commands
341
Table 23-2 Commands
341
Table 23-3 Data Block Read Commands
342
Table 23-4 Data Stream Read/Write Commands
343
Table 23-5 Data Block Write Commands
343
Table 23-6 Block-Based Write Protect Commands
343
Table 23-7 Erase Commands
344
Table 23-8 I/O Mode Commands
344
Table 23-9 Card Lock Commands
344
Response Formats
345
Table 23-10 Application-Specific Commands
345
Table 23-11 R1 Response
345
Table 23-12 R2 Response
346
Table 23-13 R3 Response
346
Table 23-14 R4 Response
346
Table 23-15 R4B Response
346
SDIO Functional Description
347
Table 23-16 R5 Response
347
Table 23-17 R6 Response
347
SDIO Adapter
348
Figure 23-6 SDIO Block Diagram
348
Table 23-18 SDIO Pin Definitions
348
Table 23-19 Command Formats
349
Table 23-20 Short Response Format
349
Table 23-21 Long Response Format
349
Figure 23-7 Command Channel State Machine (CCSM)
350
Table 23-22 Command Path Status Flags
350
Figure 23-8 SDIO Command Transfer
351
Figure 23-9 Data Channel State Machine (DCSM)
351
Data BUF
352
SDIO AHB Interface
352
Table 23-23 Data Token Formats
352
Hardware Flow Control
353
SDIO I/O Card-Specific Operations
353
SDIO Registers
354
SDIO Power Control Register (SDIO_ PWRCTRL)
354
Table 23-24 a Summary of the SDIO Registers
354
SDIO Clock Control Register (SDIO_ CLKCTRL)
355
SDIO Argument Register (SDIO_ARG)
356
SDIO Command Register (SDIO_CMD)
356
SDIO Command Response Register (SDIO_RSPCMD)
357
SDIO Response 1
357
SDIO Data Timer Register (SDIO_DTTMR)
357

ARTERY AT32F413 Series Application Note (26 pages)

Brand: ARTERY | Category: Microcontrollers | Size: 1 MB

Table of Contents
2
1 Overview

6
- Table 1. at Mcus Printf Function Use Methods
  6
2 Detailed Information

7
3 Notes

24

ARTERY AT32F413 Series Application Note (11 pages)

DM9051 with AT32 MCU

Brand: ARTERY | Category: Computer Hardware | Size: 0 MB

Table of Contents
2
Overview
5
AT32-Based Ethernet Communication
5
Figure 1. AT32 Ethernet Device System Structure
5
How to Use DM9051
6
Hardware Requirements
6
Figure 2. Combined Use of AT-START-F403 and Ethernet Arduino Board
6
Test Ethernet Communication
7
Figure 3. IP Address Printed on Serial Port
7
Figure 4. PC Network Connection Settings
8
Figure 5. Ping Test
8
Figure 6. Web Page Test
9
Revision History
10

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2 Detailed Information

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