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AT32F415CBT7
ARTERY AT32F415CBT7 Manuals
Manuals and User Guides for ARTERY AT32F415CBT7. We have
1
ARTERY AT32F415CBT7 manual available for free PDF download: Reference Manual
ARTERY AT32F415CBT7 Reference Manual (700 pages)
ARM®-based32-bit Cortex®-M4 MCU, with 64 Kbyte ~ 256 Kbyte Internal Flash, sLib, USB-OTG, 11 Timers, 2 COMPs,1 ADC, 12 Communication Interfaces
Brand:
ARTERY
| Category:
Microcontrollers
| Size: 9 MB
Table of Contents
Table of Contents
2
System Architecture
41
System Introduction
41
Figure 1- 1 AT32F415 Series Microcontrollers System Architecture
42
Bus Architecture
43
ARM Cortex -M4 Processer
43
Address Map
44
Figure 1- 2 Internal Block Diagram of Cortex ® -M4
44
Figure 1- 3 AT32F415 Address Configuration
45
Register Map
46
Table 1- 1 Register Boundary Address
46
Bit Banding
47
On-Chip SRAM
48
On-Chip Flash
48
Table 1- 2 256KB Flash Memory Module Organization
48
Table 1- 3 128KB Flash Memory Module Organization
49
Boot Configuration
51
Table 1- 4 64KB Flash Memory Module Organization
51
Table 1- 5 Boot Mode
51
Device Characteristics Information
53
Description of Register Abbreviations
53
Flash Memory Size Register
53
Device Electronic Signature
53
Table 1- 6 List of for Register Abbreviations
53
Power Control (PWR)
55
Introduction
55
Main Features
55
Function Overview
55
Power Supply
55
VDD/VDDA Power Domain
56
Figure 2- 1 Block Diagram of each Power Supply
56
Figure 2- 2 Power-On Reset/Power-Down Reset Waveform
57
Figure 2- 3 PVD Threshold and Outputs
57
Core Power Domain
58
Low-Power Mode
58
Sleep Mode
59
Stop Mode
60
Table 2- 1 SLP-NOW Mode
60
Table 2- 2 SLP-ON-EXIT Mode
60
Standby Mode
61
Table 2- 3 Stop Mode
61
Debug Mode
62
Auto-Wakeup (AWU)
62
Table 2- 4 Standby Mode
62
PWR Registers
63
Power Control Register (PWR_CTRL)
63
Power Control/Status Register (PWR_CTRLSTS)
64
Reset and Clock Control (RCC)
65
Reset
65
System Reset
65
Power Reset
65
Backup Domain Reset
66
Clocks
66
Figure 3- 1 Reset Circuit
66
Figure 3- 2 Clock Tree
67
HSE Clock
68
Figure 3- 3 HSE/LSE Clock Sources
68
HSI Clock
69
Pll
69
LSE Clock
70
LSI Clock
70
System Clock (SYSCLK) Selection
71
Clock Failure Detection (CFD)
71
ERTC Clock
71
Watchdog Clock
71
Clock-Out Capability
72
RCC Registers Description
72
Table 3- 1 RCC Register Map and Reset Values
72
Clock Control Register (RCC_CTRL)
74
Clock Configuration Register (RCC_CFG)
76
Clock Interrupt Register (RCC_CLKINT)
78
APB2 Peripheral Reset Register (RCC_APB2RST)
80
APB1 Peripheral Reset Register (RCC_APB1RST)
81
AHB Peripheral Clock Enable Register (RCC_AHBEN)
84
APB2 Peripheral Clock Enable Register (RCC_APB2EN)
84
APB1 Peripheral Clock Enable Register (RCC_APB1EN)
86
Backup Domain Control Register (RCC_BDC)
88
Control/Status Register (RCC_CTRLSTS)
89
AHB Peripheral Reset Register (RCC_AHBRST)
90
PLL Configuration Register (RCC_PLL)
90
Additional Register (RCC_MISC)
91
OTG_FS Extension Control Register (RCC_OTG_EXTCTRL)
92
Additional Register (RCC_MISC2)
93
Embedded Flash Controller (EFC)
94
EFC Introduction
94
Main Features
94
Flash Memory Architecture
94
Table 4- 1 256 KB Flash Memory Architecture
94
Table 4- 2 128 KB Flash Memory Architecture
95
Table 4- 3 64 KB Flash Memory Architecture
96
Function Overview
97
Read Operation
97
Instruction Fetch
97
D-Code Interface
98
Flash Access Controller
98
Flash Program/Erase Controller (FPEC)
98
Key Value
98
Unlock the Flash Memory
98
Main Flash Programming
98
Flash Erase
99
Figure 4- 1 Process of the Programming
99
Figure 4- 2 Process of Flash Memory
100
Option Byte Programming
101
Figure 4- 3 Process of Flash Memory Mass Erase
101
Protection
102
Write Protection
102
Read Protection
102
Table 4- 4 Flash Memory Protection Status
102
Table 4- 5 Read Protection Level Switch Description
103
Figure 4- 4 Read Protection Level Switch Status Diagram
103
Option Byte Block Write Protection
104
Option Byte Description
104
Table 4- 6 Option Byte Format
104
Table 4- 7 Information Block Organization
104
Table 4- 8 User Option Byte Description
104
Special Functions
105
Security Library Setting
105
System Memory for Main Memory Extension Purpose
106
CRC Calibration
107
EFC Registers
108
Table 4- 9 Flash Memory Interface-Register Map and Reset Values
108
Flash Access Control Register (FLASH_ACR)
109
FPEC Key Register (FLASH_FCKEY)
110
Flash OPTKEY Register (FLASH_OPTKEYR)
110
Flash Status Register (FLASH
111
Flash Control Register (FLASH_CTRL)
112
Flash Address Register (FLASH_ADDR)
113
Option Byte Register (FLASH_UOB)
113
Write Protection Register (FLASH_WRPRT)
114
Flash Slib Status Register 0 (FLASH_CDR0)
114
Flash Slib Status Register 1 (FLASH_CDR1)
115
Flash Slib Password Register (FSLI B_PSW )
117
Flash Slib Password Setting Status Register (FLASH_PSW
117
Flash CRC Verify Start Position (FLASH_CRC_AR)
118
Flash CRC Verify Control Register (FLASH_CRC_CTRL)
118
Flash CRC Verify Result Register (FLASH_CRC_OUTR)
119
Flash Slib Password Setting Register (FLASH_SET_PSW )
119
Flash Slib Rang Setting Register (FLASH_SET_RANGE)
119
Main Memory Extension Area Slib Setting Register
120
Flash Memory Extension Area Mode Register
120
Flash Slib Key Register (FSLIB_KEYR)
121
CRC Calculation Unit (CRC)
122
CRC Introduction
122
CRC Main Features
122
Figure 5- 1 Block Diagram of CRC Calculation Unit
122
CRC Function Overview
123
CRC Registers
124
Data Register (CRC_DR)
124
Independent Data Register (CRC_IDR)
124
Table 5- 1 CRC Calculation Unit Register Map
124
Control Register (CRC_CTRL)
125
CRC Initial Value (CRC_INIT)
126
General-Purpose and Alternate-Function I/Os (Gpios and Afios)
127
Introduction
127
Main Features
127
Function Overview
127
GPIO Pin Configuration
127
Figure 6- 1 Basic Structure of an I/O Port Bit
128
Figure 6- 2 Basic Structure of a 5-V Tolerant I/O Port Bit
128
External Interrupt/Wakeup Lines
129
Input Configuration
129
Table 6- 1 Port Bit Assignment
129
Table 6- 2 Output Mode Bit
129
Analog Input Configuration
130
Figure 6- 3 Input Floating/Pull-Up/Pull-Down Configuration
130
Output Configuration
131
Figure 6- 4 High Impedance Analog Input Configuration
131
GPIO Locking Mechanism
132
Alternate Function (AF)
132
Figure 6- 5 Output Configuration
132
Figure 6- 6 Alternate Function Configuration
133
Table 6- 3 Advanced Timers TMR1/8/15
134
Table 6- 4 General-Purpose Timer TMR2-5/TMR9-14
134
Table 6- 5 USART
134
Table 6- 6 SPI
134
Table 6- 7 I2S
135
Table 6- 8 I2C Interface
135
Table 6- 9 Bxcan
135
Table 6- 10 USBOTG
135
Table 6- 11 SDIO
135
Table 6- 12 ADC/DAC
135
IO Mapping Function Configuration
136
OSC32_IN/OSC32_OUT as GPIO Interface PC14/PC15
136
OSC_IN/OSC_OUT Pin as GPIO Interface PD0/PD1
136
CAN Alternate Function Remapping
136
JTAG/SWD Alternate Function Remapping
136
Table 6- 13 Other I/O Functions
136
Table 6- 14 CA1 Alternate Function Remapping
136
Table 6- 15 Debug Interface Signal
136
ADC Alternate Function Remapping
137
Table 6- 16 Debug Port Mapping
137
Table 6- 17 ADC1 External Trigger Injected Conversion Alternate Function Remapping
137
Table 6- 18 ADC1 External Trigger Regular Conversion Alternate Function Remapping
137
Timer Alternate Function Remapping
138
Table 6- 19 TMR11 Alternate Function Remapping
138
Table 6- 20 TMR10 Alternate Function Remapping
138
Table 6- 21 TMR9 Alternate Function Remapping
138
Table 6- 22 TMR5 Alternate Function Remapping
138
Table 6- 23 TMR3 Alternate Function Remapping
138
Table 6- 24 TMR2 Alternate Function Remapping
138
USART Alternate Function Remapping
139
Table 6- 25 TMR1 Alternate Function Remapping
139
Table 6- 26 USART4 Remapping
139
Table 6- 27 USART3 Remapping
139
Table 6- 28 USART1 Remapping
139
C Alternate Function Remapping
140
SPI1/I2S1 Alternate Function Remapping
140
SDIO Alternate Function Remapping
140
Table 6- 29 I2C1 Remapping
140
Table 6- 30 I2C2 Remapping
140
Table 6- 31 SPI1/I2S1 Remapping
140
Table 6- 32 SPI1/I2S12 Remapping
140
Table 6- 33 SDIO DX Alternate Function Remapping
140
COMP Alternate Function Remapping
141
GPIO and AFIO Registers
141
Table 6- 34 COMP Alternate Function Remapping
141
Table 6- 35 GPIO Register Map and Reset Values
141
Table 6- 36 AFIO Register Map and Reset Values
142
Port Configuration Register Low (Gpiox_Ctrll) (X = a
143
Port Configuration Register High (Gpiox_Ctrlh) (a
144
Port Input Data Register (Gpiox_Iptdt) (X = a
145
Port Output Data Register (Gpiox_Optdt) (X = a
145
Port Bit Set/Reset Register (Gpiox_Bsre) (X = a
145
Port Bit Reset Register (Iox_Bre) (X = a
146
Port Configuration Lock Register (Gpiox_Lock) (X = a
146
Alternate Event Control Register (AFIO_EVCTRL)
147
AF Remap and Debug I/O Configuration Register (AFIO_MAP)
147
Alternate External Interrupt Configuration Register 1 (AFIO_EXTIC1)
149
Alternate External Interrupt Configuration Register 2 (AFIO_EXTIC2)
150
Alternate External Interrupt Configuration Register 3 (AFIO_EXTIC3)
151
Alternate External Interrupt Configuration Register 4 (AFIO_EXTIC4)
151
AF Remap and Debug I/O Configuration Register 2 (AFIO_MAP2)
151
AF Remap and Debug I/O Configuration Register 3 (AFIO_MAP3)
152
AF Remap and Debug I/O Configuration Register 4 (AFIO_MAP4)
153
AF Remap and Debug I/O Configuration Register 5 (AFIO_MAP5)
154
AF Remap and Debug I/O Configuration Register 6 (AFIO_MAP6)
155
AF Remap and Debug I/O Configuration Register 7 (AFIO_MAP7)
155
AF Remap and Debug I/O Configuration Register 8 (AFIO_MAP8 )
157
Interrupts and Events
158
Nested Vectored Interrupt Controller
158
System Tick (Systick) Calibration Value Register
158
Interrupt and Exception Vectors
158
Table 7- 1 Vector Table of AT32F415 Series
158
External Interrupt/Event Controller (EXTI)
161
Main Features
161
Block Diagram
161
Wakeup Event Management
161
Figure 7- 1 External Interrupt/Event Controller Block Diagram
161
Function Overview
162
External Interrupt/Event Line Mapping
162
Figure 7- 2 External Interrupt GPIO Mapping
163
EXTI Registers Description
164
Interrupt Mask Register (EXTI_INTEN)
164
Table 7- 2 External Interrupt/Event Controller Map and Reset Values
164
Event Mask Register (EXTI_EVTEN)
165
Rising Edge Trigger Selection Register (EXTI_RTRSEL)
165
Falling Edge Trigger Selection Registe R (EXTI_FTRSEL)
165
Software Interrupt Event Register (EXTI_SW IE)
166
Pending Register (EXTI_PND)
166
DMA Controller (DMA)
167
DMA Introduction
167
DMA Main Features
167
Function Overview
168
DMA Transaction
168
Figure 8- 1 DMA Block Diagram
168
Arbiter
169
DMA Channels
169
Programmable Data Transfer Width, Alignment, and Endian
170
Table 8- 1Programmable Data Transfer Width and Endian Behavior (When PINC = MINC = 1)
170
Error Management
171
Interrupts
172
Fixed DMA Request Mapping
172
Table 8- 2 DMA Interrupt Request
172
Figure 8- 2 DMA1 Request Mapping
173
Table 8- 3 Summary of DMA1 Requests for each Channel
174
Flexible DMA Request Mapping
175
Table 8- 4 Summary of DMA2 Requests for each Channel
175
Figure 8- 3 DMA2 Request Mapping
175
Table 8- 5 Summary of Flexible DMA Request for each Channel
176
DMA Registers
177
Table 8- 6 DMA Register Map and Reset Values
177
DMA Interrupt Status Register (DMA_ISTS)
179
DMA Interrupt Flag Clear Register (DMA_ICLR)
180
DMA Channel X Configuration Register (Dma_Chctrlx) (X = 1
180
DMA Channel X Number of Data Register (Dma_Tcntx) (X = 1
182
DMA Channel X Peripheral Address Register (Dma_Cpbax) (X = 1
182
DMA Channel X Memory Address Register (Dma_Cmbax) (X = 1
183
DMA Source Register0 (DMA_SRC_SEL0)
184
DMA Source Register1 (DMA_SRC_SEL1)
184
Timer
185
General-Purpose Basic Timer (TMR2 to TMR5)
185
Tmrx Introduction
185
Tmrx Main Features
185
Tmrx Function Overview
186
Time-Base Unit
186
Figure 9- 1 General-Purpose Timer Block Diagram
186
Figure 9- 2 Counter Timing Diagram with Prescaler Division Changing from 1 to 2
187
Figure 9- 3 Counter Timing Diagram with Prescaler Division Changing from 1 to 4
187
Counting Mode
188
Figure 9- 4 Counter Timing Diagram with Internal Clock Divided by 1
188
Figure 9- 5 Counter Timing Diagram with Internal Clock Divided by 2
188
Figure 9- 7 Counter Timing Diagram with Internal Clock Divided by N
189
Figure 9- 8 Counter Timing Diagram with Update Event When ARPEN = 0 (Tmrx_Ar Not Preloaded)
189
Figure 9- 9 Counter Timing Diagram with Update Event When ARPEN = 1 (Tmrx_Ar Is Preloaded)
190
Figure 9- 10 Counter Timing Diagram with Internal Clock Divided by 1
191
Figure 9- 11 Counter Timing Diagram with Internal Clock Divided by 2
191
Figure 9- 12 Counter Timing Diagram with Internal Clock Divided by 4
191
Figure 9- 13 Counter Timing Diagram with Internal Clock Divided by N
192
Figure 9- 14 Counter Timing Diagram with Update Event When ARPEN = 0
192
Figure 9- 15 Counter Timing Diagram with Internal Clock Divided by 1, Tmrx_Ar = 0X6
193
Figure 9- 16 Counter Timing Diagram with Internal Clock Divided by 2
193
Figure 9- 17 Counter Timing Diagram with Internal Clock Divided by 4, Tmrx_Ar = 0X36
194
Figure 9- 18 Counter Timing Diagram with Internal Clock Divided by N
194
Figure 9- 19 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter Underflow)
194
Clock Selection
195
Figure 9- 20 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter Overflow)
195
Figure 9- 21 Normal Mode Timing Diagram with Internal Clock Divided by 1
195
Figure 9- 22 TI2 External Clock Connection Example
196
Figure 9- 23 Control Circuit in External Clock Mode 1
196
Capture/Compare Channel
197
Figure 9- 24 Block Diagram of External Trigger Input
197
Figure 9- 25 Control Circuit in External Clock Mode 2
197
Figure 9- 26 Capture/Compare Channel (E.g. Channel 1 Input Stage)
198
Figure 9- 27 Capture/Compare Channel 1 Main Circuit
198
Input Capture Mode
199
PWM Input Mode
200
Figure 9- 29 PWM Input Mode Timing
200
Forced Output Mode
201
Output Compare Mode
201
Figure 9- 30 Output Compare Mode, Toggle on OC1
202
PWM Mode
203
Figure 9- 31 Edge-Aligned PWM Waveforms (AR = 8)
203
Figure 9- 32 Center-Aligned PWM Waveforms (AP = 8)
204
One-Pulse Mode
205
Figure 9- 33 Example of One-Pulse Mode
205
Clearing Ocxref Signal on an External Event
206
Figure 9- 34 Clearing Ocxref in Tmrx
206
Encoder Interface Mode
207
Table 9- 1 Counting Direction and Encoder Signals
207
Timer Input XOR Function
208
Timer and External Trigger Synchronization
208
Figure 9- 35 Example of Counter Operation in Encoder Interface Mode
208
Figure 9- 36 Example of Encoder Interface Mode with IC1FP1 Polarity Inverted
208
Figure 9- 37 Control Circuit in Reset Mode
209
Figure 9- 38 Control Circuit in Gated Mode
210
Figure 9- 39 Control Circuit in Trigger Mode
210
Timer Synchronization
211
Figure 9- 40 Control Circuit in External Clock Mode 2 + Trigger Mode
211
Figure 9- 41 Master/Slave Timer Example
211
Figure 9- 42 Timer 1 OC1REF Controls Timer 2
212
Figure 9- 43 Control Timer 2 by Enabling Timer 1
213
Figure 9- 44 Using Timer 1 Update to Trigger Timer 2
214
Figure 9- 45 Using Timer 1 Enable to Trigger Timer 2
214
Debug Mode
215
Figure 9- 46 Using Timer 1 TI1 Input to Trigger Timer 1 and Timer 2
215
Tmrx Registers
216
Table 9- 2 Tmrx-Register Table and Reset Values
216
Control Register 1 (Tmrx_Ctrl1)
217
Control Register 2 (Tmrx_Ctrl2)
219
Slave Mode Control Register (Tmrx_Smc)
219
Dma/Interrupt Enable Register (Tmrx_Die)
221
Table 9- 3 Tmrx Internal Trigger Connection
221
Status Register (Tmrx_Sts)
222
Event Generation Register (Tmrx_Eveg)
223
Capture/Compare Mode Register 1 (Tmrx_Ccm1)
224
Capture/Compare Mode Register 2 (Tmrx_Ccm2)
226
Capture/Compare Enable Register (Tmrx_Cce)
228
Counter (Tmrx_Cnt)
229
Prescaler (Tmrx_Div)
229
Table 9- 4 Standard Ocx Channel Output Control Bit
229
Auto-Reload Register (Tmrx_Ar)
230
Capture/Compare Register 1 (Tmrx_Cc1)
230
Capture/Compare Register 2 (Tmrx_Cc2)
231
Capture/Compare Register 3 (Tmrx_Cc3)
231
Capture/Compare Register 4 (Tmrx_Cc4)
232
DMA Control Register (Tmrx_Dmac)
232
DMA Address in Burst Mode (Tmrx_Dmaba)
233
General-Purpose Timer (TMR9 to TMR11)
233
Tmrx Introduction
233
Tmrx Main Function
233
TMR9 Main Function
233
TMR10 and TMR11 Main Function
234
Figure 9- 47 General-Purpose TMR9/12 Block Diagram
234
Figure 9- 48 Block Diagram of General-Purpose Timers TMR10/11
235
Tmrx Function Overview
236
Time-Base Unit
236
Figure 9- 49 Counter Timing Diagram with Prescaler Division Changing from 1 to 2
236
Counter Mode
237
Figure 9- 50 Counter Timing Diagram with Prescaler Division Changing from 1 to 4
237
Figure 9- 51 Counter Timing Diagram with Internal Clock Divided by 1
237
Figure 9- 52 Counter Timing Diagram with Internal Clock Divided by 2
238
Figure 9- 53 Counter Timing Diagram with Internal Clock Divided by 4
238
Figure 9- 54 Counter Timing Diagram with Internal Clock Divided by N
238
Clock Selection
239
Figure 9- 55 Counter Timing Diagram with Update Event When ARPEN = 0 (Tmrx_Ar Not Preloaded)
239
Figure 9- 56 Counter Timing Diagram with Update Event When ARPEN = 1 (Tmrx_Ar Is Preloaded)
239
Figure 9- 57 Control Circuit in Normal Mode with Internal Clock Divided by 1
240
Figure 9- 58 TI2 External Clock Connection Example
240
Capture/Compare Channel
241
Figure 9- 59 Control Circuit in External Clock Mode 1
241
Figure 9- 60 Capture/Compare Channel (E.g. Channel 1 Input Stage)
241
Input Capture Mode
242
Figure 9- 62 Capture/Compare Channel Output Stage (Channel 1)
242
PWM Input Mode (Only TMR9)
243
Forced Output Mode
244
Output Compare Mode
244
Figure 9- 63 PWM Input Mode Timing
244
PWM Mode
245
Figure 9- 64 Output Compare Mode, Toggle on OC1
245
One-Pulse Mode
246
Figure 9- 65 Edge-Aligned PWM Waveforms (AR = 8)
246
Figure 9- 66 Example of One-Pulse Mode
246
Timer and External Trigger Synchronization (TMR9 Only)
247
Figure 9- 67 Control Circuit in Reset Mode
248
Figure 9- 68 Control Circuit in Gated Mode
248
Timer Synchronization (TMR9 Only)
249
Debug Mode
249
TMR9 Register Description
249
Table 9- 5 Tmrx - Register Table and Reset Values
249
Figure 9- 69 Control Circuit in Trigger Mode
249
Control Register 1 (Tmrx_Ctrl1)
251
Slave Mode Control Register (Tmrx_Smc)
252
Table 9- 6 Tmrx Internal Trigger Connection
252
Dma/Interrupt Enable Register (Tmrx_Die)
253
Status Register (Tmrx_Sts)
254
Event Generation Register (Tmrx_Eveg)
255
Capture/Compare Mode Register 1 (Tmrx_Ccm1)
256
Capture/Compare Enable Register (Tmrx_Cce)
259
Table 9- 7 Standard Ocx Channel Output Control Bit
259
Counter (Tmrx_Cnt)
260
Prescaler (Tmrx_Div)
260
Auto-Reload Register (Tmrx_Ar)
260
Capture/Compare Register 1 (Tmrx_ CC1)
261
Capture/Compare Register 2 (Tmrx_Cc2)
261
TMR10 and TMR11 Registers Description
261
Table 9- 8 Tmrx -Register Table and Reset Values
261
Control Register 1 (Tmrx_Ctrl1)
262
Dma/Interrupt Enable Register (Tmrx_Die)
263
Status Register (Tmrx_Sts)
263
Event Generation Register (Tmrx_Eveg)
265
Capture/Compare Mode Register 1 (Tmrx_C CM1)
265
Capture/Compare Enable Register (Tmrx_Cce)
267
Counter (Tmrx_Cnt)
268
Prescaler (Tmrx_Div)
268
Auto-Reload Register (Tmrx_Ar)
268
Table 9- 9 Standard Ocx Channel Output Control Bit
268
Capture/Compare Register 1 (Tmrx_Cc1)
269
Advanced-Control Timer (TMR1)
270
TMR1 Introduction
270
TMR1 Main Features
270
TMR1 Function Overview
271
Time-Base Unit
271
Figure 9- 70 Block Diagram of Advanced-Control Timer
271
Figure 9- 71 Counter Timing Diagram with Prescaler Division Changing from 1 to 2
272
Figure 9- 72 Counter Timing Diagram with Prescaler Division Changing from 1 to 4
272
Counter Mode
273
Figure 9- 73 Counter Timing Diagram with Internal Clock Divided by 1
273
Figure 9- 74 Counter Timing Diagram with Internal Clock Divided by 2
274
Figure 9- 75 Counter Timing Diagram with Internal Clock Divided by 4
274
Figure 9- 76 Counter Timing Diagram with Internal Clock Divided by N
274
Figure 9- 77 Counter Timing Diagram with Update Event When ARPEN = 0 (Tmrx_Ar Not Preloaded)
275
Figure 9- 78 Counter Timing Diagram with Update Event When ARPEN = 1 (Tmrx_Ar Is Preloaded)
275
Figure 9- 79 Counter Timing Diagram with Internal Clock Divided by 1
276
Figure 9- 80 Counter Timing Diagram with Internal Clock Divided by 2
276
Figure 9- 81 Counter Timing Diagram with Internal Clock Divided by 4
277
Figure 9- 82 Counter Timing Diagram with Internal Clock Divided by N
277
Figure 9- 83 Counter Timing Diagram of Update Event Without Auto-Reload
277
Figure 9- 84 Counter Timing Diagram with Internal Clock Divided by 1, Tmrx_Ar = 0X6
278
Figure 9- 6 Counter Timing Diagram with Internal Clock Divided by 4
279
Figure 9- 85 Counter Timing Diagram with Internal Clock Divided by 2
279
Figure 9- 86 Counter Timing Diagram with Internal Clock Divided by 4, Tmrx_Ar = 0X36
279
Figure 9- 87 Counter Timing Diagram with Internal Clock Divided by N
279
Figure 9- 88 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter Underflow)
280
Figure 9- 89 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter Overflow)
280
Repetition Counter
281
Figure 9- 90 Examples of Updating Rates in Different Modes and the Tmrx_Rc Register Configuration
281
Clock Selection
282
Figure 9- 91 Control Circuit in Normal Mode with Internal Clock Divided by 1
282
Figure 9- 92 TI2 External Clock Connection Example
282
Figure 9- 93 Control Circuit in External Clock Mode 1
283
Figure 9- 94 Block Diagram of External Trigger Input
283
Capture/Compare Channel
284
Figure 9- 95 Control Circuit in External Clock Mode 2
284
Figure 9- 96 Capture/Compare Channel (E.g. Channel 1 Input Stage)
284
Figure 9- 61 Capture/Compare Channel 1 Main Circuit
285
Figure 9- 97 Capture/Compare Channel 1 Main Circuit
285
Figure 9- 98 Capture/Compare Channel Output Stage (Channel 1 to 3)
285
Input Capture Mode
286
Figure 9- 99 Capture/Compare Channel Output Stage (Channel 4)
286
PWM Input Mode
287
Figure 9- 100 PWM Input Mode Timing
287
Forced Output Mode
288
Output Compare Mode
289
Figure 9- 101 Output Compare Mode, Toggle on OC1
289
PWM Mode
290
Figure 9- 102 Edge-Aligned PWM Waveforms (AR = 8)
290
Figure 9- 103 Center-Aligned PWM Waveforms (APR = 8)
291
Complementary Output and Dead-Time Insertion
292
Figure 9- 104 Complementary Output with Dead-Time Insertion
292
Figure 9- 105 Dead-Time Waveform Delay Which Is Greater than Negative Pulse
292
Using the Break Function
293
Figure 9- 106 Dead-Time Waveform Delay Which Is Greater than Positive Pulse
293
Clearing Ocxref Signal on an External Event
295
Figure 9- 107 Outputs in Response to a Break
295
6-Step PWM Output Generation
296
Figure 9- 108 Clearing Ocxref in Tmrx
296
One-Pulse Mode
297
Figure 9- 109 6-Step PWM Generation, Example of Using HALL (OSIMR = 1)
297
Figure 9- 110 One-Pulse Mode Example
298
Encoder Interface Mode
299
Table 9- 10 Counting Direction and Encoder Signals
299
Timer Input XOR Function
300
Figure 9- 111 Example of Counter Operation in Encoder Interface Mode
300
Figure 9- 112 Example of Encoder Interface Mode with IC1FP1 Polarity Inverted
300
Interfacing with Hall Sensors
301
Tmrx Timer and External Trigger Synchronization
302
Figure 9- 113 Example of HALL Sensor Interface
302
Figure 9- 114 Control Circuit in Reset Mode
303
Figure 9- 115 Control Circuit in Gated Mode
304
Figure 9- 116 Control Circuit in Trigger Mode
304
Timer Synchronization
305
Debug Mode
305
Figure 9- 117 Control Circuit in External Clock Mode 2 + Trigger Mode
305
TMR1 Register Description
306
Table 9- 11 TMR1, TMR8, and TMR15 -Register Table and Reset Values
306
TMR1 Control Register 1 (Tmrx_Ctrl1)
307
TMR1 Control Register 2 (Tmrx_Ctrl2)
309
TMR1 Slave Mode Control Register (Tmrx_Smc)
310
TMR1 Dma/Interrupt Enable Register (Tmrx_Die)
311
Table 9- 12 Tmrx Internal Trigger Connection
311
TMR1 Status Register (Tmrx_Sts)
312
TMR1 Event Generation Register (Tmrx_Eveg)
315
TMR1 Capture/Compare Mode Register 1 (Tmrx_Ccm1)
315
TMR1 Capture/Compare Mode Register 2 (Tmrx_Ccm2)
318
TMR1 Capture/Compare Enable Register (Tmrx_Cce)
319
Table 9- 13 Complementary Output Channel Ocx and Ocxn Control Bits with Break Function
321
TMR1 Counter (Tmrx_Cnt)
322
TMR1 Prescaler (Tmrx_Div)
322
TMR1 Auto-Reload Register (Tmrx_Ar)
322
TMR1 Repetition Counter Register (Tmrx_Rc)
323
TMR1 Capture/Compare Register 1 (Tmrx_Cc1)
323
TMR1 Capture/Compare Register 2 (Tmrx_Cc2)
323
TMR1 Capture/Compare Register 3 (Tmrx_Cc3)
324
TMR1 Capture/Compare Register 4 (Tmrx_Cc4)
324
TMR1 Break and Dead-Time Register (Tmrx_Brkdt)
325
TMR1 DMA Control Register (Tmrx_Dmac)
326
TMR1 DMA Address in Burst Mode (Tmrx_Dmaba)
327
Watchdog
328
Window Watchdog (WWDG)
328
WWDG Introduction
328
WWDG Main Features
328
WWDG Function Overview
328
Figure 10- 1 Watchdog Block Diagram
328
How to Program Watchdog Timeout
330
Debug Mode
330
Figure 10- 2 Window Watchdog Timing Diagram
330
Register Description
331
Control Register (WWDG_CTRL)
331
Configuration Register (WWDG_CFG)
331
Table 10- 1 WWDG Register Map and Reset Values
331
Status Register (WWDG_STS)
332
Independent Watchdog (IWDG)
333
Introduction
333
IWDG Main Features
333
IWDG Function Overview
333
Hardware Watchdog
333
Register Access Protection
333
Debug Mode
333
Figure 10- 3 Block Diagram of Independent Watchdog
333
IWDG Register Description
334
Table 10- 2 Watchdog Timeout Period (40 Khz Input Clock (LSI))
334
Key Register (IWDG_KEY)
335
Prescaler Register (IWDG_PR)
335
Reload Register (IWDG_RLD)
336
Status Register (IWDG_STS)
337
Real-Time Clock (ERTC)
338
Introduction
338
ERTC Main Features
338
ERTC Function Overview
339
Clock and Prescaler
339
Figure 11- 1 ERTC Diagram
339
Real-Time Clock and Calendar
340
Programmable Clock
340
Periodic Auto-Wakeup
341
ERTC Initialization and Configuration
341
Read the Calendar
343
Reset ERTC
344
ERTC Synchronization
344
ERTC Reference Clock Detection
344
ERTC Coarse Digital Calibration
345
ERTC Fine Digital Calibration
346
Time Stamp Function
347
Tamper Detection
348
Calibration Clock Output
349
Alarm Clock Output
349
ERTC and Low-Power Mode
349
Table 11- 1 ERTC and Low-Power Mode
349
ERTC Interrupt
350
Table 11- 2 Interrupt Control Bit
350
ERTC Register
351
ERTC Time Register (ERTC_TIME)
351
ERTC Date Register (ERTC_DATE)
352
ERTC Control Register (ERTC_CTRL)
352
ERTC Initialization and Status Register (ERTC_STS)
354
ERTC Prescaler Register (ERTC_PSC)
355
ERTC Wakeup Timer Register (ERTC_WATR)
356
ERTC Calibration Register (ERTC_CAL)
356
ERTC Alarm Clock a Register (ERTC_ALA)
357
ERTC Alarm Clock B Register (ERTC_ALB)
358
ERTC W Rite Protect Register (EERTC_W PR)
358
ERTC Sub-Second Register (ERTC_SBSR)
359
ERTC Shift Control Register (ERTC_SFCTR)
359
ERTC Time Stamp Time Register (ERTC_TSTM)
360
ERTC Time Stamp Date Register (ERTC_TSDT)
360
ERTC Time Stamp Sub-Second Register (ERTC_TSSBS)
361
ERTC Calibration Register (ERTC_CCR)
361
ERTC Tamper and Alternate Function Configuration Register (ERTC_TPAF)
362
ERTC Alarm Clock a Sub-Second Register (ERTC_ALASBS)
363
ERTC Alarm Clock B Sub-Second Register (ERTC_ALBSBS)
363
ERTC Backup Register (Ertc_Bkpxdt)
364
Analog-To-Digital Converter (ADC)
365
ADC Introduction
365
ADC Main Features
365
ADC Function Overview
365
Figure 12- 1 Single ADC Block Diagram
365
Table 12- 1 ADC Pins
366
ADC Switch
367
ADC Clock
367
Channel Selection
367
Single Conversion Mode
367
Continuous Conversion Mode
368
Timing Diagram
368
Analog Watchdog
368
Figure 12- 2 Timing Diagram
368
Scan Mode
369
Injected Channel Management
369
Table 12- 2 Analog Watchdog Channel Selection
369
Figure 12- 3 Analog Watchdog Guarded Area
369
Discontinuous Mode
370
Figure 12- 4 Injected Conversion Latency
370
Calibration
371
Data Alignment
372
Programmable Channel Sample Time
372
Conversion on External Trigger
372
Figure 12- 5 Calibration Timing Diagram
372
Figure 12- 6 Right-Alignment of Data
372
Figure 12- 7 Left-Alignment of Data
372
Table 12- 3 ADC1 and ADC2 Used in External Trigger for Regular Channels
373
Table 12- 4 ADC1 and ADC2 Used in External Trigger for Injected Channels
373
DMA Request
374
Temperature Sensor
374
Figure 12- 8 Channel Block Diagram of Temperature Sensor and V
374
ADC Interrupts
375
ADC Registers
375
Table 12- 5 ADC Interrupts
375
Table 12- 6 ADC Register Map and Reset Values
375
ADC Status Register (ADC_STS)
377
ADC Control Register 1 (ADC_CTRL1)
377
ADC Control Register 2 (ADC_CTRL2)
380
ADC Sample Time Register 1 (ADC_SMPT1)
383
ADC Sample Time Register 2 (ADC_SMPT2)
383
ADC Injected Channel Data Offset Register X (Adc_Jofsx) (X = 1
384
ADC Watchdog High Threshold Register (ADC_WHTR)
384
ADC Watchdog Low Threshold Register (ADC_WLTR)
385
ADC Regular Sequence Register 1 (ADC_RSQ1)
385
ADC Regular Sequence Register 2 (ADC_RSQ2)
385
ADC Regular Sequence Register 3 (ADC_RSQ3)
386
ADC Injected Sequence Register (ADC_JSQ)
387
ADC Injected Data Register X (Adc_Jdorx) (X = 1
387
ADC Regular Data Register (ADC_RDOR)
388
C Interface
389
C Introduction
389
I 2 C Main Features
389
C Function Overview
390
Mode Selection
390
Figure 13- 1 I2C Bus Protocol
390
C Slave Mode
391
Figure 13- 2 Block Diagram of I 2 C Function
391
Figure 13- 3 Transfer Sequence Diagram of Slave Transmitter
392
C Master Mode
393
Figure 13- 4 Transfer Sequence Diagram of Slave Receiver
393
Figure 13- 5 Transfer Sequence Diagram of Master Transmitter
395
Figure 13- 6 Transfer Sequence Diagram of Master Receiver
396
Figure 13- 7 Transfer Sequence Diagram for Master Receiver When N > 2
396
Figure 13- 8 Transfer Sequence Diagram for Master Receiver When N = 2
397
Error Condition
398
Figure 13- 9 Transfer Sequence Diagram for Master Receiver When N = 1
398
SDA/SCL Line Control
399
Smbus
399
Table 13- 1 Comparison between Smbus and I2C
399
DMA Request
401
Packet Error Checking (PEC)
402
C Interrupt Request
403
Table 13- 2 I2C Interrupt Request
403
C Debug Mode
404
C Registers
404
Table 13- 3 I2C Register Map and Reset Value
404
Figure 13- 10 I2C Interrupt Mapping Diagram
404
Control Register
405
C_Ctrl1)
405
Control Register
407
C_Ctrl2)
407
C_Oaddr1)
408
C_Oaddr2)
409
Data Register
409
C_Dt)
409
Status Register
409
C_Sts1)
409
Status Register 2 (I C_STS2)
412
Clock Control Register
413
C_Clkctrl)
413
TMRISE Register (I C_TMRISE)
414
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
415
USART Introduction
415
USART Main Features
415
USART Function Overview
416
USART Feature Description
417
Figure 14- 1 USART Block Diagram
417
Transmitter
418
Character Transmission
418
Figure 14- 2 Word Length Programming
418
Configurable Stop Bit
419
Figure 14- 3 Stop Bits Configuration
419
Single Byte Communication
420
Break Frame
420
Figure 14- 4 TRAC/TDE Behavior During Transmission
420
Idle Character
421
Receiver
421
Start Bit Detection
421
Figure 14- 5 Start Bit Detection
421
Character Reception
422
Break Frame
422
Idle Frame
422
Overrun Error
422
Table 14- 1 Sampled Data from Noise Detection
423
Figure 14- 6 Data Sampling for Noise Detection
423
Framing Error
424
Configurable Stop Bits During Reception
424
Fractional Baud Rate Generation
424
How to Derive USARTDIV from USART_ BAUDR Register Values
425
Table 14- 2 Error Calculation for Programming Baud Rates
425
USART Receiver's Tolerance to Clock Deviation
426
Multiprocessor Communication
426
Table 14- 3 USART Receiver Tolerance When Div_Decimal = 0
426
Table 14- 4 USART Receiver Tolerance When Div_Decimal! = 0
426
Idle Line Detection (WUMODE = 0)
427
Address Mark Detection (WUMODE = 1)
427
Parity Control
427
Figure 14- 7 Mute Mode Using Idle Line Detection
427
Figure 14- 8 Mute Mode Using Address Mark Detection
427
LIN (Local Interconnection Network) Mode
428
LIN Transmission
428
LIN Reception
428
Table 14- 5 Frame Format
428
Figure 14- 9 Break Detection in LIN Mode (11-Bit Break Length - the LBDLEN Bit Is Set)
429
USART Synchronous Mode
430
Figure 14- 10 Break Detection and Framing Error Detection in LIN Mode
430
Figure 14- 11 Example of USART Synchronous Transmission
431
Figure 14- 12 Example of USART Data Clock Timing (LEN = 0)
431
Single-Wire Half-Duplex Communication
432
Figure 14- 13 Example of USART Data Clock Timing (LEN = 1)
432
Figure 14- 14 Rx Data Setup/Hold Time
432
Smartcard
433
Figure 14- 15 ISO7816-3 Asynchronous Protocol
433
Figure 14- 16 Parity Error Detection Using 1.5 Stop Bits
434
Irda SIR ENDEC Block
435
Continuous Communication Using DMA
436
Transmission Using DMA
436
Figure 14- 17 Irda SIR ENDEC Block Diagram
436
Figure 14- 18 Irda Data Modulation (3/16) - Normal Mode
436
Reception Using DMA
437
Figure 14- 19 Transmission Using DMA
437
Figure 14- 20 Reception Using DMA
437
Error Flag and Interrupt Generation in Multi-Buffer Communication
438
Hardware Flow Control
438
RTS Flow Control
438
Figure 14- 21 Hardware Flow Control between Two USART
438
Figure 14- 22 RTS Flow Control
438
CTS Flow Control
439
USART Interrupt Request
439
Table 14- 6 USART Interrupt Request
439
Figure 14- 23 CTS Flow Control
439
USART Mode Configuration
440
USART Registers
440
USART Register Map
440
Table 14- 7 USART Mode Configuration
440
Figure 14- 24 USART Interrupt Mapping Diagram
440
Status Register (USART_STS)
441
Data Register (USART_DT)
443
Baud Rate Register (USART_BAUDR)
443
Control Register 1 (USART_CTRL1)
444
Control Register 2 (USART_CTRL2)
445
Control Register 3 (USART_CTRL3)
447
Guard Time and Prescaler Register (GTP)
448
Serial Peripheral Interface (SPI)
450
SPI Introduction
450
Main Features
450
SPI Main Features
450
I 2 S Function Overview
450
Function Overview
451
SPI Function Overview
451
Introduction
451
Figure 15- 1 SPI Block Diagram
451
Figure 15- 2 Single Master and Single Slave Application
452
Figure 15- 3 Hardware/Software Slave Select Management
453
Configure SPI in Slave Mode
454
Figure 15- 4 Data Clock Timing Diagram
454
Configure SPI in Master Mode
455
Configure SPI for Half-Duplex Communication
456
Data Transmission and Reception
456
CRC Calculation
462
Figure 15- 10 TE/BSY Behavior During Discontinuous Transfer (BDMODE = 0 and RONLY = 0)
462
Status Flag
463
Disabling SPI
464
SPI Communication Using DMA
464
Error Flag
466
Figure 15- 11 Transmission Using DMA
466
Figure 15- 12 Reception Using DMA
466
SPI Interrupt
467
S Function Overview
467
I 2 S Function Overview
467
Table 15- 1 SPI Interrupt Request
467
Figure 15- 13 I2S Block Diagram
468
Supported Audio Protocol
469
Figure 15- 14 I2S Philips Protocol Waveforms (16Bit/32-Bit Full Accuracy, CPOL = 0)
469
Figure 15- 15 I2S Philips Protocol Standard Waveforms (24-Bit Frame, CPOL = 0)
470
Figure 15- 16 Transmitting 0X8Eaa33
470
Figure 15- 17 Receiving 0X8Eaa33
470
Figure 15- 18 I2S Philips Protocol Standard Waveforms (16-Bit Extended to 32-Bit Frame, CPOL = 0)
470
Figure 15- 19 Example
471
Figure 15- 20 MSB-Justified 16-Bit or 32-Bit Full-Accuracy, CPOL = 0
471
Figure 15- 21 MSB-Justified 24-Bit Data, CPOL = 0
472
Figure 15- 22 MSB-Justified 16-Bit Data Extended to 32-Bit Frame, CPOL = 0
472
Figure 15- 23 LSB-Justified 16-Bit or 32-Bit Full-Accuracy, CPOL = 0
472
Figure 15- 24 LSB-Justified 24-Bit Data, CPOL = 0
473
Figure 15- 25 Operations Required to Transmit 0X3478Ae
473
Figure 15- 26 Operations Required to Receive 0X3478Ae
473
Figure 15- 27 LSB-Justified 16-Bit Data Extended to 32-Bit Frame, CPOL = 0
473
Figure 15- 28 Example
474
Figure 15- 29 PCM Standard Waveform (16-Bit)
474
Figure 15- 30 PCM Standard Waveform (16-Bit Extended to 32-Bit Package Frame)
474
Clock Generator
475
Figure 15- 31 Definition of Audio Sampling Frequency
475
Figure 15- 32 I2S Clock Generator Architecture
475
Table 15- 2 Audio-Frequency Precision Using System Clock
476
S Master Mode
477
S Slave Mode
478
Status Flag
479
Error Flag
480
S Interrupt
481
DMA Function
481
SPI Registers
481
Table 15- 3 I2S Interrupt Request
481
Table 15- 4 SPI Register Map and Reset Values
481
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)
483
SPI Control Register 2 (SPI_CTRL2)
484
SPI Status Register (SPI_STS)
485
SPI Data Register (SPI_DT)
486
SPICRC Polynomial Register (SPI_CPOLY) (Not Used in I S Mode)
486
Spirxcrc Register (SPI_RCRC)
487
Mode)
487
Spitxcrc Register (SPI_TCRC)
487
SPI_I2S Configuration Register (SPI_I2SCTRL)
487
SPI_I2S Prescaler Register (SPI_I2SCLKP)
489
CAN Bus Controller
490
Introduction
490
Main Features
490
Function Overview
490
CAN Overall Function Descr Iption
490
Figure 16- 1 CAN Network Topology
491
Operating Mode
492
Initialization Mode
492
Figure 16- 2 CAN Block Diagram
492
Normal Mode
493
Sleep Mode (Low Power)
493
Figure 16- 3 Bxcan Operating Mode
493
Test Mode
494
Silent Mode
494
Loopback Mode
494
Figure 16- 4 Bxcan in Silent Mode
494
Figure 16- 5 Bxcan in Loopback Mode
494
Loopback and Silent Mode
495
AT32F415 in Debug Mode
495
Transmission Handling
495
Figure 16- 6 Bxcan in Loopback and Silent Mode
495
Time-Triggered Communication Mode
496
Figure 16- 7 Transmit Mailbox States
496
Reception Handling
497
Figure 16- 8 Receive FIFO States
497
Identifier Filtering
498
Figure 16- 9 Filter Bank Scale Configuration - Register Organization
499
Figure 16- 10 Example of Filter Numbering
500
Message Storage
501
Figure 16- 11 Example of Filtering Mechanism
501
Table 16- 1 Transmit Mailbox Mapping
502
Table 16- 2 Receive Mailbox Mapping
502
Figure 16- 12 CAN Error State Diagram
502
Error Management
503
Bit Timing
503
Figure 16- 13 Bit Timing
504
Figure 16- 14 Various CAN Frames
505
Bxcan Interrupt
506
Figure 16- 15 Event Flag and Interrupt Generation
506
CAN Registers
507
Table 16- 3 CAN Register Map and Reset Values
507
Register Access Protection
509
CAN Control and Status Register
509
CAN Main Control Register (CAN_MCTRL)
509
CAN Main Status Register (CAN_MSTS)
511
CAN Tx Status Register (CAN_TSTS)
512
CAN Receive FIFO 0 Register (CAN_RF0)
514
CAN Receive FIFO 1 Register (CAN_RF1)
514
CAN Interrupts Enable Register (CAN_INTEN)
515
CAN Error Status Register (CAN_ESTS)
516
CAN Bit Timing Register (CAN_BTMG)
517
CAN Mailbox Register
518
Tx Mailbox Identifier Register (Can_Tmix) (X = 0
518
Figure 16- 16 Tx and Rx Mailboxes
518
Mailbox Data Length and Time Stamp Register ( Can_Tdtx)
519
Tx Mailbox Data Low Register (Can_Tdlx) (X = 0
520
Tx Mailbox Data High Register (Can_Tdhx) (X = 0
520
Rx FIFO Mailbox Identifier Register (Can_Rfix) (X = 0
521
Rx FIFO Mailbox Data Length and Time Stamp Register
521
(Can_Rdtx) (X = 0
521
Rx FIFO Mailbox Data High Register (Can_Rdlx) (X = 0
522
Rx FIFO Mailbox Data High Register (Can_Rdhx) (X = 0
522
CAN Filter Register
523
CAN Filter Main Control Register (CAN_FM)
523
CAN Filter Mode Register (CAN_FM1)
524
CAN Filter Scale Register (CAN_FS1)
524
CAN Filter FIFO Assignment Register (CAN_FFA1)
524
CAN Filter Activation Register (CAN_FA1)
525
CAN Filter Bank I Register X (Can_Fbirx)
525
(Where I = 0
525
SDIO Interface
527
Introduction
527
Main Features
527
Figure 17- 1 SDIO "No Response" and "No Data" Operation
528
Figure 17- 2 SDIO (Multiple) Data Block Read Operation
528
Figure 17- 3 SDIO (Multiple) Data Block Read Operation
528
Function Overview
529
SDIO Function Overview
529
Figure 17- 4 SDIO Sequential Read Operation
529
Figure 17- 5 SDIO Sequential Write Operation
529
SDIO Adapter
530
Table 17- 1 SDIO Pin Definitions
530
Figure 17- 6 SDIO Block Diagram
530
Figure 17- 7 SDIO Adaptor
531
Figure 17- 8 Control Unit
532
Figure 17- 9 SDIO Adapter Command Path
532
Figure 17- 10 Command Path State Machine (CPSM)
533
Table 17- 2 Command Format
534
Table 17- 3 Short Response Format
534
Figure 17- 11 SDIO Command Transfer
534
Table 17- 4 Long Response Format
535
Table 17- 5 Command Path Status Flags
535
Figure 17- 12 Data Path
535
Figure 17- 13 Data Path Status Machine (DPSM)
536
Table 17- 6 Data Token Format
537
SDIO AHB Interface
538
Table 17- 7 Transmit BUF Status Flag
538
Table 17- 8 Receive BUF Status Flag
538
Card Function Overview
539
Card Identification Mode
539
Card Reset
539
Operating Voltage Range Validation
539
Card Identification Process
540
Block Write
541
Block Read
541
Stream Access, Stream Write, and Stream Read
542
(Multimediacard Only)
542
Erase: Group Erase and Sector Erase
543
Wide Bus Selection or Deselection
543
Protection Management
543
Card Status Register
546
Table 17- 9 Card Status
546
SD Status Register
548
Table 17- 10 SD Status
549
Table 17- 11 Speed Class Code Field
550
Table 17- 12 Performance Move Field
550
Table 17- 13 AU_SIZE Field
550
Table 17- 14 the Maximum of AU Size
551
Table 17- 15 ERASE_SIZE Field
551
Table 17- 16 Erase Timeout Field
551
Table 17- 17 Erase Offset Field
551
SD I/O Mode
552
Command and Response
552
Table 17- 18 Block-Oriented Write Command
553
Table 17- 19 Block-Oriented Write Protection Command
554
Table 17- 20 Erase Command
554
Table 17- 21 I/O Mode Command
554
Table 17- 22 Lock Command
554
Response Format
555
R1 (Normal Response Command)
555
R1B
555
Table 17- 23 Application-Specific Command
555
Table 17- 24 R1 Response
555
R2 (the CID and CSD Registers)
556
R3 (the OCR Register)
556
R4 (Fast I/O)
556
Table 17- 25 R2 Response
556
Table 17- 26 R3 Response
556
Table 17- 27 R4 Response
556
R4B
557
R5 (Interrupt Request)
557
Table 17- 28 R4B Response
557
Table 17- 29 R5 Response
557
R6 (Interrupt Request)
558
SDIO I/O Card-Specific Operation
558
SDIO I/O Read Wait Operation by SDIO_D2 Signaling
558
SDIO Read Wait Operation by Stopping SDIO_CK
558
Table 17- 30 R6 Response
558
SDIO Suspend/Resume Operation
559
SDIO Interrupts
559
Hardware Flow Control
559
SDIO Registers
559
Table 17- 31 SDIO Register Map
559
SDIO Power Control Register (SDIO_POWER)
561
SDIO Clock Control Register (SDIO_CLKCTRL)
561
SDIO Argument Register (SDIO_ARG)
562
SDIO Command Register (SDIO_CMD)
563
SDIO Command Response Register (SDIO_RSPCMD)
564
SDIO Response 1
564
Table 17- 32 Response Types and the Sdio_Rspx Register
564
SDIO Data Timer Register (SDIO_DTTMR)
565
SDIO Data Length Register (SDIO_DTLEN)
565
SDIO Data Control Register (SDIO_DTCTRL)
566
SDIO Data Counter Register (SDIO_DTCNTR)
567
SDIO Status Register (SDIO_STS)
567
SDIO Clear Interrupt Register (SDIO_INTCLR)
568
SDIO Interrupt Mask Register (SDIO_INTEN)
569
SDIO BUF Counter Register (SDIO_BUFCNTR)
571
SDIO Data BUF Register (SDIO_BUF)
572
MCU Debug (MCUDBG)
573
Introduction
573
Figure 18- 1 Block Diagram of AT32F415-Level and Cortex
573
Function Overview
574
Debug Support for Low-Power Mode
574
Debug Support for Timer, Watchdog, Bxcan, and I C
574
ID Code
574
SWJ Debug Port Pins
574
Internal Pull-Up and Pull-Down on JTAG Pins
574
Trace Pin Assignment
575
MCUDBG Registers
575
Table 18- 1 Flexible Trace Pin Assignment
575
Table 18- 2 MCUDBG Register Address Map and Reset Value
575
MCUDBG Control Register (MCUDBG_CTRL)
576
Comparator (COMP)
578
COMP Introduction
578
COMP Main Characteristics
578
Comparator Function Overview
578
Comparator Block Diagram
578
Figure 19- 1 Block Diagram of Comparator 1 and Comparator 2
578
COMP Pins and Internal Signals
579
Comparator Reset and Clock
579
Comparator Lock Mechanism
579
Hysteresis
579
Figure 19- 2 Comparator Hysteresis
579
Power Mode
580
Interference Filter
580
Figure 19- 3 Interference Filter Timing Sequence Diagram When H_PULSE_CNT = 1 and
580
Figure 19- 4 Interference Filter Timing Sequence Diagram When H_PULSE_CNT = 2 and
580
COMP Interrupt
581
COMP Register
581
Table 19- 1 COMP Register Mapping and Reset Value
581
Comparator Control and Status Register 1 (COMP_CTRLSTS1)
582
Comparator Control/Status Register 2 (COMP_CTRLSTS2)
584
Glitch Filter Enable Register (G_FILTER_EN)
584
Interference Filter High Pulse (HIGH_PULSE)
585
Interference Filter Low Pulse (LOW
585
HSI Auto Clock Calibration
586
ACC Introduction
586
ACC Main Features
586
ACC Function Overview
586
ACC Characteristics
587
Figure 20- 1 ACC Block Diagram
587
Figure 20- 2 Cross-Return Strategy
587
ACC Interrupt Request
588
Table 20- 1 ACC Interrupt Request
588
ACC Register Description
589
ACC Register Address Mapping
589
Figure 20- 3 ACC Interrupt Mapping Diagram
589
Status Register (ACC_STS)
590
Control Register 1 (ACC_CTRL1)
590
Control Register 2 (ACC_CTRL2)
591
Compare Value 1 (ACC_C1)
592
Compare Value 2 (ACC_C2)
592
Compare Value 3 (ACC_C3)
592
USB OTG Full-Speed (OTG_FS)
593
OTG Module Introduction
593
OTG_FS Main Features
593
General Functions
593
Host Mode Function
594
Device Mode Function
594
OTG_FS Function Descriptions
595
OTG Full-Speed Core
595
Full-Speed OTG PHY (Port Physical Layer)
595
Figure 21- 1 Function Diagram
595
Dual-Role Device (DRD)
596
ID Signal Detection
596
USB Device Mode
596
Figure 21- 2 OTG A-B Device Connection
596
Device State
597
Figure 21- 3 Simple USB Peripheral Connections
597
Device Endpoint
598
USB Host Mode
599
USB Host States
600
Figure 21- 4 Simple USB Host Connections
600
Host Channel
601
Host Scheduler
602
SOF Trigger
604
Host Sofs
604
Device Sofs
604
Figure 21- 5 SOF Connection
604
Power Supply Option
605
USB Data FIFO
606
Figure 21- 6 OTG_FS Core Diagram
606
Device FIFO Architecture
607
Device RX FIFO
607
Device TX FIFO
607
Figure 21- 7 FIFO Address Mapping and AHB FIFO Mapping in Device Mode
607
Host FIFO Architecture
608
Host RX FIFO
608
Figure 21- 8 FIFO Address Mapping and AHB FIFO Mapping in Host Mode
608
Host TX FIFO
609
USB System Performance
609
OTG_FS Interrupt
610
OTG_FS Control and Status Register
610
Figure 21- 9 Interrupt Structure
610
CSR Register Mapping
611
Figure 21- 10 CSR Register Mapping
611
Table 21- 1 Controller Global Control and Status Register (Csrs)
612
Table 21- 2 Control and Status Register (Csrs) in Host Mode
612
Table 21- 3 Device Mode Control and Status Register
613
Table 21- 4 Data FIFO (DFIFO) Access Register
614
Table 21- 5 Power Supply and Gate Control and Status Register
614
OTG_FS Register Address Mapping
615
Table 21- 6 OTG_FS Register Mapping and Reset Values
615
OTG_FS Global Registers
622
OTG_FS AHB Configuration Register (OTG_FS_GAHBCFG)
622
OTG_FS_USB Configuration Register (OTG_FS_GUSBCFG)
623
OTG_FS Reset Register (OTG_FS_GRSTCTL)
624
OTG_FS Core Interrupt Register (OTG_FS_GINTSTS)
625
OTG_FS Interrupt Mask Register (OTG_FS_GINTMSK)
628
OTG_FS RX Status Debug Read/Otg Status Read and POP Register
630
(Otg_Fs_Grxstsr/Otg_Fs_Grxstsp)
630
OTG_FSRX FIFO Size Register (OTG_FS_GRXFSIZ)
632
OTG_FS Non-Periodic TX FIFO Size Register (OTG_FS_GNPTXFSIZ)
632
OTG_FS Non-Periodic TX Fifo/Request Queue Status Register
633
(Otg_Fs_Gnptxsts)
633
OTG_FS General Core Configuration Register (OTG_FS_GCCFG)
634
OTG_FS Core ID Register (OTG_FS_GUID)
635
OTG_FS Host Periodic TX FIFO Size Register (OTG_FS_HPTXFSIZ)
635
(Where N Is FIFO Number, N = 1
636
Host Mode Registers
636
OTG_FS Host Mode Configuration Register (OTG_FS_HCFG)
636
OTG_FS Host Frame Interval Register (OTG_FS_HFIR)
637
OTG_FS Host Frame Number/Frame Time Remaining Register
637
(Otg_Fs_Hfnum)
637
OTG_FS Host Periodic TX Fifo/Request Queue Register
638
(Otg_Fs_Hptxsts)
638
OTG_FS Host All Channel Interrupt Register (OTG_FS_HAINT)
639
OTG_FS Host All Channel Interrupt Mask Register (OTG_FS_HAINTMSK)
639
OTG_FS Host Port Control and Status Register (OTG_FS_HPRT)
639
OTG_FS Host Channel X Characteristic Register (Otg_Fs_Hccharx)
642
Channel Number, X = 0
642
OTG_FS Host Channel X Interrupt Register (Otg_Fs_Hcintx)
643
Number, X = 0
643
OTG_FS Host Channel X Interrupt Mask Register (Otg_Fs_Hcintmskx)
644
Channel Number, X = 0
644
OTG_FS Host Channel X Transfer Size Register (Otg_Fs_Hctsizx)
645
Channel Number, X = 0
645
Device Mode Registers
645
OTG_FS Device Configuration Register (OTG_FS_DCFG)
645
OTG_FS Device Control Register (OTG_FS_DCTL)
646
OTG_FS Device Status Register (OTG_FS_DSTS)
647
Table 21- 7 Minimum Duration of Software Disconnect
647
OTG_FS Device in Endpoint General Interrupt Mask Register
648
(Otg_Fs_Diepmsk)
648
OTG_FS Device out Endpoint General Interrupt Mask Register
649
(Otg_Fs_Doepmsk)
649
OTG_FS Device All Endpoint Interrupt Register (OTG_FS_DAINT)
650
OTG_FS Device All Endpoint Interrupt Mask Register
651
(Otg_Fs_Daintmsk)
651
OTG_FS Device in Endpoint FIFO Empty Interrupt Mask Register
651
OTG_FS Device Control in Endpoint 0 Control Register (OTG_FS_DIEPCTL0)
652
OTG_FS Device Endpoint X Control Register (Otg_Fs_Diepctlx)
653
OTG_FS Device Control out Endpoint 0 Control Register (OTG_FS_DOEPCTL0)
655
OTG_FS Device out Endpoint X Control Register (Otg_Fs_Doepctlx)
656
OTG_FS Device Endpoint X Interrupt Register (Otg_Fs_Diepintx)
658
OTG_FS Device Endpoint X Interrupt Register (Otg_Fs_Doepintx)
658
OTG_FS Device in Endpoint 0 Transfer Size Register (OTG_FS_DIEPTSIZ0)
660
OTG_FS Device out Endpoint 0 Transfer Size Register (OTG_FS_DOEPTSIZ0)
661
OTG_FS Device Endpoint X Transfer Size Register
662
(Otg_Fs_Dieptsizx)(Where X Is Endpoint Number, X = 1
662
OTG_FS Device in Endpoint TX FIFO Status Register (OTG-Fs_Dtxfstsx)
663
Is Endpoint Number, X = 0
663
OTG_FS Device Endpoint X Transfer Size Register
663
(Otg_Fs_Doeptsizx)(Where X Is Endpoint Number, X = 1
663
OTG_FS Programming Model
665
Core Initialization
665
Host Mode Initialization
665
Device Mode Initialization
666
Host Mode Programming Model
666
Figure 21- 11 TX FIFO Write Task
668
Figure 21- 12 RX FIFO Read Task
669
Figure 21- 13 Normal Bulk/Control OUT/SETUP and in Transaction Procedure
670
Figure 21- 14 Bulk/Control in Transaction Procedur E
673
Figure 21- 15 Normal Interrupt OUT/IN Transaction P Rocedure
675
Figure 21- 16 Normal Isochronous OUT/IN Transaction Procedure
679
Device Mode Programming Model
682
Operation Model
683
Figure 21- 17 Reading RX FIFO Data Message in Slave Mode
684
Figure 21- 18 Processing a SETUP Data Message
686
Figure 21- 19 Bulk out Transaction
691
Worst Case Response Time
697
Figure 21- 20 TRDTIM under Maximum Time Sequence
698
Revision History
699
Table 22- 1 Document Revision History
699
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