ARTERY AT32A423CCT7 Manuals
Manuals and User Guides for ARTERY AT32A423CCT7. We have 1 ARTERY AT32A423CCT7 manual available for free PDF download: Reference Manual
ARTERY AT32A423CCT7 Reference Manual (513 pages)
ARM-based 32-bit Cortex-M4F MCU, 64 to 256 KB Flash, sLib, 15 timers, 1 ADC, 18 communication interfaces (CAN and OTGFS)
Brand: ARTERY
|
Category: Computer Hardware
|
Size: 7 MB
Table of Contents
-
Bit Band35
-
Reset41
-
Flash Memory44
-
SRAM Memory46
-
Introduction49
-
Por/Lvr49
-
Power Domain51
-
Clock56
-
System Clock58
-
Interrupts59
-
Reset59
-
System Reset59
-
Unlock/Lock80
-
Unlock/Lock84
-
Read Access88
-
CRC Verify89
-
Introduction97
-
GPIO Registers111
-
Introduction115
-
SCFG Registers115
-
EXINT Registers121
-
Introduction123
-
Main Features123
-
Arbiter124
-
Errors125
-
Interrupts126
-
DMA Registers129
-
CRC Introduction138
-
CRC Registers139
-
C Interface141
-
I 2 C Interface142
-
C Timing Control144
-
Smbus156
-
Error Management166
-
I 2 C Debug Mode168
-
I 2 C Registers168
-
Mode Selector176
-
Introduction176
-
Introduction182
-
Configuration182
-
Transmitter183
-
Receiver184
-
Low-Power Wakeup186
-
Tx/Rx Swap187
-
I/O Pin Control188
-
USART Registers188
-
SPI Introduction196
-
SPI Description196
-
Crc201
-
DMA Transfer202
-
TI Mode202
-
Transmitter203
-
Receiver203
-
Motorola Mode204
-
TI Mode206
-
Interrupts207
-
IO Pin Control207
-
Precautions207
-
S Introduction208
-
S Full-Duplex209
-
DMA Transfer213
-
Interrupts215
-
IO Pin Control215
-
SPI Registers215
-
Mode)215
-
Mode)218
-
Timer221
-
Counting Clock222
-
Counting Mode222
-
Debug Mode223
-
Counting Clock227
-
Counting Mode230
-
Debug Mode242
-
Counting Clock253
-
Counting Mode256
-
Debug Mode267
-
Counting Clock278
-
Counting Mode279
-
Debug Mode287
-
Tmrx Registers288
-
Counting Clock297
-
Counting Mode300
-
Debug Mode314
-
TMR1 Registers314
-
Debug Mode329
-
WWDT Registers329
-
WDT Introduction331
-
Debug Mode332
-
WDT Registers332
-
ERTC Clock336
-
ERTC Calibration338
-
Tamper Detection339
-
ERTC Wakeup341
-
ERTC Registers342
-
ADC Introduction351
-
ADC Structure352
-
Trigger355
-
Sequence Mode356
-
Repetition Mode357
-
Partition Mode357
-
Oversampling358
-
Data Management360
-
Data Alignment360
-
Data Read361
-
ADC Registers362
-
DAC Introduction376
-
Trigger Events377
-
DAC Registers379
-
CAN Introduction385
-
Baud Rate385
-
Design Tips389
-
Operating Modes390
-
Test Modes390
-
Error Management395
-
CAN Registers396
-
OTGFS Structure410
-
OTGFS Interrupts412
-
Device Mode413
-
Host Mode414
-
OTGFS Host Mode415
-
Queue Depth416
-
Special Cases418
-
CSR Register Map447
-
(Otgfs_Gnptxsts)462
-
(X = 0470
-
(X=X=1476
-
(Otgfs_Doepctl0)478
-
(X=0481
-
ACC Introduction486
-
Main Features486
-
Principle488
-
ACC Register Map489
-
XMC Introduction493
-
XMC Architecture494
-
Block Diagram494
-
Address Mapping495
-
Nor/Psram495
-
Operating Mode496
-
Access Mode497
-
Multiplexed Mode497
-
Synchronous Mode499
-
XMC Registers501
-
Debug (DEBUG)507
-
Debug and Trace507
-
I/O Pin Control507
-
DEGUB Registers507
-
Revision History512
Advertisement
Advertisement