User Manuals: Aptina MT9T111 Image Sensor Module

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Aptina MT9T111 Manual (147 pages)

1/4-Inch 3.1Mp System-On-A-Chip (SOC) CMOS Digital Image Sensor

Brand: Aptina | Category: Accessories | Size: 6 MB

About this Document
1
Introduction to Registers
2
Accessing the Firmware Drivers' Variables
2
Write Access
2
Read Access
2
Figure 2: Firmware Variable Legend
2
Refresh Mode and Refresh Commands
3
MCU Memory
3
Conventions and Notations
3
Table 1: R0X098E[15:0], Indirect Access Address Register
3
Table of Contents
4
Overview
11
System Configuration
12
Figure 3: Typical Configuration (Connection)
12
Signal Description
14
I/O Signals
16
Table 3: Attributes of I/O and Power Supply Signals
16
Table 4: Output Signal States During Reset and Standby
17
Low-Noise Operation
18
Table 5: Power Supply Descriptions
18
Table 6: Recommended System Power Connections (5 Pins)
18
Table 7: Recommended System Power Connections (4 Pins)
18
Architecture Overview
19
PLL and Clock Divider
20
PIXCLK and DOUT [7:0] Timing
21
Table 9: MT9T111 Clock Calculation Summary
22
Table 10: PLL and Clock Related Registers and Variables
23
PLL Bypass Mode
24
Low Power Mode
24
Example of Code to Program PLL and Clocks
24
RX and TX FIFO Watermark
26
Figure 6: Watermark Block Diagram
26
Table 11: Watermark Values to be Programmed
26
Example of .Ini File to Program the Watermark
27
Output Slew Rate Control
28
Figure 7: Output Slew Rate Defined
28
Table 12: Slew Rate Control Related Registers
28
GPIO Control
29
Overview of GPIO Signals
29
Table 13: GPIO Related Registers and Variables
29
Table 14: GPIO Input / Output Multiplexer Control
30
One-Time Programmable (OTP) Memory
33
MT9T111 Rev3 Silicon OTP Memory Programming Procedure
34
Step 1: Sensor Setup
34
Step 2: Initialize the Sensor for OTP Memory Programming
34
Step 3: Programming the Data
34
Device ID
36
Module ID
36
Table 15: Device ID Related Registers and Variables
36
Master Two-Wire Serial Interface
37
And External Sensor Control Interface
37
Table 16: Control of an External Secondary Sensor
37
Output Interface
38
Figure 13: Output Interface Block
38
JPEG Encoder
39
JPEG Encoding Highlights
39
JPEG Output Interface
39
JPEG Data
39
RGB Thumbnail
40
JPEG Continuous Stream
41
Figure 14: JPEG Continuous Data Output
41
JPEG Spoof Stream
42
Figure 16: JPEG Spoof Mode Timing with Continuous Clock
42
JPEG Spoof Stream in MIPI Output Mode
43
Figure 17: JPEG Spoof Mode Timing with Adaptive Clock
43
JPEG Stream with Embedded Thumbnail Image
44
Figure 18: JPEG Spoof Mode Timing with Thumbnail
44
Transfer Modes
45
Bypass Mode
45
Continuous Mode
45
Table 17: Transfer Modes and Sources
45
Spoof Mode
46
Thumbnail Index Table
46
Thumbnail Index Pointer
47
JPEG Status Segment
47
Figure 19: Contents of Status Segment
47
Figure 20: JPEG Data Segment Structure
48
Utilization of the Thumbnail Index Pointer
49
Original JPEG and Thumbnail Image Resolution
49
JPEG and Thumbnail Length Information
49
JPEG Status Information
50
Error Handling
51
FIFO Underflow
51
FIFO Overflow
51
Frame Overflow
51
Spoof Oversize Error
52
Parallel Output Interface
52
Protocol
52
Features
52
Adaptive Clock Switching
53
Table 20: Clock Switching Criteria
53
Output Interface Timing
54
Parallel Output Interface
54
Summary of Parallel Output Interface Options
54
Table 21: Parallel Output Interface Options
54
JPEG Bypass Stream and Color Pipe Bypass Stream
56
Case 1: Parallel Bypass Output with Clock Enabled
56
Case 2: Parallel Bypass Output with Clock Disabled between Frames
56
Figure 21: Timing of Parallel Bypass Output with Clock Enabled
56
Figure 22: Timing of Parallel Bypass Output with Clock Disabled between Frames
56
Case 3: Parallel Bypass Output with Clock Disabled between Lines
57
Case 4: Parallel Bypass Output with Clock Disabled and CCIR Codes Inserted
57
Figure 23: Timing of Parallel Bypass Output with Clock Disabled between Lines
57
Figure 24: Timing of Parallel Bypass Output with Clock Disabled and CCIR Codes Inserted
57
JPEG Continuous Stream
58
Case 1: Parallel Output with Continuous Clock
58
Figure 25: Timing of Parallel Output with Continuous Clock
58
Case 2: Parallel Output with Gated Clock
59
Case 3: Parallel Output When LINE_VALID Is Enabled During FRAME_VALID
59
Figure 26: Timing of Parallel Output with Gated Clock
59
Figure 27: Timing of Parallel Output with Gated Clock
59
Case 4: Parallel Output When SOI and EOI Are Enabled During FRAME_VALID
60
Case 5: Parallel Output When SOI and EOI Are Enabled but Not During FRAME_VALID
60
Figure 28: Timing of Parallel Output When SOI and EOI Are Enabled During FRAME_VALID
60
Figure 29: Timing of Parallel Output When SOI and EOI Are Enabled but Not During FRAME_VALID
60
Case 6: Parallel Output with SOI/EOI, FRAME_VALID, and JPEG Status Inserted
61
Case 7: Parallel Output with Embedded Thumbnail Data
61
Figure 30: Timing of Parallel Output with SOI/EOI, FRAME_VALID, and JPEG Status Inserted
61
Figure 31: Timing of Parallel Output with Embedded Thumbnail Data
61
Case 8: Parallel Output with Adaptive Clock Switching
62
Case 9: Parallel Output with Adaptive Clock Switching and Embedded Thumbnail Data
62
Figure 32: Timing of Parallel Output with Adaptive Clock Switching
62
Figure 33: Timing of Parallel Output with Adaptive Clock Switching and Embedded Thumbnail Data
62
Case 10: Parallel Output with Gated PIXCLK
63
Figure 34: Timing of Parallel Output with Gated PIXCLK
63
JPEG Spoof Stream
64
Case 1: PIXCLK Disabled between Lines and Frames
64
Figure 35: Timing of PIXCLK Disabled between Lines and Frames
64
Case 2: PIXCLK Enabled between Lines but Disabled between Frames
65
Case 3: Thumbnail Stream with One Frame of Data
65
Figure 36: Timing of PIXCLK Enabled between Lines but Disabled between Frames
65
Figure 37: Timing of Thumbnail Stream with One Frame of Data
65
Case 4: Thumbnail Enabled with Less than One Frame of Data
66
Case 5: Adaptive Clock Switching with PIXCLK Enabled between Lines
66
Figure 38: Timing of Thumbnail Stream with Less than One Frame of Data
66
Figure 39: Timing of Adaptive Clock Switching with PIXCLK Enabled between Line
66
Output Data Format
67
Selecting Output Data Formats
67
Table 22: Changing Output Format Variables
67
Outputting Raw Bayer Data
68
YUV Output
68
Table 23: Output Format Option Configuration Settings
68
Table 24: Ycrcb Output Data Ordering
68
RGB Output
69
Table 25: RGB Ordering in Default Mode
69
Walking 1S Test Pattern
70
Figure 40: Sample Operation on One Line
70
Procedure
71
Figure 41: Sample Operation for Multiple Lines with Horizontal Blanking
71
Sensor Core Interface
72
Figure 42: Spatial Illustration of Image Readout
72
Mirroring and Flipping the Image
73
Image Test Pattern Generation
74
Programming and Operation
75
Figure 43: Register and Variable Interfaces
75
Table 26: Summary of MT9T111 Registers and Variables
76
Power-On Operation
77
Example of Ini File for Power-On Sequence
77
Standby
78
Entering Standby Mode
78
Table 27: Standby Operation in Different Modes
78
Exiting Standby Mode
79
Timing Specifications
80
Power-Up Sequence for Rev2 Silicon
80
Figure 44: Power-Up Sequence Rev2 Silicon
80
Table 28: Power-Up Signal Timing for Rev2 Silicon
80
Power-Up Sequence for Rev3 Silicon
81
Figure 45: Power-Up Sequence Rev3 Silicon
81
Table 29: Power-Up Signal Timing Rev3 Silicon
81
Reset
82
Hard Reset
82
Figure 46: Hard Reset Signal Sequence
82
Table 30: Hard Reset Signal Timing
82
Soft Reset
83
Standby Modes
84
Hard Standby with Shutdown Mode
84
Hard Standby with Memory Retention Mode
84
Figure 48: Hard Standby Signal Sequence Mode
84
Soft Standby with State Retention
85
Figure 49: Soft Standby Signal Sequence
85
Table 32: Hard Standby Signal Timing
85
Table 33: Soft Standby Signal Timing
85
Image Signal Processing Flow and Camera Control
86
Context Switching and Output Configuration
86
Figure 50: State Machine for Context Switching
86
Setting up Preview (A) and Capture (B) Modes
87
Examples of Switching from One Context to Another
87
Scaling
88
Examples of .Ini Settings for Different Output Resolutions
88
Zoom
89
Enabling Special Effects
90
Examples of Programming for Special Effects
90
Auto Focus
91
AF Algorithm
91
Figure 51: Auto Focus Functional Block Diagram
91
AF Mode
92
Table 34: Auto Focus Ics Supported by the MT9T111
92
Example of Programming Simple Full-Scan Triggering Operation
93
Anti-Shake
94
Introduction
94
Algorithm Description
94
Figure 54: Anti-Shake Algorithm
94
Configuration
95
Example of Settings for Anti-Shake
95
Lens Shading Correction (LC)
97
Related Registers for the Lens Shading Algorithm
97
Example: PGA Values for LC
97
Auto White Balance (AWB)
100
Color Correction Procedure
100
Table 35: Color Correction Matrix Structure
100
AWB Procedure
101
Example: CCM Values for AWB
101
Auto Exposure (AE)
103
Introduction
103
AE Driver
103
Evaluation Algorithm
104
Accelerated Settling During Overexposure
104
Exposure Control
104
Configuration
104
Related Registers
105
Example: AE Control
105
Flicker Avoidance
107
How to Use the Flicker Detection Driver
107
How to Fine-Tune the Anti-Flicker Driver Settings
108
How to Verify the Anti-Flicker Driver Settings
109
Gamma
110
Bright Scenes
111
Dark Scenes
111
Figure 55: Gamma Correction in Bright Scenes
111
Figure 56: Gamma Correction in Dark Scenes
111
Gamma/Contrast Manual Control
112
Gamma/Contrast Automatic Control
112
Example: Gamma Control
112
Development Tool Overview
115
Figure 57: Development Tool Overview
115
Register Wizard
116
Procedure for Generating Frame Timing Setting
116
Input Clock and PLL Output Frequencies
116
Image Timing
116
Register Wizard - Register Output
117
Figure 58: Register Wizard PLL Menu
117
Lens Calibration Procedure
122
Equipment
122
Setup
122
Figure 59: Lens Calibration Equipment Setup
122
Table 36: Recommended Equipment and Settings
122
Calibration Procedure
123
Figure 60: Check Image to See if It Is Flipped Correctly
124
Using Devware for the Lens Calibration
125
Figure 62: Sensor Array and Row Column Selection
125
Figure 63: Lens Correction Curves
126
Calibration Procedure Summary
128
Color Tuning Procedure
129
Figure 65: Color Tuning Lab Setup
129
Calibration of True Gray (TG) Limits
139
Appendix A - Dual Camera Implementation
141
Figure 66: Dual Camera System Level
141
Figure 67: Dual Camera Data Flow Diagram
142
Figure 68: Dual Camera Typical Interconnect
143
Appendix B - Demo Board Systems
145
Figure 69: Demo Board (Parallel Mode)
145
Figure 70: Demo Board (Serial Mode)
146
Revision History
147

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User Manuals: Aptina MT9T111 Image Sensor Module

Aptina MT9T111 Manual (147 pages)

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