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AppoTech AX2228D Manuals
Manuals and User Guides for AppoTech AX2228D. We have
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AppoTech AX2228D manual available for free PDF download: User Manual
AppoTech AX2228D User Manual (139 pages)
Audio Player Microcontroller
Brand:
AppoTech
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Table of Contents
2
Figure
6
Table
6
Register
7
1 Product Overview
13
Outline
13
Features
13
System Architecture
14
2 Pin Definitions
15
Ax2228D
15
Packages
15
Pin Assignment
15
Pin Descriptions
15
3 CPU Core Information
20
Architecture
20
Instruction Set
20
Memory Mapping
23
Program Memory Mapping
23
External Data Memory Mapping
24
Internal Data Memory Mapping
24
Interrupt Processing
25
Interrupt Sources
25
Interrupt Priority
27
CPU and Memory Related SFR Description
27
Register 3-2 DPL0 – Data Pointer Low Byte
28
Register 3-6 SP – Stack Pointer Low Byte
29
Register 3-9 SPMODE – Special Mode
30
Register 3-11 IE1 – Interrupt Enable 1
31
Register 3-13 IP0 – Interrupt Priority 0
32
Register 3-14 IPH1 – Interrupt Priority High 1
33
4 Reset Generation
35
Power-On Reset (POR)
35
System Reset
35
AX2228D Audio Player Microcontroller Version
35
Copyright © 2015, Www.appotech.com. All Rights Reserved
35
Lvd
36
Appendix I Revision History
36
Figure 4-2 Reset Sources
36
Register 4-1 LVDCON– LVD Control
37
Clock System
38
Clock Control
38
Register 4-3 PCON1 – Power Control 1
39
Port Wakeup Reset
38
RTCC Reset
38
Watchdog Reset
38
Register 4-4 PCON2 - Power Control 2
40
Register 4-5 PCON3 - Power Control 3
40
Register 4-6 CLKCON - Clock Control
41
Figure 4-3 Source of XCK12V
42
Register 4-7 CLKCON1 - Clock Control 1
42
Register 4-8 CLKCON2 - Clock Control 2
43
Phase Lock Loop (PLL)
44
Register 4-8 CLKCON3- Clock Control 3
44
Register 4-9 PLLCON - PLL Configuration
44
Register 4-10 PLLCON2 - PLL Configuration2
45
Register 4-11 PLLINTH - PLL Integer High
45
Register 4-12 PLLINTL - PLL Integer Low
46
Register 4-13 PLLFRACH - PLL Fraction High
46
Register 4-14 PLLFRACL - PLL Fraction Low
46
5 Low Power Management
48
Power Saving Mode
48
Sleep Mode
48
Hold Mode
48
Idle Mode
48
Deep Sleep Mode
49
Power down Mode
49
Power Supply
50
Register 5-1 PWRCON1 - Power Control 1
50
Register 5-2 PWRCON2 - Power Control 2
51
6 General Purpose Input/Output (GPIO)
52
Overview
52
Features
52
Function Multiplexing
52
Table 6-2 Ports Multiplexed Mapping
53
GPIO Special Function Registers
54
Register 6-1 P0DIR-P0 Direction Register
54
Register 6-2 P1DIR-P1 Direction Register
54
Register 6-3 P2DIR-P2 Direction Register
54
Register 6-4 P3DIR-P3 Direction Register
54
Register 6-4 P4DIR-P4 Direction Register
55
Register 6-1 SRCCON-Slew Rate Control Register
55
Register 6-5 P0 - P0 Data Register
55
Register 6-6 P1 - P1 Data Register
56
Register 6-7 P2 - P2 Data Register
56
Register 6-8 P3 - P3 Data Register
56
Register 6-8 P4 - P4 Data Register
56
Register 6-9 P0PU0 - P0 Pull-Up Resistor Control
56
Register 6-10 P1PU0 - P1 Pull-Up Resistor Control
57
Register 6-11 P2PU0 - P2 Pull-Up Resistor Control Low Byte
57
Register 6-12 P2PU1 - P2 Pull-Up Resistor Control High Byte
57
Register 6-13 P3PU0 - P3 Pull-Up Resistor Control
57
Register 6-9 P4PU0 - P4 Pull-Up Resistor Control
58
Register 6-10 PU200- Pull-Up 200Ωresistor Control
58
Register 6-14 P0PD0 - P0 Pull-Down Resistor Control
59
Register 6-15 P1PD0 - P1 10KΩ Pull-Down Resistor Control
59
Register 6-16 P2PD0 - P2 3.3KΩ Pull-Down Resistor Control
59
AX2228D Audio Player Microcontroller Version
59
Copyright © 2015, Www.appotech.com. All Rights Reserved
59
Register 6-17 P2PD1 - P2 0.5KΩ Pull-Down Resistor Control
59
Register 6-18 P3PD0 - P3 10KΩ Pull-Down Resistor Control
60
Register 6-19 P3PUD1 - P3 10KΩ Pull-Down Resistor Control
60
Register 6-14 P4PD0 - P4 Pull-Down Resistor Control
60
Register 6-20 PIE0 - Port Digital Input Enable Control
61
Register 6-21 PIE1 - Port Digital Input Enable Control1
61
Register 6-21 PIE2 - Port Digital Input Enable Control2
62
Register 6-22 P0DRV0 - Port 0 Driving Control
62
Register 6-23 P1DRV0 - Port 1 Driving Control 0
63
Register 6-24 P1DRV1 - Port 1 Driving Control 1
63
Register 6-25 P2DRV0 - Port 2 Driving Control
64
Register 6-26 P3DRV0 - Port 3 Driving Control
65
Register 6-27 P3DRV1 - Port 3 Driving Control
66
Register 6-28 PMUXCON0 - Port Function MUX Control 0
66
Port Interrupt and Wakeup
67
Wakeup Registers
67
Register 6-29 PWKEN - Port Wakeup Enable
67
Register 6-30 PWKEDGE - Port Wakeup Event Select
68
Operation Guide
69
7 Timers
70
Timer0
70
Timer0 Features
70
Timer0 Special Function Registers
70
Register 7-1 TMR0CON - Timer0 Control
70
Timer1
71
Register 7-2 TMR0CNT - Timer0 Counter
71
Register 7-3 TMR0PR - Timer0 Period
71
Register 7-4 TMR0PWM - Timer0 PWM Duty
71
Timer1 Features
72
Timer1 Special Function Registers
72
Register 7-5 TMR1CON0 - Timer1 Control 0
72
Register 7-6 TMR1CON1 - Timer1 Control 1
73
Register 7-7 TMR1CNTH/TMR1CNTL - Timer1 Counter
74
Register 7-8 TMR1PRH/TMR1PRL - Timer1 Period
74
Register 7-9 TMR1PWMH/TMR1PWML - Timer1 PWM Duty
74
Register 7-10 TMR2CON0 - Timer2 Control 0
74
Timer2
74
Register 7-11 TMR2CON1 - Timer2 Control 1
75
Register 7-12 TMR2CNTH/TMR2CNTL - Timer2 Counter
76
Register 7-13 TMR2PRH/TMR2PRL - Timer2 Period
76
Register 7-14 TMR2PWMH/TMR2PWML - Timer2 PWM Duty
76
Register 7-15 TMR3CON - Timer3 Control
76
Timer3
76
Register 7-16 TMR3CNT - Timer3 Counter
77
Register 7-17 TMR3PR - Timer3 Period
77
Register 7-18 TMR3PWM - Timer3 PWM Duty
78
Register 7-19 WDTCON - Watchdog Control
78
Watchdog Timer (WDT)
78
Independent Power Real Time Clock Counter (IRTCC)
79
Communication with IRTCC Timer
80
IRTCC Components Description
82
IRTCC Special Function Registers
87
Register 7-21 RTCDAT – RTCC Communication Data
88
IRTCC Operating Guide
89
8 Universal Asynchronous Receiver/Transmitter (UART)
91
Uart0
91
Register 10-2 UARTSTA – UART0 Status
92
Uart1
93
Register 10-7 UART1STA – UART1 Status
94
Register 10-9 UART1BAUD – UART1 Baud Rate Low
95
UART1 Operation Guide
96
Register 8-15 UART2STA – UART2 Status
97
Register 8-16 UART2DIV – UART2 Divide Register
98
Register 8-20 UART2DMATXPTR–UART2 DMA Transmit Start Pointer Byte
99
Operation Guide
100
9 Spi
102
Spi0
102
SPI0 Special Function Registers
103
SPI0 Operation Guide
104
Spi1
105
SPI1 Special Function Registers
106
Register 14-7 SPI1CON2 – SPI1 Configure Register 2
107
SPI1 Operation Guide
108
10 External Memory Interface (EMI)
109
Register 15-2 EMICON1 – EMI Control1
110
Register 15-2 EMICON3 – EMI Control3
111
Register 15-3 PWMBUF0/1/2/3/4/5/6/7 –Pwmbuffer0/1/2/3/4/5/6/7
112
11 Audio Terminal (DAC)
113
Function of DAC Control Registers
114
Register 17-4 DACSM - DAC Soft Mute Configuration Register
115
Register 17-7 DACVOLH– DAC Volume Setting High Byte Register
116
Register 17-10 TRIMCON2 - DAC Trim Control Register2
117
Operation Guide
118
12 Saradc
119
Register 19-2 ADCMODE– SARADC Mode Control
120
Register 19-4 ADCDATAL– SARADC Buffer Low Byte Control
121
13 Integrated Interchip Sound (IIS)
122
IIS Special Function Register
123
Register 22-2 IISCON1
124
Register 22-5 IISCH0: First Group of IIS Buffer
125
Operation Guide
126
IIS Operation Flow
127
LCD Driver
128
Position
130
LCD Function Control Registers
130
Register 23-2 LCD_CFG1 - LCD Configuration Control 1
131
Register 23-4 LCD_COM0L – Segment Data Low Byte for LCDCOM0
132
Access wo wo wo wo wo wo wo wo
133
Position
133
Name
133
Wo wo wo wo wo wo wo wo
133
Register 23-7 LCD_COM1H - Segment Data High Byte for LCDCOM1
133
Access wo wo wo wo wo wo wo wo
134
15 Characteristics
135
OSC Parameters
136
16 Package Dimensions
137
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