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DNPCIe 10G K7 LL QSFP
User Manuals: Applistar DNPCIe 10G K7 LL QSFP Card
Manuals and User Guides for Applistar DNPCIe 10G K7 LL QSFP Card. We have
1
Applistar DNPCIe 10G K7 LL QSFP Card manual available for free PDF download: User Manual
Applistar DNPCIe 10G K7 LL QSFP User Manual (62 pages)
DINI GROUP LOGIC Emulation Source
Brand:
Applistar
| Category:
PCI Card
| Size: 2 MB
Table of Contents
Table of Contents
4
Introduction
8
Dnpcie_10G_K7_Ll (_QSFP) Ethernet Packet Analysis Engine
8
Overview
8
FPGA - Xilinx, Kintex-7
8
Two Channels of 10 Gbe or Four Channels of 10 Gbe for the _QSFP Version
9
QDR II+ SSRAM - Memory with the Lowest Latency
9
DDR3 DRAM - Bulk Memory
9
PCI Express - Customizable 4-Lane, GEN2 PCI Express
10
Time Synchronization
10
How Everything Works
10
Dnpcie_10G_K7_Ll (_QSFP) Ethernet Packet Analysis Engine Features
11
Figure 1 - Dnpcie_10G_K7_Ll (_QSFP) Ethernet Packet Analysis Engine. (Upper Picture Is the Dnpcie_10G_K7_Ll and Lower Picture Is the Dnpcie_10G_K7_Ll_Qsfp)
11
Package Contents
13
Inspect the Board
13
Additional Information
14
Getting Started
15
Before You Begin
15
Configuring the Programmable Components
15
Warnings
15
Installing the Software
15
Exploring the Customer Support Package
16
Board Setup
16
Before Powering up the Board
16
Figure 2 - USB Flash Drive Directory Structure
16
Table 1 - USB Flash Drive Directory Contents
16
Cooling Requirements - IMPORTANT
17
Powering up the Board
17
Using the Reference Design (Main)
18
Programming/Configuring the Hardware
21
Introduction
21
Configuring the Fpga Using Jtag
22
Setup - Configuring the FPGA Using JTAG
22
Powering up the Board
22
Installing Digilent Cable Driver
22
Windows
22
Linux
23
Configuring the FPGA
24
Configuring the Fpga Using Master Bpi
25
Table 2 - Kintex-7 Uncompressed Bitstream Length
25
Configuring the FPGA
26
Powering up the Board
26
Setup - Configuring the FPGA Using Master BPI
26
Using Multiple FPGA "Boot" Images for Configuration Fallback
28
Using Chipscope Pro (Via JTAG)
29
Setup - Using Chipscope Pro (Via JTAG)
30
Powering up the Board
30
Configuring the FPGA
30
Hardware Description
32
Description
32
Overview
32
FPGA - Xilinx, Kintex-7
33
Two Channels of 10 Gbe or Four Channels of 10 Gbe for the _QSFP Version
33
Figure 3 - Dnpcie_10G_K7_Ll (_QSFP) Block Diagram - Note the Two SFP+ Modules Are Replaced with One QSFP+ Module in the _QSFP Version
33
QDR II+ SSRAM - Memory with the Lowest Latency
34
DDR3 DRAM - Bulk Memory
34
PCI Express - Customizable 4-Lane, GEN2 PCI Express
34
Time Synchronization
35
FPGA (Kintex-7)
35
FPGA Configuration
35
USB Port (RS232/JTAG)
35
RS232/JTAG Circuit Diagram
35
Connections between FPGA and the RS232 Port
36
QDR II+ SRAM Memory
36
Figure 4 -FPGA Serial Port
36
Table 3 - Connections between RS232 Port and the FPGA
36
Design Guidelines - QDR II+ SRAM IO Standards
37
Figure 5 - QDR II+ Memory Architecture
37
QDRII+ SRAM Memory Architecture
37
Table 4 - QDR II+ SRAM IO Standards
37
Connections between FPGA and QDR II+ SRAM Devices (4M X 18)
38
Table 5 - Connections between FPGA and the QDR II+ SRAM Devices
38
DDR3 Memory (VLP MINIUDIMM)
40
DDR3 SDRAM Memory Interface Solution
40
Design Guidelines - DDR3 Termination
41
Design Guidelines - DDR3 IO Standards
42
Serial Presence-Detect EEPROM Operation
42
Table 6 - Serial Presence-Detect EEPROM Connections
42
Clocking Connections between FPGA and MINIUDIMM
43
Connections between FPGA and MINIUDIMM
43
Table 7 - Clocking Connections between FPGA and the UDIMM Connector
43
Table 8 - Connections between FPGA and the UDIMM Connector
43
Eeprom
48
EEPROM Circuit Diagram
48
Connections between FPGA and the EEPROM
48
PCI Express Interface (X4)
48
Figure 6 -FPGA Serial Port
48
Table 9 - Connections between FPGA and the EEPROM
48
Clocking - Jitter Attenuator
49
Connections between FPGA and PCI Express Edge Connector
49
PCI Express Circuit
49
System Requirements
49
SFP+ Interface (Only for Dnpcie_10G_K7_Ll)
50
SFP+ Circuit Diagram
50
Table 10 - Connections between FPGA and the PCI Express Edge Connector
50
LED Indicators
51
Figure 7 - SFP+ Channel 0 Interface
51
Figure 8 - SFP+ GTX Oscillator
51
SFP+ Pin Assignments
52
Connections between FPGA and the SFP+ Connectors
52
Table 11 - SFP+ Pin Assignments
52
Table 12 - Connections between FPGA and the SFP+ Connectors
53
QSFP+ Interface (Only for the Dnpcie_10G_K7_Ll_Qsfp)
54
QSFP+ Circuit Diagram
54
Figure 9 - QSFP+ Channel 0 Interface
54
LED Indicators
55
QSFP+ Pin Assignments
55
Figure 10 - QSFP+ GTX Oscillator
55
Table 13 - QSFP+ Pin Assignments
55
Connections between FPGA and the QSFP+ Connectors
56
Table 14 - Connections between FPGA and the QSFP+ Connectors
56
Time Synchronization
58
Time Synchronization Circuit Diagram
58
Connections between the FPGA and Time Synchronization Circuitry
58
Clock Generation
59
System Clock - IDELAYCTRL
59
Connection between FPGA and the System Clock Oscillator
59
High-Speed (GTX) Clocks
59
Led Indicators
59
FPGA Status Leds
59
Table 15 - Connection between the FPGA and the System Clock Oscillator
59
Table 16 - FPGA Status Leds
59
Configuration DONE Leds
60
Power Distribution
60
In-System Operation
60
Mechanical
60
Board Dimensions
60
Table 17 - FPGA DONE LED
60
Appendix
62
Appendix A: Ucf File
62
Ordering Information
62
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