1. Manuals
  2. Brands
  3. Applistar Manuals
  4. PCI Card
  5. DNPCIe 10G K7 LL QSFP
  6. User manual

Applistar DNPCIe 10G K7 LL QSFP User Manual

Dini group logic emulation source
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
DINI GROUP
LOGIC Emulation Source
User Manual
DNPCIe_10G_K7_LL (_QSFP)

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the DNPCIe 10G K7 LL QSFP and is the answer not in the manual?

Questions and answers

Summary of Contents for Applistar DNPCIe 10G K7 LL QSFP

  • Page 1 DINI GROUP LOGIC Emulation Source User Manual DNPCIe_10G_K7_LL (_QSFP)
  • Page 2 L O G I C E M U L A T I O N S O U R C E DNPCIe_10G_K7_LL (_QSFP) User Manual Version Date of Print December 12, 2017  Dini Group 2012-2017 7469 Draper Ave. La Jolla, CA92037 Phone 858.454.3419 •...
  • Page 3 Copyright Notice and Proprietary Information Copyright © 2012-2017 Dini Group. All rights reserved. No part of this copyrighted work may be reproduced, modified or distributed in any form or by any means, without the prior written permission of the Dini Group. Right to Copy Documentation Dini Group permits licensee to make copies of the documentation for its internal use only.

  • Page 4: Table Of Contents

    T able of Contents INTRODUCTION ............................................1 DNPCI _10G_K7_LL (_QSFP) E ......................1 THERNET ACKET NALYSIS NGINE Overview............................................1 FPGA – Xilinx, Kintex-7 ....................................... 1 Two Channels of 10 GbE or Four Channels of 10 GbE for the _QSFP version ....................... 2 QDR II+ SSRAM - Memory with the Lowest Latency ..............................
  • Page 5 ........................................25 ESCRIPTION Overview............................................25 FPGA – Xilinx, Kintex-7 ......................................26 Two Channels of 10 GbE or Four Channels of 10 GbE for the _QSFP version ..................... 26 QDR II+ SSRAM - Memory with the Lowest Latency ............................... 27 DDR3 DRAM - Bulk Memory ..................................... 27 PCI Express –...
  • Page 6 List of Figures Figure 1 - DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine. (upper picture is the DNPCIe_10G_K7_LL and lower picture is the DNPCIe_10G_K7_LL_QSFP) ..........................................4 Figure 2 - USB Flash Drive Directory Structure...........................................9 Figure 3 - DNPCIe_10G_K7_LL (_QSFP) Block Diagram – Note the two SFP+ modules are replaced with one QSFP+ module in the _QSFP version ..26 Figure 4 –FPGA Serial Port................................................
  • Page 7 List of Tables Table 1 – USB Flash Drive Directory Contents ...........................................9 Table 2 – Kintex-7 Uncompressed Bitstream Length ......................................18 Table 3 - Connections between RS232 Port and the FPGA ....................................29 Table 4 – QDR II+ SRAM IO Standards ........................................... 30 Table 5 - Connections between FPGA and the QDR II+ SRAM Devices ................................

  • Page 8: Introduction

    Chapter I N T R O D U C T I O N Introduction This User Manual accompanies the DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine. For specific information regarding the Xilinx Kintex-7 parts, please reference the datasheet on the Xilinx website. 1 DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine 1.1 Overview...

  • Page 9: Two Channels Of 10 Gbe Or Four Channels Of 10 Gbe For The _Qsfp Version

    I N T R O D U C T I O N Either the XC7K325T or the XC7K410T FPGAs can be populated. Both come in three speeds grades, with -3 being the fastest. 1.3 Two Channels of 10 GbE or Four Channels of 10 GbE for the _QSFP version The Kintex-7 FPGAs have transceivers capable of 10 GbE.

  • Page 10: Pci Express - Customizable 4-Lane, Gen2 Pci Express

    I N T R O D U C T I O N utilized. As with the QDRII+ SRAM, the only real limitation is the amount of time and effort spent customizing the DDR3 memory controller to your needs. 1.6 PCI Express – Customizable 4-lane, GEN2 PCI Express PCI Express is connected directly to the FPGA via 4-lanes of GTX transceivers.

  • Page 11: Dnpcie_10G_K7_Ll (_Qsfp) Ethernet Packet Analysis Engine Features

    I N T R O D U C T I O N 2 DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine Features Figure 1 - DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine. (upper picture is the DNPCIe_10G_K7_LL and lower picture is the DNPCIe_10G_K7_LL_QSFP) DNPCIe_10G_K7_LL (_QSFP) Kintex-7 Board features the following: ...
  • Page 12 I N T R O D U C T I O N  Flexible Clock Resources o PCI Express Clock Jitter Attenuator – 250MHz o Oscillators for GTX Transceivers  Memory o Bulk Memory: DDR3 VLP MINIUDIMM (244-pin)  72-bit data width (64-bit with 8-bit ECC) ...

  • Page 13: Package Contents

    I N T R O D U C T I O N o PCIe Interface (4-lane, GEN2) o Memory o QDRII+ Controller o DDR3 Controller 3 Package Contents: Before using the kit or installing the software, be sure to check the contents of the kit and inspect the board to verify that you received all of the items.

  • Page 14: Additional Information

    I N T R O D U C T I O N 5 Additional Information For additional information, please visit http://www.dinigroup.com/. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource Description/URL User Manual...

  • Page 15: Getting Started

    Chapter G E T T I N G S T A R T E D Getting Started Congratulations on your purchase of the DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine. The remainder of this chapter describes how to start using the DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine.

  • Page 16: Exploring The Customer Support Package

    G E T T I N G S T A R T E D 2.1 Exploring the Customer Support Package The USB Flash Drive contains the following items, see Figure Documentation FPGA Reference Designs Host Software Figure 2 - USB Flash Drive Directory Structure A description of the USB Flash Drive directory contents is listed in Table 1.

  • Page 17: Cooling Requirements - Important

    G E T T I N G S T A R T E D 2. Plug board into x4, x8, or x16 PCIE slot. 3. Connect the “USB 2.0 Cable” to the USB-B connector on the bracket. Note: The DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine is shipped with a passive heat sink for operation in a server or PC with forced cooling.

  • Page 18: Using The Reference Design (Main)

    G E T T I N G S T A R T E D installation, please refer http://www.ftdichip.com/Support/Documents/InstallGuides.htm). 3. Once drivers are finished installing, open a Terminal Emulator and configure the session as follows: 4 Using the Reference Design (Main) This section lists detailed instructions for executing the reference design.
  • Page 19 G E T T I N G S T A R T E D 2. Select test option (0), “DDR3 Test (requires ECC module)” in the Terminal window and verify that the test PASS (periods will be displayed as the memory locations are being tested, if no DDR3 Module is present, the test will display read/write errors).
  • Page 20 G E T T I N G S T A R T E D The remainder of the reference design functional tests requires various loop-back test boards/modules to make them PASS, and is not covered in this User Manual. Please reference the Customer Support Package (on USB Flash Drive) for code examples.

  • Page 21: Programming/Configuring The Hardware

    Chapter P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E Programming/Configuring the Hardware This chapter details the programming and configuration instructions for the DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine.

  • Page 22: Configuring The Fpga Using Jtag

    P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E 2 Configuring the FPGA using JTAG This section lists detailed instructions for programming the Xilinx Kintex-7 FPGA using iMPACT, Version 14.7 tools.

  • Page 23: Linux

    P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E After restarting Vivado, the board should be visible when connecting to the hardware server.

  • Page 24: Configuring The Fpga

    P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E d. Unplug and replug the USB cable from the board, so that UDEV applies the newly installed Digilent rules.

  • Page 25: Configuring The Fpga Using Master Bpi

    P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E 5. Right-click on the FPGA and select the “Program” option. Click “OK” in the “Device Programming Properties”...

  • Page 26: Setup - Configuring The Fpga Using Master Bpi

    P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E Note: This User Manual will not be updated for every revision of the Xilinx ISE tools, so please be aware of minor differences.
  • Page 27 P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E A pop-up window will display “Device Programming Properties – Device 1 Programming Properties”.

  • Page 28: Using Multiple Fpga "Boot" Images For Configuration Fallback

    P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E 8. Power-cycle the board and verify that the “FPGA_DONE” blue LED (DS15) is enabled, indicating successful configuration of the FPGA from BPI PROM.

  • Page 29: Using Chipscope Pro (Via Jtag)

    P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E Following the Vivado build flow for the Darklite reference design a post-routing dcp file is saved under implement directory.

  • Page 30: Setup - Using Chipscope Pro (Via Jtag)

    P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E system at the speed of operation and brought out through the programming interface, freeing up pins for your design.
  • Page 31 P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E Note: In order for the JTAG offsets to be set correctly, set the IR Length for the QDR SRAMs to 3.

  • Page 32: Hardware Description

    Chapter H A R D W A R E D E S C R I P T I O N Hardware Description This chapter describes the hardware features of the DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine. 1 Description 1.1 Overview The DNPCIe_10G_K7_LL (_QSFP) is a PCI Expressed based FPGA board designed to minimize input to output processing latency on 10Gb/s Ethernet packets.

  • Page 33: Fpga - Xilinx, Kintex-7

    H A R D W A R E D E S C R I P T I O N Figure 3 - DNPCIe_10G_K7_LL (_QSFP) Block Diagram – Note the two SFP+ modules are replaced with one QSFP+ module in the _QSFP version 1.2 FPGA –...

  • Page 34: Qdr Ii+ Ssram - Memory With The Lowest Latency

    H A R D W A R E D E S C R I P T I O N DNPCIe_10G_K7_LL channels DNPCIe_10G_K7_LL_QSFP has four 10 GbE channel, and can support 10GBASET-ER, 10GBASET-SR, 10GBASET-KR. 1.4 QDR II+ SSRAM - Memory with the Lowest Latency One, quad data rate, static RAMs (QDR II+ SSRAM) is used in the 4M x 18 size.

  • Page 35: Time Synchronization

    H A R D W A R E D E S C R I P T I O N performance, while utilizing the minimum FPGA resources. 'C' source for drivers for several operating systems are included no charge. Partial reconfiguration of the FPGA is supported via the PCIe interface.

  • Page 36: Connections Between Fpga And The Rs232 Port

    H A R D W A R E D E S C R I P T I O N Figure 4 –FPGA Serial Port There are two signals attached to the FPGA for RS232 communication:  Transmit Data – USB_B_TXD ...

  • Page 37: Qdrii+ Sram Memory Architecture

    H A R D W A R E D E S C R I P T I O N transferred into and out of the device on every rising edge of both input clocks (K and Kn), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

  • Page 38: Connections Between Fpga And Qdr Ii+ Sram Devices (4M X 18)

    H A R D W A R E D E S C R I P T I O N Signal Name Direction IO Standard qdriip_r_n OUTPUT HSTL_I qdriip_sa OUTPUT HSTL_I qdriip_w_n OUTPUT HSTL_I 2.3.3 Connections between FPGA and QDR II+ SRAM Devices (4M x 18) Table 5 shows the connections between the FPGA and the QDR II+ SRAM device (U4).
  • Page 39 H A R D W A R E D E S C R I P T I O N Signal Name FPGA QRD II+ SRAM QDRIIP_DOFFn U6-K25 U4-H1 QDRIIP_K U6-V23 U4-B6 QDRIIP_Kn U6-V24 U4-A6 QDRIIP_Q0 U6-P19 U4-P11 QDRIIP_Q1 U6-N19 U4-M10 QDRIIP_Q2 U6-P20 U4-L11...

  • Page 40: Ddr3 Memory (Vlp Miniudimm)

    H A R D W A R E D E S C R I P T I O N Signal Name FPGA QRD II+ SRAM QDRIIP_SA7 U6-AB21 U4-N5 QDRIIP_SA8 U6-AB22 U4-N6 QDRIIP_SA9 U6-AD21 U4-N7 QDRIIP_SA10 U6-Y22 U4-P4 QDRIIP_SA11 U6-AA22 U4-P5 QDRIIP_SA12 U6-AC22 U4-P7...

  • Page 41: Design Guidelines - Ddr3 Termination

    H A R D W A R E D E S C R I P T I O N 2.4.2 Design Guidelines - DDR3 Termination These rules apply to termination for DDR3 SDRAM:  Unidirectional signals are to be terminated with the memory device’s internal termination or a pull-up of 40Ω...

  • Page 42: Design Guidelines - Ddr3 Io Standards

    H A R D W A R E D E S C R I P T I O N  The RESET and CKE signals are not terminated. These signals should be pulled down during memory initialization with a 4.7 kΩ resistor connected to GND.

  • Page 43: Clocking Connections Between Fpga And Miniudimm

    H A R D W A R E D E S C R I P T I O N DIMM_SDA U6-C14 J7-242, pull-up 4.7K (R324) 2.4.5 Clocking Connections between FPGA and MINIUDIMM The clocking connections between the FPGA and the MINIUDIMM connector are shown in Table Table 7 –...
  • Page 44 H A R D W A R E D E S C R I P T I O N Signal Name FPGA UDIMM DIMM_BA0 J7-72 U6-AE13 DIMM_BA1 J7-193 U6-Y12 DIMM_BA2 J7-53 U6-AD13 DIMM_CASN J7-75 U6-AF10 DIMM_CB0 J7-40 U6-V11 DIMM_CB1 J7-41 U6-W11 DIMM_CB2 J7-46...
  • Page 45 H A R D W A R E D E S C R I P T I O N Signal Name FPGA UDIMM DIMM_DQ5 J7-126 U6-AF15 DIMM_DQ6 J7-131 U6-AF14 DIMM_DQ7 J7-132 U6-AD15 DIMM_DQ8 J7-13 U6-AA18 DIMM_DQ9 J7-14 U6-AA17 DIMM_DQ10 J7-19 U6-AB15 DIMM_DQ11 J7-20...
  • Page 46 H A R D W A R E D E S C R I P T I O N Signal Name FPGA UDIMM DIMM_DQ37 J7-205 U6-V3 DIMM_DQ38 J7-210 U6-U1 DIMM_DQ39 J7-211 U6-U7 DIMM_DQ40 J7-92 U6-Y1 DIMM_DQ41 J7-93 U6-V2 DIMM_DQ42 J7-98 U6-AB2 DIMM_DQ43 J7-99...
  • Page 47 H A R D W A R E D E S C R I P T I O N Signal Name FPGA UDIMM DIMM_DQS2P J7-26 U6-AD20 DIMM_DQS3N J7-34 U6-W19 DIMM_DQS3P J7-35 U6-W18 DIMM_DQS4N J7-86 U6-W5 DIMM_DQS4P J7-87 U6-W6 DIMM_DQS5N J7-95 U6-AC1 DIMM_DQS5P J7-96...

  • Page 48: Eeprom

    H A R D W A R E D E S C R I P T I O N 2.5 EEPROM The AT24C256C (U26) provides 262,144-bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 32,768 words of eight bits each.

  • Page 49: System Requirements

    H A R D W A R E D E S C R I P T I O N integrated block follows the PCI Express Base Specification layering model, which consists of the Physical, Data Link, and Transaction layers. The integrated block is compliant with the PCI Express Base Specification, Rev.

  • Page 50: Sfp+ Interface (Only For Dnpcie_10G_K7_Ll)

    H A R D W A R E D E S C R I P T I O N Table 10 - Connections between FPGA and the PCI Express Edge Connector Signal Name FPGA PCI Express PCIE_TX_0p U9-R4 P1-B14 PCIE_TX_0n U9-R3 P1-B15 PCIE_TX_1p...

  • Page 51: Led Indicators

    H A R D W A R E D E S C R I P T I O N Figure 7 - SFP+ Channel 0 Interface Fixed frequency, 156.25 MHz LVPECL oscillator (X5), is used to clock the GTX transceivers, see Figure 8.

  • Page 52: Sfp+ Pin Assignments

    H A R D W A R E D E S C R I P T I O N 2.7.3 SFP+ Pin Assignments The SFP+ pin assignments are listed in Table 11. Table 11 – SFP+ Pin Assignments Symbol Description Logic Number Family...

  • Page 53: Table 12 - Connections Between Fpga And The Sfp+ Connectors

    H A R D W A R E D E S C R I P T I O N Table 12 - Connections between FPGA and the SFP+ Connectors Signal Name FPGA SFP+ Connector SFP+ Clocks SFP0_REFCLKP U6-D6 X5-4 SFP0_REFCLKN U6-D5 X5-5 SFP+ Channel 0...

  • Page 54: Qsfp+ Interface (Only For The Dnpcie_10G_K7_Ll_Qsfp)

    H A R D W A R E D E S C R I P T I O N 2.8 QSFP+ Interface (only for the DNPCIe_10G_K7_LL_QSFP) The 40GBASE QSFP+ modules offer customers a wide variety of 40 Gigabit Ethernet connectivity options for data center, enterprise wiring closet, and service provider transport applications.

  • Page 55: Led Indicators

    H A R D W A R E D E S C R I P T I O N Figure 10 – QSFP+ GTX Oscillator 2.8.2 LED indicators There are two separate LEDs that connect to the ‘light pipes’ that display on the bracket.

  • Page 56: Connections Between Fpga And The Qsfp+ Connectors

    H A R D W A R E D E S C R I P T I O N Pin Number Symbol Description Logic Family Rx3n Receiver Inverted Data Output CML-O Ground Rx1p Receiver Non-Inverted Data Output CML-O Rx1n Receiver Inverted Data Output CML-O Ground Ground...
  • Page 57 H A R D W A R E D E S C R I P T I O N Signal Name FPGA QSFP+ Connector QSFP_TX1p U6-F1* J11-36 QSFP_TX1n U6-F2* J11-37 QSFP_RX2p U6-E4 J11-22 QSFP_RX2n U6-E3 J11-21 QSFP_TX2p U6-D1* J11-3 QSFP_TX2n U6-D2* J11-2 QSFP_RX3p...

  • Page 58: Time Synchronization

    H A R D W A R E D E S C R I P T I O N 2.9 Time Synchronization 2.9.1 Time Synchronization Circuit Diagram Depending on the time code input, U2/U3 can be configured to accept signals including PPS, and IRIG-B000 (RS232, RS485, RS422, TTL).

  • Page 59: Clock Generation

    H A R D W A R E D E S C R I P T I O N 3 Clock Generation 3.1 System Clock – IDELAYCTRL Either X3 or X2 can be used as the IDELAYCTRL system clock. The IDELAYCTRL module must be instantiated when using the tap-delay line.

  • Page 60: Configuration Done Leds

    H A R D W A R E D E S C R I P T I O N Signal Name FPGA LED5 U6-B15 DS22 LED6 U6-A15 DS23 LED7 U6-A13 DS24 LED8 U6-A12 DS25 4.2 Configuration DONE LEDs After the FPGA has received all the configuration data successfully, it releases the DONE pin, which is pulled high by a pull-up resistor.
  • Page 61 H A R D W A R E D E S C R I P T I O N The mounting holes are connected to the ground plane and can be used to ground test equipment. DNPCIe_10G_K7_LL (_QSFP) User Manual www.dinigroup.com...

  • Page 62: Appendix

    Chapter A P P E N D I X Appendix 1 Appendix A: UCF File See the Customer Support Package (USB Flash Drive) for the Xilinx User Constraint Files (UCF). 2 Ordering Information Request quotes by emailing sales@dinigroup.com. For technical questions email support@dinigroup.com DNPCIe_10G_K7_LL (_QSFP) User Manual www.dinigroup.com...

Table of Contents