Sign In
Upload
Manuals
Brands
Altera Manuals
Control Unit
EP3SL340
Altera EP3SL340 Manuals
Manuals and User Guides for Altera EP3SL340. We have
1
Altera EP3SL340 manual available for free PDF download: Device Handbook
Altera EP3SL340 Device Handbook (456 pages)
Volume 1
Brand:
Altera
| Category:
Control Unit
| Size: 8.76 MB
Table of Contents
Table of Contents
3
List of Figures
15
Additional Information
25
How to Contact Altera
25
Typographic Conventions
25
Chapter I. Device Core
27
Revision History
27
Chapter 1. Stratix III Device Family Overview Features Summary
31
Table 1-1: FPGA Family Features for Stratix III Devices
31
Table 1-2: Package Options and I/O Pin Counts (Note 1)
32
Table 1-3: Fineline BGA Package Sizes
32
Table 1-4: Hybrid Fineline BGA Package Sizes
33
Table 1-5: Speed Grades for Stratix III Devices
33
Architecture Features
34
Logic Array Blocks and Adaptive Logic Modules
34
DSP Blocks
35
Multitrack Interconnect
35
Trimatrix Embedded Memory Blocks
35
Clock Networks and Plls
36
External Memory Interfaces
37
High-Speed Differential I/O Interfaces with DPA
37
I/O Banks and I/O Structure
37
Configuration
38
Hot Socketing and Power-On Reset
38
Design Security
39
IEEE 1149.1 (JTAG) Boundary-Scan Testing
39
Remote System Upgrades
39
Programmable Power
40
SEU Mitigation
40
Reference and Ordering Information
41
Signal Integrity
41
Software Support
41
Chapter Revision History
42
Figure 1-1: Stratix III Device Packaging Ordering Information
42
Ordering Information
42
Table 4-10: Chapter Revision History
42
Chapter 2 .Logic Array Blocks and Adaptive Logic Modules in Stratixiii Devices
45
Introduction
45
Logic Array Blocks
45
Figure 2-1: Stratix III LAB Structure
46
Figure 2-2: Stratix III LAB and MLAB Structure
47
LAB Interconnects
47
Figure 2-3: Direct Link Connection
48
LAB Control Signals
48
Adaptive Logic Modules
49
Figure 2-4: LAB-Wide Control Signals
49
Figure 2-5: High-Level Block Diagram of the Stratix III ALM
50
Figure 2-6: Stratix III ALM Details
51
ALM Operating Modes
52
Normal Mode
52
Figure 2-7: ALM in Normal Mode (Note 1)
53
Figure 2-8: 4 × 2 Crossbar Switch Example
54
Arithmetic Mode
55
Extended LUT Mode
55
Figure 2-10: Template for Supported Seven-Input Functions in Extended LUT Mode
55
Figure 2-9: Input Function in Normal Mode (Note 1)
55
Figure 2-11: ALM in Arithmetic Mode
56
Figure 2-12: Conditional Operation Example
57
Carry Chain
58
Shared Arithmetic Mode
58
Figure 2-13: ALM in Shared Arithmetic Mode
59
Figure 2-14: Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
60
Shared Arithmetic Chain
60
Figure 2-15: LUT Register from Two Combinational Blocks
61
LUT-Register Mode
61
Figure 2-16: ALM in LUT-Register Mode with 3-Register Capability
62
Register Chain
62
Figure 2-17: Register Chain Within an LAB
63
ALM Interconnects
64
Clear and Preset Logic Control
64
Figure 2-18: Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
64
LAB Power Management Techniques
65
Chapter Revision History
65
Conclusion
65
Table 2-1: Chapter Revision History
65
Chapter 3 .Multitrack Interconnect in Stratixiii Devices
67
Introduction
67
Row Interconnects
67
Column Interconnects
68
Figure 3-1: R4 Interconnect Connections
68
Figure 3-2: Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
69
Figure 3-3: C4 Interconnect Connections (Note 1)
70
Table 3-1: Stratix III Device Routing Scheme
71
Memory Block Interface
72
Table 3-2: Number of Labs Reachable Using C4 and R4 Interconnects
72
Figure 3-4: MLAB RAM Block LAB Row Interface
73
Figure 3-5: M9K RAM Block LAB Row Interface
74
DSP Block Interface
75
Figure 3-6: M144K Row Unit Interface to Interconnect
75
Figure 3-7: High-Level View, DSP Block Interface to Interconnect
76
Figure 3-8: Detailed View, DSP Block Interface to Interconnect
77
I/O Block Connections to Interconnect
77
Figure 3-9: Row I/O Block Connection to Interconnect
78
Conclusion
79
Figure 3-10: Column I/O Block Connection to Interconnect
79
Chapter Revision History
80
Table 3-3: Chapter Revision History
80
Chapter 4 .Trimatrix Embedded Memory Blocks in Stratixiii Devices
81
Introduction
81
Table 4-1: Summary of Trimatrix Memory Features
81
Overview
82
Byte-Enable Support
83
Parity Bit Support
83
Table 4-2: Trimatrix Memory Capacity and Distribution in Stratix III Devices
83
Trimatrix Memory Block Types
83
Figure 4-1: Stratix III Byte-Enable Functional Waveform for M9K and M144K
84
Address Clock Enable Support
85
Figure 4-2: Stratix III Byte-Enable Functional Waveform for Mlabs
85
Packed Mode Support
85
Figure 4-3: Stratix III Address Clock Enable Block Diagram
86
Figure 4-4: Stratix III Address Clock Enable During Read Cycle Waveform
86
Figure 4-5: Stratix III Address Clock Enable During Write Cycle Waveform for M9K and M144K
87
Asynchronous Clear
88
Figure 4-6: Stratix III Address Clock Enable During Write Cycle Waveform for Mlabs
88
Mixed Width Support
88
Error Correction Code Support
89
Figure 4-7: Output Latch Asynchronous Clear Waveform
89
Table 4-3: Truth Table for ECC Status Flags
89
Figure 4-8: ECC Block Diagram of the M144K
90
Single Port RAM
90
Figure 4-9: Single-Port Memory (Note 1)
91
Table 4-4: Stratix III Port Width Configurations for Mlabs, M9K Blocks, and M144K Blocks
91
Figure 4-10: Timing Waveform for Read-Write Operations (Single-Port Mode) for M9K and M144K
92
Figure 4-11: Timing Waveform for Read-Write Operations (Single-Port Mode) for Mlabs
92
Simple Dual-Port Mode
92
Figure 4-12: Stratix III Simple Dual-Port Memory
93
Table 4-5: Stratix III M9K Block Mixed-Width Configurations (Simple Dual-Port Mode)
93
Table 4-6: Stratix III M144K Block Mixed-Width Configurations (Simple Dual-Port Mode)
93
Figure 4-13: Stratix III Simple Dual-Port Timing Waveforms for M9K and M144K
94
Figure 4-14: Stratix III Simple Dual-Port Timing Waveforms for Mlabs
94
Figure 4-15: Stratix III True Dual-Port Memory
95
Table 4-7: Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode)
95
True Dual-Port Mode
95
Table 4-8: Stratix III M144K Block Mixed-Width Configurations (True Dual-Port Mode)
96
Figure 4-16: Stratix III True Dual-Port Timing Waveform
97
Shift-Register Mode
97
FIFO Mode
98
Figure 4-17: Stratix III Shift-Register Memory Configuration
98
ROM Mode
98
Clocking Modes
99
Independent Clock Mode
99
Input/Output Clock Mode
99
Table 4-9: Stratix III Trimatrix Memory Clock Modes
99
Read/Write Clock Mode
100
Single Clock Mode
100
Design Considerations
100
Conflict Resolution
100
Selecting Trimatrix Memory Blocks
100
Figure 4-18: Stratix III Read-During-Write Data Flow
101
Read During Write
101
Same-Port Read-During-Write Mode
101
Figure 4-19: same Port Read-During-Write: New Data Mode (Note 1)
102
Figure 4-20: same Port Read-During-Write: Old Data Mode (Note 1)
102
Mixed-Port Read-During-Write Mode
102
Figure 4-21: Mixed Port Read During Write: Old Data Mode (Note 1)
103
Power-Up Conditions and Memory Initialization
103
Power Management
104
Programming File Compatibility
104
Conclusion
104
Chapter Revision History
105
Table 1-6: Chapter Revision History
105
Chapter 5. DSP Blocks in Stratix III Devices
107
Introduction
107
DSP Block Overview
107
Table 5-1: Number of DSP Blocks in Stratix III Devices
108
Simplified DSP Operation
109
Figure 5-1: Overview of DSP Block Signals
109
Figure 5-2: Basic Two-Multiplier Adder Building Block
109
Figure 5-3: Four-Multiplier Adder and Accumulation Capability
111
Figure 5-4: Output Cascading Feature for FIR Structures
112
Figure 5-5: Stratix III Full DSP Block Summary
113
Operational Modes Overview
114
Table 5-2: Stratix III DSP Block Operation Modes
114
DSP Block Resource Descriptions
115
Figure 5-6: Half-DSP Block Architecture
115
Input Registers
116
Figure 5-7: Input Register of Half-DSP Block
117
Multiplier and First-Stage Adder
118
Table 5-3: Input Register Modes
118
Table 5-4: Multiplier Sign Representation
118
Pipeline Register Stage
119
Second-Stage Adder
119
Round and Saturation Stage
120
Second Adder and Output Registers
120
Operational Mode Descriptions
121
12-, and 18-Bit Multiplier
121
Figure 5-8: 18-Bit Independent Multiplier Mode for Half-DSP Block
121
Independent Multiplier Modes
121
Figure 5-9: 12-Bit Independent Multiplier Mode for Half-DSP Block
122
Figure 5-10: 9-Bit Independent Multiplier Mode for Half-Block
123
36-Bit Multiplier
124
Figure 5-11: 36-Bit Independent Multiplier Mode for Half-DSP Block
124
Double Multiplier
125
Figure 5-12: Double Mode for Half-DSP Block
125
Figure 5-13: Unsigned 54 × 54 Multiplier
126
Two-Multiplier Adder Sum Mode
127
Figure 5-14: Two-Multiplier Adder Mode for Half-DSP Block
128
Figure 5-15: Loopback Mode for Half-DSP Block
129
18 × 18 Complex Multiply
130
Figure 5-16: Complex Multiplier Using Two-Multiplier Adder Mode
130
Figure 5-17: Four-Multiplier Adder Mode for Half-DSP Block
131
Four-Multiplier Adder
131
High Precision Multiplier Adder
132
Figure 5-18: Four-Multiplier Adder Mode for Half-DSP Block
133
Figure 5-19: Multiply Accumulate Mode for Half-DSP Block
134
Multiply Accumulate Mode
134
Shift Modes
135
Figure 5-20: Shift Operation Mode for Half-DSP Block
136
Rounding and Saturation Mode
137
Table 5-5: Examples of Shift Operations (Note 1)
137
Table 5-6: Example of Round-To-Nearest-Even Mode
137
Table 5-7: Comparison of Round-To-Nearest-Integer and Round-To-Nearest-Even
138
Table 5-8: Examples of Saturation
138
Figure 5-21: Round and Saturation Locations
139
DSP Block Control Signals
140
Application Examples
141
FIR Example
141
Table 5-10: DSP Block Dynamic Signals
141
Figure 5-22: FIR Filter Using Tap-Delay Line Input and Tree Summation of Final Result
143
Figure 5-23: FIR Filter Using Tap-Delay Line Input and Chained Cascade Summation of Final Result
144
Figure 5-24: Semi-Parallel FIR Structure Using Chained Cascaded Summation
146
Software Support
147
Figure 5-25: Radix-4 Butterfly
147
Chapter Revision History
148
Table 5-10: Document Revision History
148
Table 6-1: Clock Resources in Stratix III Devices
149
Clock Networks in Stratix III Devices
150
Figure 6-1: Global Clock Networks
150
Global Clock Networks
150
Figure 6-2: Regional Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices)
151
Figure 6-3: Regional Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices)
151
Regional Clock Networks
151
Figure 6-4: Regional Clock Networks (EP3SL200, EP3SE260, and EP3SL340 Devices)
152
Figure 6-5: Periphery Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices)
152
Periphery Clock Networks
152
Figure 6-6: Periphery Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices)
153
Figure 6-7: Periphery Clock Networks (EP3SL200 Devices)
153
Clocking Regions
154
Figure 6-8: Periphery Clock Networks (EP3SE260 Devices)
154
Figure 6-9: Periphery Clock Networks (EP3SL340 Devices)
154
Clock Network Sources
155
Figure 6-10: Stratix III Dual-Regional Clock Region
155
Table 6-2: Clock Input Pin Connectivity to Global Clock Networks
156
Table 6-3: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 1)
157
Table 6-4: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 2)
157
Table 6-6: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 4)
159
Table 6-7: Stratix III Device Plls and PLL Clock Pin Drivers
159
Clock Output Connections
160
Table 6-8: PLL Connectivity to Gclks on Stratix III Devices
160
Clock Source Control for Plls
161
Table 6-9: Regional Clock Outputs from Plls on Stratix III Devices (Note 1)
161
Clock Control Block
162
Figure 6-11: Clock Input Multiplexer Logic for L2, L3, T1, T2, B1, B2, R2, and R3 Plls
162
Figure 6-12: Clock Input Multiplexer Logic for L1, L4, R1, and R4 Plls
162
Figure 6-13: Stratix III Global Clock Control Block
163
Figure 6-14: Regional Clock Control Block
163
Figure 6-15: Stratix III External PLL Output Clock Control Block
164
Clock Enable Signals
165
Figure 6-16: Clkena Implementation
165
Figure 6-17: Clkena Signals
165
Chapter 6 Plls in Stratix III Devices
166
Table 6-10: Stratix III Device PLL Availability
166
Table 6-11: Stratix III PLL Features
167
Figure 6-18: Stratix III PLL Locations
168
Stratix III PLL Hardware Overview
168
Figure 6-19: Stratix III PLL Block Diagram
169
PLL Clock I/O Pins
169
Figure 6-20: External Clock Outputs for Top/Bottom Plls
170
Figure 6-21: External Clock Outputs for Left/Right Plls
171
Figure 6-22: Stratix III PLL Ports
172
Stratix III PLL Software Overview
172
Table 6-12: PLL Input Signals
172
Table 6-13: PLL Output Signals
173
Clock Feedback Modes
174
Table 6-14: Clock Feedback Mode Availability
174
Figure 6-23: Phase Relationship between Clock and Data in Source-Synchronous Mode
175
Figure 6-24: Phase Relationship between Clock and Data LVDS Modes
175
Source Synchronous Mode
175
Figure 6-25: Phase Relationship between PLL Clocks in no Compensation Mode
176
No-Compensation Mode
176
Normal Mode
176
Source-Synchronous Mode for LVDS Compensation
176
Figure 6-26: Phase Relationship between PLL Clocks in Normal Mode
177
Figure 6-27: Zero-Delay Buffer Mode in Stratix III Plls
177
Zero-Delay Buffer Mode
177
External Feedback Mode
178
Figure 6-28: Phase Relationship between PLL Clocks in Zero Delay Buffer Mode
178
Figure 6-29: External Feedback Mode in Stratix III Devices
178
Clock Multiplication and Division
179
Figure 6-30: Phase Relationship between PLL Clocks in External-Feedback Mode
179
Figure 6-31: Counter Cascading
180
Post-Scale Counter Cascading
180
Programmable Duty Cycle
180
Areset
181
Clock Switchover
181
Locked
181
Pfdena
181
PLL Control Signals
181
Automatic Clock Switchover
182
Figure 6-32: Automatic Clock Switchover Circuit Block Diagram
182
Figure 6-33: Automatic Switchover Upon Loss of Clock Detection
183
Figure 6-34: Clock Switchover Using the Clkswitch (Manual) Control
184
Figure 6-35: Manual Clock Switchover Circuitry in Stratix III Plls
185
Guidelines
185
Manual Clock Switchover
185
Figure 6-36: VCO Switchover Operating Frequency
186
Background
187
Figure 6-37: Open- and Closed-Loop Response Bode Plots
187
Programmable Bandwidth
187
Figure 6-38: Loop Filter Programmable Components
188
Implementation
188
Phase-Shift Implementation
189
Figure 6-39: Delay Insertion Using VCO Phase Output and Counter Delay Time
190
PLL Reconfiguration
190
Figure 6-40: PLL Reconfiguration Scan Chain
191
PLL Reconfiguration Hardware Implementation
191
Table 6-15: Real-Time PLL Reconfiguration Ports
192
Figure 6-41: PLL Reconfiguration Waveform
193
Post-Scale Counters (C0 to C9)
193
Scan Chain Description
194
Table 6-16: Top/Bottom PLL Reprogramming Bits
194
Figure 6-42: Scan-Chain Order of PLL Components for Top/Bottom Plls (Note 1)
195
Figure 6-43: Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix III Plls
195
Charge Pump and Loop Filter
196
Table 6-17: Charge_Pump_Current Bit Settings
196
Table 6-18: Loop_Filter_R Bit Settings
196
Table 6-19: Loop_Filter_C Bit Settings
196
Bypassing PLL
197
Dynamic Phase-Shifting
197
Table 6-20: PLL Counter Settings
197
Table 6-21: Dynamic Phase-Shifting Control Signals
197
Table 6-22: Phase Counter Select Mapping
198
Figure 6-44: Dynamic Phase Shifting Waveform
199
PLL Cascading and Clock Network Guidelines
200
PLL Specifications
200
Spread-Spectrum Tracking
200
Chapter Revision History
201
Table 6-23: Chapter Revision History
201
Chapter II. I/O Interfaces
203
Revision History
203
Chapter 7. Stratix III Device I/O Features
205
Stratix III I/O Standards Support
206
Table 7-1: I/O Standard Applications for Stratix III Devices
206
I/O Standards and Voltage Levels
207
Table 7-2: I/O Standards and Voltage Levels for Stratix III Devices
208
Stratix III I/O Banks
209
Figure 7-1: I/O Banks for Stratix III Devices
210
Modular I/O Banks
211
Table 7-3: Bank Migration Path with Increasing Device Size (Note 1)
211
Figure 7-3: Number of I/Os in each Bank in the 780-Pin Fineline BGA Package
213
Figure 7-4: Number of I/Os in each Bank in the 1152-Pin Fineline BGA Package
214
Figure 7-5: Number of I/Os in each Bank in EP2SL200, EP3SE260, and EP3SL340 Devices in the 1517-Pin Fineline BGA Package (Note 1)
215
Stratix III I/O Structure
216
Figure 7-6: Number of I/Os in each Bank in EP3SL340 Devices in the 1760-Pin Fineline BGA Package
216
Figure 7-7: IOE Structure for Stratix III Devices
217
Figure 9-10: Programmable
217
3.3-V I/O Interface
218
Chapter 8 External Memory Interfaces
218
Table 7-4: Memory Interface Standards Supported
218
High-Speed Differential I/O with DPA Support
219
Programmable Current Strength
219
Programmable Slew Rate Control
220
Table 7-5: Programmable Current Strength (Note 1)
220
Programmable Delay
221
Programmable Output Buffer Delay
221
Open-Drain Output
221
Table 7-6: Default Programmable Slew Rate
221
Bus Hold
222
Programmable Pull-Up Resistor
222
Programmable Pre-Emphasis
222
Programmable Differential Output Voltage
223
Multivolt I/O Interface
223
Table 7-7: Multivolt I/O Support for Stratix III Devices
223
OCT Support
224
On-Chip Series Termination Without Calibration
224
Figure 7-8: On-Chip Series Termination Without Calibration for Stratix III Devices
225
Figure 7-9: On-Chip Series Termination with Calibration for Stratix III Devices
225
On-Chip Series Termination with Calibration
225
Expanded On-Chip Series Termination with Calibration
226
Table 7-8: Selectable I/O Standards with On-Chip Series Termination with or Without Calibration
226
Left Shift Series Termination Control
227
Table 7-9: Selectable I/O Standards with Expanded On-Chip Series Termination with Calibration Range
227
Figure 7-10: On-Chip Parallel Termination with Calibration for Stratix III Devices
228
On-Chip Parallel Termination with Calibration
228
Table 7-10: Selectable I/O Standards that Support On-Chip Parallel Termination with Calibration
228
Dynamic OCT
229
Figure 7-11: Dynamic Parallel OCT in Stratix III Devices
229
Figure 7-12: Differential Input On-Chip Termination
230
LVDS Input On-Chip Termination
230
Table 7-11: On-Chip Differential Termination in Quartus II Software Assignment Editor
230
OCT Calibration
231
Figure 7-13: OCT Calibration Block (CB) Location in EP3SL50, EP3SL70, and EP3SE50 Devices
231
OCT Calibration Block Location
231
Figure 7-14: OCT Calibration Block (CB) Location in EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices
232
Figure 7-15: OCT Calibration Block (CB) Location in EP3SL200, EP3SE260 and EP3SL340
232
Figure 7-16: Example of Sharing Multiple I/O Banks with One OCT Calibration Block (Note 1)
233
OCT Calibration Block Modes of Operation
233
Power-Up Mode
233
Sharing an OCT Calibration Block in Multiple I/O Banks
233
Figure 7-17: Signals Used for User Mode Calibration (Note 1)
234
Table 7-12: OCT Calibration Block Ports for User Control and Description
234
User Mode
234
Example of Using Multiple OCT Calibration Blocks
235
Figure 7-18: OCT User-Mode Signal Timing Waveform for One OCT Block
235
OCT Calibration
235
Serial Data Transfer
235
RS Calibration
236
Termination Schemes for I/O Standards
236
Figure 7-19: OCT User-Mode Signal Timing Waveform for Two OCT Blocks
236
Single-Ended I/O Standards Termination
236
Figure 7-20: SSTL I/O Standard Termination for Stratix III Devices
237
Differential I/O Standards Termination
238
Figure 7-21: HSTL I/O Standard Termination for Stratix III Devices
238
Figure 7-22: Differential SSTL I/O Standard Termination for Stratix III Devices
239
Figure 7-23: Differential HSTL I/O Standard Termination for Stratix III Devices
239
Figure 7-24: LVDS I/O Standard Termination for Stratix III Devices (Note 1)
240
Lvds
240
Differential LVPECL
241
Figure 7-25: LVPECL AC Coupled Termination (Note 1)
241
Figure 7-26: LVPECL DC Coupled Termination (Note 1)
241
Rsds
241
Figure 7-27: RSDS I/O Standard Termination for Stratix III Devices
242
Mini-LVDS
242
Design Considerations
243
Figure 7-28: Mini-LVDS I/O Standard Termination for Stratix III Devices
243
Differential I/O Standards
244
I/O Banks Restrictions
244
I/O Termination
244
Non-Voltage-Referenced Standards
244
Single-Ended I/O Standards
244
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
245
Voltage-Referenced Standards
245
Chapter Revision History
246
Table 7-13: Chapter Revision History
246
Figure 8-1: Package Bottom View for Stratix III Devices
250
Memory Interfaces Pin Support
251
Figure 8-2: External Memory Interface Data Path Overview
251
Data and Data-Strobe/Clock Pins
252
Table 8-1: DQS and DQ Bus Mode Pins for Stratix III Devices
253
Using RUP /RDN Pins in a DQS/DQ Group Used for Memory Interfaces
253
Table 8-2: Number of DQS/DQ Groups in Stratix III Devices Per Side
254
Figure 8-3: Number of DQS/DQ Groups Per Bank in EP3SE50, EP3SL50, and EP3SL70 Devices in the 484-Pin Fineline BGA Package (Note 1)
256
Figure 8-4: Number of DQS/DQ Groups Per Bank in EP3SE50, EP3SL50, EP3SL70, EP3SE80, EP3SE110
257
Figure 8-5: Number of DQS/DQ Groups in EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200
258
Figure 8-6: Number of DQS/DQ Groups Per Bank in EP3SL200, EP3SE260 and EP3SL340 Devices in the
259
Figure 8-7: DQS/DQ Bus Mode Support Per Bank in EP3SL340 Devices in the 1760-Pin Fineline BGA Pack
260
Figure 8-8: DQS Pins in Stratix III I/O Banks
262
Combining ×16/×18 DQS/DQ Groups for ×36 QDR II+/QDR II SRAM Interface
263
Rules to Combine Groups
263
Table 8-3: DQ/DQS Group in Stratix III Modular I/O Banks
263
Table 8-4: I/O Sub-Bank Combinations for Stratix III Devices that Do Not Have ×36 Groups to Form Two ×36
264
Address and Control/Command Pins
265
Optional Parity, DM, Bwsn, Nwsn, ECC and QVLD Pins
265
Memory Clock Pins
266
Stratix III External Memory Interface Features
266
Figure 8-9: Memory Clock Generation Block Diagram (Note 1)
266
DQS Phase-Shift Circuitry
267
Figure 8-10: DQS and Cqn Pins and DQS Phase-Shift Circuitry (Note 1)
268
Dll
269
Figure 8-11: Stratix III DLL and I/O Bank Locations (Package Bottom View)
270
Table 8-5: DLL Location and Supported I/O Banks
271
Table 8-6: DLL Reference Clock Input for EP3SE50, EP3SL50, and EP3SL70 Devices
271
Table 8-7: DLL Reference Clock Input for EP3SE80, EP3SE110, and EP3SL150 Devices in the 780-Pin Pack
272
Table 8-8: DLL Reference Clock Input for EP3SE80, EP3SE110, EP3SL110, and EP3SL150 Devices in the
272
Table 8-9: DLL Reference Clock Input for EP3SL200, EP3SE260 and EP3SL340 Devices
273
Figure 8-12: Simplified Diagram of the DQS Phase Shift Circuitry (Note 1)
274
Phase Offset Control
275
Table 8-10: Stratix III DLL Frequency Modes
275
DQS Delay Chain
277
DQS Logic Block
277
Figure 8-13: Stratix III DQS Logic Block
277
DQS Postamble Circuitry
278
Figure 8-14: Example of a DQS Update Enable Waveform
278
Update Enable Circuitry
278
Figure 8-15: Avoiding a Glitch on a Non-Consecutive Read Burst Waveform
279
Leveling Circuitry
279
Figure 8-16: DDR3 SDRAM Unbuffered Module Clock Topology
280
Figure 8-17: Stratix III Write Leveling Delay Chains and Multiplexers (Note 1)
280
Dynamic OCT Control
281
Figure 8-18: Stratix III Read Leveling Delay Chains and Multiplexers (Note 1)
281
Figure 8-19: Stratix III Dynamic OCT Control Block
282
IOE Registers
282
Figure 8-20: Stratix III IOE Input Registers (Note 1)
283
Figure 8-21: Stratix III IOE Output and Output-Enable Path Registers (Note 1)
286
Delay Chain
287
Figure 8-22: Delay Chain
288
Figure 8-23: Delay Chains in an I/O Block
288
Figure 8-24: Delay Chains in the DQS Input Path
288
Figure 8-25: I/O Configuration Block and DQS Configuration Block
289
I/O Configuration Block and DQS Configuration Block
289
Table 8-11: I/O Configuration Block Bit Sequence
289
IOE Features
290
Table 8-12: DQS Configuration Block Bit Sequence
290
Oct
291
Programmable IOE Delay Chains
291
Programmable Output Buffer Delay
291
Pll
292
Programmable Drive Strength
292
Programmable Slew Rate Control
292
Chapter Revision History
293
Table 8-13: Chapter Revision History
293
Chapter 9 .High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
296
I/O Banks
296
Figure 9-1: I/O Banks in Stratix III Devices
296
LVDS Channels
297
Table 9-1: LVDS Channels Supported in Stratix III Device Side I/O Banks
297
Differential Transmitter
298
Table 9-2: LVDS Channels (Emulated) Supported in Stratix III Device Column I/O Banks
298
Figure 9-2: Transmitter Block Diagram for Stratix III Devices
299
Figure 9-3: Transmitter in Clock Output Mode for Stratix III Devices
299
Differential Receiver
300
Figure 9-4: Serializer Bypass for Stratix III Devices
300
Figure 9-5: Receiver Block Diagram for Stratix III Devices
301
Figure 9-6: Deserializer Bypass for Stratix III Devices
301
Receiver Data Realignment Circuit (Bit Slip)
301
Dynamic Phase Aligner (DPA)
302
Figure 9-7: Data Realignment Timing
302
Figure 9-8: DPA Clock Phase-To-Serial Data Timing Relationship
302
Soft-CDR Mode
303
Figure 9-9: Soft-CDR Data and Clock Path for a Stratix III Devices
304
Synchronizer
304
Programmable Pre-Emphasis and Programmable V
305
Differential I/O Termination
306
Left/Right Plls (Pll_Lx/ Pll_Rx)
306
Figure 9-11: On-Chip Differential I/O Termination for Stratix III Devices
306
Figure 9-12: PLL Block Diagram for Stratix III Devices
307
Clocking
308
Figure 9-13: LVDS/DPA Clocks with Center Plls for Stratix III Devices
308
Figure 9-14: LVDS/DPA Clocks with Center and Corner Plls for Stratix III Devices
308
Differential Data Orientation
309
Differential I/O Bit Position
309
Figure 9-15: Bit Orientation in Quartus II Software
309
Source-Synchronous Timing Budget
309
Figure 9-16: Bit-Order and Word Boundary for One Differential Channel (Note 1)
310
Table 9-3: Differential Bit Naming
310
Receiver Skew Margin for Non-DPA
311
Figure 9-17: Differential High-Speed Timing Diagram and Timing Budget for Non-DPA
312
Differential Pin Placement Guidelines
313
DPA-Enabled Channel Driving Distance
313
DPA-Enabled Channels and Single-Ended I/Os
313
Guidelines for DPA-Enabled Differential Channels
313
Using Corner and Center Left/Right Plls
313
Figure 9-18: Corner and Center Left/Right Plls Driving DPA-Enabled Differential I/Os in the same Bank
314
Figure 9-19: Center Left/Right Plls Driving DPA-Enabled Differential I/Os
315
Using both Center Left/Right Plls
315
Figure 9-20: Invalid Placement of DPA-Enabled Differential I/Os Driven by both Center Left/Right Plls
316
DPA-Disabled Channel Driving Distance
317
DPA-Disabled Channels and Single-Ended I/Os
317
Guidelines for DPA-Disabled Differential Channels
317
Using Corner and Center Left/Right Plls
317
Figure 9-21: Corner and Center Left/Right Plls Driving DPA-Disabled Differential I/Os in the same Bank
318
Figure 9-22: Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels Driven
319
Figure 9-23: both Center Left/Right Plls Driving Cross-Bank DPA-Disabled Channels Simultaneously
320
Using both Center Left/Right Plls
320
Chapter Revision History
321
Table 9-4: Chapter Revision History
321
Chapter III. Hot Socketing, Configuration, Remote Upgrades, and Testing
323
Revision History
323
Chapter 10 . Hot Socketing and Power-On Reset in Stratix III Devices
325
Stratix III Hot-Socketing Specifications
325
Stratix III Devices Can be Driven before Power up
325
I/O Pins Remain Tri-Stated During Power up
326
Insertion or Removal of a Stratix III Device from a Powered-Up System
326
Hot-Socketing Feature Implementation in Stratix III Devices
326
Figure 10-1: Hot-Socketing Circuitry for Stratix III Devices
327
Figure 10-2: Transistor Level Diagram of a Stratix III Device I/O Buffers
328
Power-On Reset Circuitry
328
Figure 10-3: Simplified por Block Diagram
329
Power-On Reset Specifications
329
Table 10-1: Power Supplies Ramp-Up Time
329
Table 10-2: Power Supplies Monitored by the por Circuitry
329
Table 10-3: Power Supplies that Are Not Monitored by the por Circuitry
330
Chapter Revision History
331
Table 10-4: Chapter Revision History
331
Chapter 11. Configuring Stratix III Devices
333
Configuration Devices
333
Configuration Schemes
333
Table 11-1: Stratix III Configuration Schemes
334
Table 11-2: Stratix III Uncompressed Raw Binary File (.Rbf) Sizes
334
Configuration Features
335
Table 11-3: Stratix III Configuration Features
335
Configuration Data Decompression
336
Figure 11-1: Enabling Compression for Stratix III Bitstreams in Compiler Settings
337
Design Security Using Configuration Bitstream Encryption
338
Figure 11-2: Compressed and Uncompressed Configuration Data in the same Configuration File
338
Power-On Reset Circuit
339
Remote System Upgrade
339
Fast Passive Parallel Configuration
340
FPP Configuration Using a MAX II Device as an External Host
340
Table 11-4: Stratix III MSEL Pin Settings for FPP Configuration Schemes
340
Figure 11-3: Single Device FPP Configuration Using an External Host
341
Figure 11-4: Multi-Device FPP Configuration Using an External Host
344
Figure 11-5: Multiple-Device FPP Configuration Using an External Host When both Devices Receive the
345
Figure 11-6: FPP Configuration Timing Waveform
346
FPP Configuration Timing
346
Table 11-5: FPP Timing Parameters for Stratix III Devices (Note 1)
346
Figure 11-7: FPP Configuration Timing Waveform with Decompression or Design Security Feature en
347
FPP Configuration Using a Microprocessor
348
Table 11-6: FPP Timing Parameters for Stratix III Devices with Decompression or Design Security Feature Enabled (Note 1)
348
Fast Active Serial Configuration (Serial Configuration Devices)
349
Table 11-7: Stratix III MSEL Pin Settings for as Configuration Schemes (Note 1)
349
Figure 11-8: Single Device Fast as Configuration
350
Figure 11-9: Multi-Device Fast as Configuration
353
Estimating Active Serial Configuration Time
355
Figure 11-10: Multi-Device Fast as Configuration When the Devices Receive the same Data Using a Single
355
Figure 11-11: Fast as Configuration Timing
356
Table 11-8: Fast as Timing Parameters for Stratix III Devices
356
Programming Serial Configuration Devices
357
Figure 11-12: In-System Programming of Serial Configuration Devices
358
Passive Serial Configuration
359
Figure 11-13: Single Device PS Configuration Using an External Host
359
PS Configuration Using a MAX II Device as an External Host
359
Table 11-9: Stratix III MSEL Pin Settings for PS Configuration Scheme
359
Figure 11-14: Multi-Device PS Configuration Using an External Host
362
Figure 11-15: Multiple-Device PS Configuration When both Devices Receive the same Data
363
Figure 11-16: PS Configuration Timing Waveform (Note 1)
364
PS Configuration Timing
364
Table 11-10: PS Timing Parameters for Stratix III Devices
364
PS Configuration Using a Download Cable
365
PS Configuration Using a Microprocessor
365
Figure 11-17: PS Configuration Using a Download Cable
367
Figure 11-18: Multi-Device PS Configuration Using a Download Cable
368
JTAG Configuration
369
Table 11-11: Dedicated JTAG Pins
370
Figure 11-19: JTAG Configuration of a Single Device Using a Download Cable
371
Table 11-12: Dedicated Configuration Pin Connections During JTAG Configuration
372
Figure 11-20: JTAG Configuration of Multiple Devices Using a Download Cable
373
Figure 11-21: JTAG Configuration of a Single Device Using a Microprocessor
374
Jam STAPL
375
Device Configuration Pins
375
Table 11-13: Stratix III Configuration Pin Summary (Note 1)
375
Table 11-14: Dedicated Configuration Pins on the Stratix III Device
376
Table 11-15: Optional Configuration Pins
381
Table 11-16: Dedicated JTAG Pins
382
Table 11-17: Chapter Revision History
383
Figure 12-1: Functional Diagram of Stratix III Remote System Upgrade
386
Figure 12-2: Remote System Upgrade Block Diagram for Stratix III Fast as Configuration Scheme
386
Chapter 12. Remote System Upgrades with Stratix III Devices Functional Description
387
Enabling Remote Update
387
Table 12-1: Stratix III Remote System Upgrade Modes
387
Configuration Image Types
388
Figure 12-3: Enabling Remote Update for Stratix III Devices in Compiler Settings
388
Remote System Upgrade Mode
389
Remote Update Mode
389
Figure 12-4: Transitions between Configurations in Remote Update Mode
390
Dedicated Remote System Upgrade Circuitry
391
Figure 12-5: Remote System Upgrade Circuit Data Path (Note 1)
392
Remote System Upgrade Registers
392
Table 12-2: Remote System Upgrade Registers
392
Figure 12-6: Remote System Upgrade Control Register
393
Remote System Upgrade Control Register
393
Table 12-3: Remote System Upgrade Control Register Contents
393
Figure 12-7: Remote System Upgrade Status Register
394
Remote System Upgrade Status Register
394
Table 12-4: Remote System Upgrade Status Register Contents
394
Remote System Upgrade State Machine
395
Table 12-5: Control Register Contents after an Error or Reconfiguration Trigger Condition
395
User Watchdog Timer
395
Quartus II Software Support
396
Table 12-6: 10-Mhz Internal Oscillator Specifications
396
ALTREMOTE_UPDATE Megafunction
397
Figure 12-8: Interface Signals between the ALTREMOTE_UPDATE Megafunction and the Nios II Proces
397
Chapter Revision History
398
Table 12-7: Chapter Revision History
398
Chapter 13 .IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratixiii Devices
399
IEEE Std. 1149.1 BST Architecture
399
Table 13-1: IEEE Std. 1149.1 Pin Descriptions
400
Figure 13-2: IEEE Std. 1149.1 Circuitry
401
IEEE Std. 1149.1 Boundary-Scan Register
402
Figure 13-3: Boundary-Scan Register
402
Table 13-2: Stratix III Boundary-Scan Register Length
402
Boundary-Scan Cells of a Stratix III Device I/O Pin
403
Figure 13-4: Stratix III Device's User I/O BSC with IEEE Std. 1149.1 BST Circuitry
403
Table 13-3: Stratix III Device Boundary Scan Cell Descriptions (Note 1)
404
IEEE Std. 1149.1 BST Operation Control
405
Table 13-4: Stratix III JTAG Instructions
405
Figure 13-5: IEEE Std. 1149.1 TAP Controller State Machine
406
Figure 13-6: IEEE Std. 1149.1 Timing Waveforms
407
Figure 13-7: Selecting the Instruction Mode
407
Figure 13-8: IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode
409
SAMPLE/PRELOAD Instruction Mode
409
Figure 13-9: SAMPLE/PRELOAD Shift Data Register Waveforms
410
EXTEST Instruction Mode
411
Figure 13-10: IEEE Std. 1149.1 BST EXTEST Mode
411
Figure 13-11: EXTEST Shift Data Register Waveforms
412
BYPASS Instruction Mode
413
Figure 13-12: BYPASS Shift Data Register Waveforms
413
CLAMP Instruction Mode
414
IDCODE Instruction Mode
414
Table 13-5: 32-Bit Stratix III Device IDCODE
414
USERCODE Instruction Mode
414
HIGHZ Instruction Mode
415
I/O Voltage Support in JTAG Chain
415
Table 13-6: Supported TDO/TDI Voltage Combinations
415
IEEE Std. 1149.1 BST Circuitry
416
Figure 13-13: JTAG Chain of Mixed Voltages
416
IEEE Std. 1149.1 BST Circuitry (Disabling)
417
IEEE Std. 1149.1 BST Guidelines
417
Table 13-7: Disabling IEEE Std. 1149.1 Circuitry
417
Boundary-Scan Description Language (BSDL) Support
418
Chapter Revision History
419
Table 13-8: Chapter Revision History
419
Chapter 14. Design Security in Stratix III Devices
421
Introduction
423
Stratix III Security Protection
423
Security against Copying
423
Security against Reverse Engineering
424
Security against Tampering
424
AES Decryption Block
424
Flexible Security Key Storage
424
Table 14-1: Security Keys Options
424
Stratix III Design Security Solution
425
Table 14-2: Key Retention Time of Coin-Cell Type Batteries Used for Volatile Key Storage
425
Security Modes Available
426
Figure 14-1: Design Security (Note 1)
426
Non-Volatile Key
426
Non-Volatile Key with Tamper Protection Bit Set
426
Volatile Key
426
No Key Operation
427
Supported Configuration Schemes
427
Table 14-3: Security Modes Supported
427
Figure 14-2: Stratix III Security Modes - Sequence and Restrictions
428
Table 14-4: Allowed Configuration Modes for Various Security Modes (Note 1)
428
Table 14-5: Design Security Configuration Schemes Availability
429
Conclusion
430
Chapter Revision History
430
Table 14-6: Chapter Revision History
430
Chapter IV. Design Security and Single Event Upset (SEU) Mitigation
421
Revision History
421
Chapter 15. SEU Mitigation in Stratix III Devices
432
Error Detection Fundamentals
432
Configuration Error Detection
432
User Mode Error Detection
432
Table 15-1: EDERROR_INJECT JTAG Instruction
434
Automated Single Event Upset Detection
435
Table 15-2: Fault Injection Register and Error Injection
435
Error Detection Pin Description
436
CRC_ERROR Pin
436
Table 15-3: CRC_ERROR Pin Description
436
Error Detection Block
437
Error Detection Registers
437
Figure 15-1: Error Detection Block Diagram
438
Table 15-4: Error Detection Registers
438
Error Detection Timing
439
Table 15-5: Minimum and Maximum Error Detection Frequencies
439
Table 15-6: Minimum Update Interval for Error Message Register (Note 1)
440
Table 15-7: CRC Calculation Time
440
Figure 15-2: Enabling the Error Detection CRC Feature in the Quartus II Software
441
Software Support
441
Recovering from CRC Errors
442
Chapter Revision History
442
Table 15-8: Chapter Revision History
442
Chapter V. Power and Thermal Management
443
Revision History
443
Chapter 16. Programmable Power and Temperature-Sensing Diodes
445
In Stratix III Devices
445
Introduction
445
Selectable Core Voltage
445
Stratix III Power Technology
445
Programmable Power Technology
446
Relationship between Selectable Core Voltage and Programmable Power Technology
447
Stratix III External Power Supply Requirements
447
Table 16-1: Stratix III Programmable Power Capabilities
447
Table 16-2: Stratix III Power Supply Requirements
448
Figure 16-1: Stratix III Power Management Example
449
Temperature Sensing Diode
449
Conclusion
450
External Pin Connections
450
Figure 16-2: TEMPDIODEP and TEMPDIODEN External Pin Connections
450
Figure 16-3: TSD Connections
450
Chapter Revision History
451
Table 16-3: Chapter Revision History
451
Chapter 17. Stratix III Device Packaging Information
453
Chapter VI. Packaging Information
453
Revision History
453
Table 17-1: Fineline and Hybrid Fineline BGA Packages for Stratix III Devices
455
Chapter Revision History
456
Package Outlines
456
Table 17-2: Chapter Revision History
456
Thermal Resistance
456
Advertisement
Advertisement
Related Products
Altera EP3SL50
Altera EP3SL70
Altera EP3SL110
Altera EP3SL150
Altera EP3SL200
Altera EP3SE50
Altera EP3SE80
Altera EP3SE110
Altera EP3SE260
Altera Enpirion EP5358xUI Series
Altera Categories
Motherboard
Microcontrollers
Computer Hardware
Transceiver
Media Converter
More Altera Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL