Page 1 Stratix III Device Handbook, Volume 1 Software Version: 10.0 Document Version: Document Date: © March 2011 101 Innovation Drive San Jose, CA 95134 www.altera.com...
Page 2 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation.
Page 3: Table Of Contents
How to Contact Altera ........
Page 5 Chapter Revision History ..............5-42 Chapter 6. Clock Networks and PLLs in Stratix III Devices © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 6 Revision History ............... . II-1 Chapter 7. Stratix III Device I/O Features Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 7 Chapter Revision History ..............7-42 Chapter 8. External Memory Interfaces in Stratix III Devices © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 8 Receiver Skew Margin for Non-DPA ........... 9-17 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 10 Supported Configuration Schemes ............14-5 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 13 Chapter 10 Hot Socketing and Power-On Reset in Stratix III Devices Revised: March 2010 Part Number: SIII51010-1.7 Chapter 11 Configuring Stratix III Devices Revised: March 2011 Part Number: SIII51011-2.0 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 14 Chapter 16 Programmable Power and Temperature-Sensing Diodes in Stratix III Devices Revised: February 2009 Part Number: SIII51016-1.5 Chapter 17 Stratix III Device Packaging Information Revised: March 2010 Part Number: SIII51017-1.7 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 16 Figure 6–22: Stratix III PLL Ports ............6-24 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 17 Figure 7–22: Differential SSTL I/O Standard Termination for Stratix III Devices ....7-35 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 18 Figure 9–13: LVDS/DPA Clocks with Center PLLs for Stratix III Devices ......9-14 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 19 Figure 12–7: Remote System Upgrade Status Register ......... 12-10 Figure 12–8: Interface Signals Between the ALTREMOTE_UPDATE Megafunction and the Nios II Proces- © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 20 Figure 16–3: TSD Connections ............. . 16-6 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 22 Table 11–4: Stratix III MSEL Pin Settings for FPP Configuration Schemes ......11-8 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 25: Additional Information
(Software Licensing) Email authorization@altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Meaning Bold Type with Initial Capital...
Page 26 A warning calls attention to a condition or possible situation that can cause injury to the user. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 27: Chapter I. Device Core
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 28 I–2 Section I: Device Core Revision History Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 29 ® high-performance, low-power FPGAs in the marketplace. Stratix III FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use.
Page 30 M144K TriMatrix memory blocks Nios II embedded processor support ■ ® ■ Support for multiple intellectual property megafunctions from Altera MegaCore ® ® functions and Altera Megafunction Partners Program (AMPP Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 31: Chapter 1. Stratix Iii Device Family Overview Features Summary
Stratix III devices are available in space-saving FineLine BGA (FBGA) packages (refer Table 1–2 Table 1–3). © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 32: Table 1-2: Package Options And I/O Pin Counts (Note 1)
484 Pin 780 Pin 1152 Pin 1517 Pin 1760 Pin Pitch (mm) 1.00 1.00 1.00 1.00 1.00 Area (mm 1,225 1,600 1,849 Length/Width (mm/ mm) 23/23 29/29 35/35 40/40 43/43 Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 33: Table 1-4: Hybrid Fineline Bga Package Sizes
— — — –2,–3, –4, –2, –3, –4, Commercial — — — — — –4L –4L EP3SE110 Industrial — –3, –4, –4L — –3, –4, –4L — — — © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 34: Architecture Features
Adaptive Logic Modules in Stratix III Devices chapter. For more information about MLAB modes, features and design considerations, refer to the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 35: Multitrack Interconnect
DSP blocks to implement finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 36: Clock Networks And Plls
Stratix III PLLs also support external feedback mode, spread-spectrum input clock tracking, and post-scale counter cascading. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 37: I/O Banks And I/O Structure
I/O interconnect standards and applications: Utopia IV, SPI-4.2, SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. Stratix III devices support 2×, 4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 38: Hot Socketing And Power-On Reset
■ Joint Test Action Group (JTAG) All configuration schemes use either an external controller (for example, a MAX ® device or microprocessor), a configuration device, or a download cable. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 39: Remote System Upgrades
Stratix III devices have the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm, an industry standard encryption algorithm that is FIPS-197 certified and requires a 256-bit security key. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 40: Seu Mitigation
■ Programmable Power and Temperature Sensing Diode in Stratix III Devices chapter ■ AN 437: Power Optimization in Stratix III FPGAs Stratix III Programmable Power White Paper ■ Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 41: Signal Integrity
The following section describes Stratix III device software support and ordering information. Software Support Stratix III devices are supported by the Altera Quartus II design software, version 6.1 and later, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes...
Page 42: Ordering Information
February 2009 Updated Table 1–1. ■ Removed “Referenced Documents” section. ■ Updated “Features” section. ■ October 2008 Updated Table 1–1 and Table 1–5. ■ Updated New Document Format. ■ Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 43 ■ Added live links for references. ■ Minor formatting changes, fixed PLL numbers and ALM, LE and MLAB bit counts in May 2007 Table 1–1. November 2006 Initial Release. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 44 1–16 Chapter 1: Stratix III Device Family Overview Chapter Revision History Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 45: Introduction
Figure 2–1 shows the Stratix III LAB structure and the LAB interconnects. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 46: Figure 2-1: Stratix Iii Lab Structure
LAB and MLAB topology. The MLAB is described in detail in the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 47: Lab Interconnects
Each ALM can drive 30 ALMs through fast local and direct link interconnects. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 48: Lab Control Signals
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrack interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2–4shows the LAB control signal generation circuit. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 49: Adaptive Logic Modules
Figure 2–5 shows a high-level block diagram of the Stratix III ALM while Figure 2–6 shows a detailed view of all the connections in an ALM. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 50: Figure 2-5: High-Level Block Diagram Of The Stratix Iii Alm
To general or adder1 local routing 6-Input LUT datae1 reg1 dataf1 To general or local routing Combinational/Memory ALUT1 reg_chain_out carry_out shared_arith_out Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 51: Figure 2-6: Stratix Iii Alm Details
Either general-purpose I/O pins or internal logic can drive the clock enable. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of an ALM. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 52: Alm Operating Modes
The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs. Figure 2–7 shows the supported LUT combinations in normal mode. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 53: Figure 2-7: Alm In Normal Mode (Note 1)
The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab). © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 54: Figure 2-8: 4 × 2 Crossbar Switch Example
The Quartus II Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 55: Extended Lut Mode
LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of 2 four-input functions. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 56: Figure 2-11: Alm In Arithmetic Mode
50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in Figure 2–12. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 57: Figure 2-12: Conditional Operation Example
LAB. These signals can also be individually disabled or enabled per register. The Quartus II software automatically places any registers that are not used by the counter into other LABs. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 58: Carry Chain
This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. Figure 2–13 shows the ALM using this feature. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 59: Figure 2-13: Alm In Shared Arithmetic Mode
An example of a three-bit add operation utilizing the shared arithmetic mode is shown in Figure 2–14. The partial sum (S[3..0]) and the partial carry (C[3..0]) is obtained using the LUTs, while the result (R[3..0]) is computed using the dedicated adders. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 60: Shared Arithmetic Chain
ALMs in a LAB while leaving the other half available for narrower fan-in functionality. Every other LAB column is top-half bypassable, while the other LAB columns are bottom-half bypassable. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 61: Lut-Register Mode
ALM. Figure 2–16 shows the ALM in LUT-Register mode. Figure 2–15. LUT Register from Two Combinational Blocks sumout LUT regout 4-input combout aclr sumout 5-input combout datain(datac) sclr © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 62: Register Chain
These resources speed up connections between ALMs while saving local interconnect resources (refer to Figure 2–17). The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 63: Figure 2-17: Register Chain Within An Lab
(1) You can use the combinational or adder logic to implement an unrelated, un-registered function. For more information on register chain interconnect, refer to “ALM Interconnects” on page 2–20. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 64: Alm Interconnects
Stratix III devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This device-wide reset overrides all other control signals. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 65: Lab Power Management Techniques
Summary of Changes February 2009, Removed “Referenced Documents” section. — version 1.5 Updated “LAB Control Signals”, and “Carry Chain” Sections. ■ October 2008, — version 1.4 Updated New Document Format. ■ © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 66 Added live links for references. ■ Minor formatting changes. ■ May 2007, Minor changes. version 1.1 Updated Figure 2–6 to include a missing connection. ■ November 2006, Initial Release. — version 1.0 Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 67: Introduction
LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 68: Column Interconnects
Register chain interconnects in a LAB ■ C4 interconnects traversing a distance of four blocks in the same device column ■ C12 column interconnects for high-speed vertical routing through the device Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation...
Page 69: Figure 3-2: Shared Arithmetic Chain, Carry Chain, And Register Chain Interconnects
IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 70: Figure 3-3: C4 Interconnect Connections (Note 1)
Adjacent LAB can drive onto neighboring LAB's C4 interconnect Local Interconnect C4 Interconnects Driving Down Note to Figure 3–3: (1) Each C4 interconnect can drive either up or down four rows. Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation...
Page 71: Table 3-1: Stratix Iii Device Routing Scheme
— — — — — — — — — Notes to Table 3–1: (1) Except column IOE local interconnects. (2) Row IOE local interconnects. (3) Column IOE local interconnects. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 72: Memory Block Interface
MLAB RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 3–4 shows the MLAB RAM block to LAB row interface. Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation...
Page 73: Figure 3-4: Mlab Ram Block Lab Row Interface
20 possible from the right adjacent LAB. M9K RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 3–5 shows the M9K RAM block to logic array interface. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 74: Figure 3-5: M9K Ram Block Lab Row Interface
20 possible from the right adjacent LAB. M144K block outputs can also connect to the LABs on the block’s left and right sides through direct link interconnect. Figure 3–6 shows the interface between the M144K RAM block and the logic array. Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation...
Page 75: Dsp Block Interface
LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects. Outputs can drive right- or left-column routing. Figure 3–7 Figure 3–8 show the DSP block interfaces to LAB rows. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 76: Figure 3-7: High-Level View, Dsp Block Interface To Interconnect
DSP Block OA[17..0] R4, C4 & Direct R4, C4 & Direct OB[17..0] Link Interconnects Link Interconnects A1[35..0] B1[35..0] OC[17..0] OD[17..0] A2[35..0] B2[35..0] OE[17..0] OF[17..0] A3[35..0] B3[35..0] OG[17..0] OH[17..0] A4[35..0] B4[35..0] Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation...
Page 77: I/O Block Connections To Interconnect
Figure 3–9 shows how a row I/O block connects to the logic array. Figure 3–10 shows how a column I/O block connects to the logic array. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 78: Figure 3-9: Row I/O Block Connection To Interconnect
Logic Array Horizontal I/O Block io_dataina[3..0] io_datainb[3..0] Direct Link Direct Link Interconnect Interconnect Horizontal I/O from Adjacent LAB to Adjacent LAB Block Contains LAB Local up to Four IOEs Interconnect Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation...
Page 79: Conclusion
DSP blocks, and IOEs. These blocks communicate with themselves and one another through the MultiTrack interconnect structures. The Quartus II compiler automatically routes critical design paths on faster interconnects to improve design performance and optimize the device resources. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 80: Chapter Revision History
Minor formatting changes. ■ October 2007, Minor formatting Added section “Chapter Revision History”. ■ version 1.1 changes. Added live links for references. ■ November 2006, Initial Release. — version 1.0 Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation...
Page 81: Introduction
16 × 20 512 × 16 4 K × 36 512 × 18 2 K × 64 256 × 32 2 K × 72 256 × 36 Parity bits © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 82: Overview
Notes to Table 4–1: (1) In ROM mode, MLABs support the (depth × width) configurations of 64×8, 64×9, 64×10, 32×16, 32×18, or 32× 20. (2) MLABs support byte-enable via emulation. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 83: Trimatrix Memory Block Types
The unwritten bytes retain the previous written value. The write enable (wren) signals, along with the byte-enable (byteena) signals, control the RAM blocks’ write operations. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 84: Figure 4-1: Stratix Iii Byte-Enable Functional Waveform For M9K And M144K
FFFF ABCD contents at a2 doutn ABXX XXCD ABCD ABFF FFCD ABCD don't care: q (asynch) FFCD doutn ABFF ABCD ABFF FFCD ABCD current data: q (asynch) Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 85: Packed Mode Support
(addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signals is low (disabled). © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 86: Figure 4-3: Stratix Iii Address Clock Enable Block Diagram
Figure 4–4. Stratix III Address Clock Enable during Read Cycle Waveform inclock rdaddress rden addressstall latched address (inside memory) q (synch) dout0 dout4 doutn-1 doutn dout1 q (asynch) doutn dout0 dout1 dout4 dout5 Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 87: Figure 4-5: Stratix Iii Address Clock Enable During Write Cycle Waveform For M9K And M144K
Figure 4–5. Stratix III Address Clock Enable during Write Cycle Waveform for M9K and M144K inclock wraddress data wren addressstall latched address (inside memory) contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 88: Mixed Width Support
Therefore, if your M9K and M144K are not using the output registers, you can still clear the RAM outputs via the output latch asynchronous clear. The functional waveform in Figure 4–7 shows this functionality. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 89: Error Correction Code Support
Double error and no fix Illegal Illegal Illegal Illegal You cannot use the byte-enable feature when ECC is engaged. Read during write “old data” mode is not supported when ECC is engaged. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 90: Single Port Ram
Simultaneous reads and writes are not supported in single-port mode. Figure 4–9 shows the single-port RAM configuration. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 91: Figure 4-9: Single-Port Memory (Note 1)
(1) Configurations of 64 × 8, 64 × 9, 64 × 10, 32 × 16, 32 × 18, and 32 × 20 are supported by stitching multiple MLAB blocks. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 92: Simple Dual-Port Mode
All TriMatrix memory blocks support simple dual-port mode. Simple dual-port mode allows you to perform one-read and one-write operation to different locations at the same time. Figure 4–12 shows the simple dual-port configuration. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 93: Figure 4-12: Stratix Iii Simple Dual-Port Memory
— — — — 2K×64 — — — — 16K×9 — — — — 8K×18 — — — — 4K×36 — — — — 2K×72 — — — — © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 94: Figure 4-13: Stratix Iii Simple Dual-Port Timing Waveforms For M9K And M144K
Figure 4–14. Stratix III Simple Dual-Port Timing Waveforms for MLABs wrclock wren wraddress an-1 data din-1 din4 din5 din6 rdclock rden rdaddress q (asynch) dout0 doutn-1 doutn Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 95: True Dual-Port Mode
1K×9 512×18 8K×1 — — 4K×2 — — 2K×4 — — 1K×8 — — 512×16 — — 1K×9 — — — — — 512×18 — — — — — © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 96: Table 4-8: Stratix Iii M144K Block Mixed-Width Configurations (True Dual-Port Mode)
A and read operation at port B with the Read-During-Write behavior set to new data. Registering the RAM’s outputs would simply delay the q outputs by one clock cycle. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 97: Shift-Register Mode
The size of a shift register (w × m × n) is determined by the input data width (w), the length of the taps (m), and the number of taps (n). You can cascade memory blocks to implement larger shift registers. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 98: Rom Mode
Quartus II software FIFO MegaWizard Plug-In Manager. Both single and dual-clock (asynchronous) FIFOs are supported. For more information about implementing FIFO buffers, refer to the Single- and Dual-Clock FIFO Megafunctions User Guide. MLABs do not support mixed-width FIFO mode. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 99: Clocking Modes
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This applies to both read and write operations. Altera recommends using a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block performance.
Page 100: Read/Write Clock Mode
Therefore, you must implement conflict resolution logic external to the memory block to avoid address conflicts. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 101: Read During Write
Using the don’t care mode increases the flexibility in the type of memory block used, provided you do not assign block type when instantiating a memory block. You may also get potential performance gain by selecting the don’t care mode. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 102: Mixed-Port Read-During-Write Mode
RAM outputs to reflect the old data at that address location. In don’t care mode, the same operation results in a “don’t care” or “unknown” value on the RAM outputs. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 103: Power-Up Conditions And Memory Initialization
(for example, by a .mif file), it still powers up with its outputs cleared. For more information about .mif files, refer to the RAM Megafunction User Guide Quartus II Handbook. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 104: Power Management
You can independently configure each embedded memory block to be a single- or dual-port RAM, FIFO, ROM, or shift register via the Quartus II MegaWizard Plug-In Manager software. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 105: Chapter Revision History
Added section “Referenced Documents”. — ■ version 1.2 Added live links for references. ■ May 2007, Updated Table 4–2, Table 4–9. — version 1.1 November 2006, Initial Release. — version 1.0 © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 106 4–26 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Chapter Revision History Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 107: Chapter 5. Dsp Blocks In Stratix Iii Devices
■ Cascading 44-bit output bus to propagate output results from one block to the next block without external logic support ■ Rich and flexible arithmetic rounding and saturation units © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 108: Table 5-1: Number Of Dsp Blocks In Stratix Iii Devices
The Stratix III DSP block input data lines of 288-bits are double that of Stratix and Stratix II, but the number of output data lines remains at 144 bits. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 109: Simplified Dsp Operation
Equation 5–1. Multiplier Equation P[36..0] = A [17..0] × B [17..0] ± A [17..0] × B [17..0] Figure 5–2. Basic Two-Multiplier Adder Building Block A0[17..0] B0[17..0] +/− P[36..0] A1[17..0] B1[17..0] © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 110 44-bit accumulation capability by feeding the output of the unit back to itself. This is shown in Figure 5–3. You can bypass all register stages depending on which mode you select. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 111: Figure 5-3: Four-Multiplier Adder And Accumulation Capability
To support single-channel type FIR filters efficiently, you can configure one of the multiplier input’s registers to form a tap delay line input, saving resources and providing higher system performance. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 112: Figure 5-4: Output Cascading Feature For Fir Structures
A top-level view of the Stratix III DSP block is shown in Figure 5–5. A more detailed diagram is shown in Figure 5–6. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 113: Figure 5-5: Stratix Iii Full Dsp Block Summary
Simplified DSP Operation Figure 5–5. Stratix III Full DSP Block Summary From Previous Half-Block DSP Input Result Data Top Half-DSP Block Input Result Data Bottom Half-DSP Block To Next Half-Block DSP © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 114: Operational Modes Overview
DSP block resource efficiency and allows you to implement more multipliers within a Stratix III device. The Quartus II software automatically places multipliers that can share the same DSP block resources within the same block. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 115: Dsp Block Resource Descriptions
(2) Block output for accumulator overflow and saturate overflow. (3) Block output for saturation overflow of chainout. (4) When the chainout adder is not in use, the second adder register banks are known as output register banks. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 116: Input Registers
A feature of the input register bank is to support a tap delay line. Therefore, the top leg of the multiplier input (A) could be driven from general routing or from the cascade chain, as shown in Figure 5–7. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 117: Figure 5-7: Input Register Of Half-Dsp Block
DSP blocks. The dedicated shift register chain spans a single column, but you can implement longer shift register chains requiring multiple columns using the regular FPGA routing resources. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 118: Multiplier And First-Stage Adder
(signb Value) Unsigned (logic 0) Unsigned (logic 0) Unsigned Unsigned (logic 0) Signed (logic 1) Signed Signed (logic 1) Unsigned (logic 0) Signed Signed (logic 1) Signed (logic 1) Signed Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 119: Pipeline Register Stage
The output of the second-stage adder has the option to go into the round and saturation logic unit or the output register. You cannot use the second-stage adder independently from the multiplier and first-stage adder. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 120: Round And Saturation Stage
(functioning as regular output registers). Refer to “Operational Mode Descriptions” on page 5–15 for details. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 121: Operational Mode Descriptions
Figure 5–8. 18-Bit Independent Multiplier Mode for Half-DSP Block signa clock[3..0] signb ena[3..0] overflow output_round aclr[3..0] output_saturate dataa_0[17..0] result_0[ ] datab_0[17..0] dataa_1[17..0] result_1[ ] datab_1[17..0] Half-DSP Block © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 122: Figure 5-9: 12-Bit Independent Multiplier Mode For Half-Dsp Block
Operational Mode Descriptions Figure 5–9. 12-Bit Independent Multiplier Mode for Half-DSP Block clock[3..0] signa ena[3..0] aclr[3..0] signb dataa_0[11..0] result_0[ ] datab_0[11..0] dataa_1[11..0] result_1[ ] datab_1[11..0] dataa_2[11..0] result_2[ ] datab_2[11..0] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 123: Figure 5-10: 9-Bit Independent Multiplier Mode For Half-Block
You can use the pipeline registers within the DSP block to pipeline the multiplier result, increasing the performance of the DSP block. The round and saturation logic unit is supported for the 18-bit independent multiplier mode only. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 124: 36-Bit Multiplier
Figure 5–11. 36-Bit Independent Multiplier Mode for Half-DSP Block clock[3..0] signa ena[3..0] signb aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] result[ ] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 125: Double Multiplier
This is shown in Figure 5–12 Figure 5–13. Figure 5–12. Double Mode for Half-DSP Block clock[3..0] ena[3..0] signa signb aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] result[ ] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 126: Figure 5-13: Unsigned 54 × 54 Multiplier
Double Mode dataa[35..18] datab[53..36] dataa[17..0] datab[53..36] result[ ] dataa[53..36] datab[35..18] dataa[53..36] datab[17..0] 36 x 36 Mode dataa[35..18] datab[35..18] dataa[17..0] datab[35..18] dataa[35..18] datab[17..0] dataa[17..0] datab[17..0] Unsigned 54 X 54 Multiplier Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 127: Two-Multiplier Adder Sum Mode
The two-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 128: Figure 5-14: Two-Multiplier Adder Mode For Half-Dsp Block
Figure 5–14. Two-Multiplier Adder Mode for Half-DSP Block signa clock[3..0] signb ena[3..0] output_round aclr[3..0] output_saturate overflow dataa_0[17..0] datab_0[17..0] result_0[ ] dataa_1[17..0] datab_1[17..0] dataa_2[17..0] datab_2[17..0] result_1[ ] dataa_3[17..0] datab_3[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 129: Figure 5-15: Loopback Mode For Half-Dsp Block
5–23 Operational Mode Descriptions Figure 5–15. Loopback Mode for Half-DSP Block signa clock[3..0] signb ena[3..0] output_round output_saturate aclr[3..0] zero_loopback overflow dataa_0[17..0] loopback datab_0[17..0] result[ ] dataa_1[17..0] datab_1[17..0] Half-DSP Block © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 130: 18 × 18 Complex Multiply
This mode automatically assumes all inputs are using signed numbers. Figure 5–16. Complex Multiplier Using Two-Multiplier Adder Mode clock[3..0] ena[3..0] signa signb aclr[3..0] C) − (B − (Real Part) D) − (B (Imaginary Part) Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 131: Four-Multiplier Adder
The four-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 132: High Precision Multiplier Adder
Equation 5–5. High Precision Multiplier Adder Equation Z[54..0] = P [53..0] + P [53..0] where = A[17..0] ´ B[35..0] and P = C[17..0] ´ D[35..0] Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 133: Figure 5-18: Four-Multiplier Adder Mode For Half-Dsp Block
Operational Mode Descriptions Figure 5–18. Four-Multiplier Adder Mode for Half-DSP Block signa clock[3..0] signb ena[3..0] aclr[3..0] overflow dataA[17..0] dataB[17..0] dataA[17..0] <<18 dataB[35..18] Z[54..0] dataC[17..0] dataD[17..0] dataC[17..0] <<18 dataD[35..0] Half-DSP Block © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 134: Multiply Accumulate Mode
] datab_0[ ] dataa_1[ ] datab_1[ ] result[ ] dataa_2[ ] datab_2[ ] dataa_3[ ] datab_3[ ] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 135: Shift Modes
Two control signals rotate and shift_right together with the signa and signb signals, determining the shifting operation. Examples of shift operations are listed in Table 5–5 on page 5–31. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 136: Figure 5-20: Shift Operation Mode For Half-Dsp Block
Operational Mode Descriptions Figure 5–20. Shift Operation Mode for Half-DSP Block signa clock[3..0] signb ena[3..0] rotate shift_right aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] result[ ] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 137: Rounding And Saturation Mode
Odd (0011) = 0.5 (10) 0100 110111 > 0.5 (11) 1110 101101 < 0.5 (01) 1011 110110 Odd (1101) = 0.5 (10) 1110 110010 Even (1100) = 0.5 (10) 1100 © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 138: Table 5-7: Comparison Of Round-To-Nearest-Integer And Round-To-Nearest-Even
In this example, a 44-bit input is saturated to 36-bits. Table 5–8. Examples of Saturation 44 to 36 Bits Saturation Symmetric SAT Result Asymmetric SAT Result 5926AC01342h 7FFFFFFFFh 7FFFFFFFFh ADA38D2210h 800000001h 800000000h Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 139: Figure 5-21: Round And Saturation Locations
Result = SAT[S(A × B)], when used for an accumulation type of operation. If both the round and saturation logic units are used for an accumulation type of operation, the format is: Result = SAT[RND[S(A × B)]] © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 140: Dsp Block Control Signals
= 1, rotation feature is enabled rotate shift_right = 1, shift right feature is enabled shift_right — Total Signals per Half-block clock0 clock1 DSP-block-wide clock signals clock2 clock3 Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 141: Application Examples
The B input of the multiplier feeds from the general routing. You can scan in the data in 18-bit parallel form and multiply it by the 18-bit input bus from general routing in each cycle. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 142 For a complete FIR, the results per individual Four-Multiplier Adder can be combined in either a tree or chained cascade manner. Using external logic and adders, you can very easily implement a tree summation, as shown in Figure 5–22. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 143: Figure 5-22: Fir Filter Using Tap-Delay Line Input And Tree Summation Of Final Result
One of the two second-stage adders is used to add the current Four-Multiplier Adder. The second second-stage adder takes the output of the first second-stage adder and adds it to the adjacent half DSP block of the Four-Multiplier Adder result. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 144: Figure 5-23: Fir Filter Using Tap-Delay Line Input And Chained Cascade Summation Of Final Result
Figure 5–23. FIR Filter using Tap-Delay Line Input and Chained Cascade Summation of Final Result signa clock[3..0] signb ena[3..0] chainout_round chainout_saturate aclr[3..0] zero_chainout chainout_sat_overflow dataa_0[ ] datab_0[17..0] Zero datab_1[17..0] datab_2[17..0] datab_3[17..0] Half-DSP Block Delay Register datab_4[17..0] datab_5[17..0] result[ ] datab_6[17..0] datab_7[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 145 Four-Multiplier Mode with independent inputs. Figure 5–24 shows an example for chained cascaded summation. In most cases, only the final stage FIR tap with the rounding and saturation unit is deployed. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 146: Figure 5-24: Semi-Parallel Fir Structure Using Chained Cascaded Summation
FFT is the FFT butterfly. FFTs are most efficient when operating on complex samples. You can use the Stratix III DSP block to form the core of a complex FFT butterfly very efficiently. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 147: Software Support
X[k,2] BFPU G[k,3] H[k,3] BFPU X[k,3] Software Support Altera provides two distinct methods for implementing various modes of the DSP block in a design: instantiation and inference. Both methods use the following Quartus II megafunctions: ■ LPM_MULT ALTMULT_ADD ■ ALTMULT_ACCUM ■...
Page 148: Chapter Revision History
Updated Table 5–1 and Table 5–5. ■ May 2007 Deleted Table 5-10. ■ Added sections “Double Multiplier” and “Referenced Documents”. ■ Clarification added for “Shift Modes” on page 5–28. ■ November 2006 Initial Release. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 149: Table 6-1: Clock Resources In Stratix Iii Devices
(PLLs) with advanced features in Stratix III devices. The large number of ® clocking resources, in combination with the clock synthesis precision provided by the PLLs, provide a complete clock management solution. The Altera Quartus ® ® software compiler automatically turns off clock networks not used in the design, thereby reducing the overall power consumption of the device.
Page 150: Clock Networks In Stratix Iii Devices
CLK pins and PLLs that can drive GCLK networks in Stratix III devices. Figure 6–1. Global Clock Networks CLK[12..15] T1 T2 GCLK[12..15] GCLK[0..3] GCLK[8..11] CLK[0..3] CLK[8..11] GCLK[4..7] B1 B2 CLK[4..7] Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 151: Regional Clock Networks
RCLK[12..21] RCLK[22..31] CLK[4..7] Figure 6–3. Regional Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices) CLK[12..15] RCLK[54..63] RCLK[44..53] RCLK[0..5] RCLK[38..43] Q1 Q2 CLK[0..3] CLK[8..11] Q4 Q3 RCLK[6..11] RCLK[32..37] RCLK[12..21] RCLK[22..31] CLK[4..7] © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 152: Periphery Clock Networks
Stratix III device. Figure 6–5. Periphery Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices) CLK[12..15] PCLK[0..13] PCLK[42..55] CLK[0..3] CLK[8..11] PCLK[14..27] PCLK[28..41] CLK[4..7] Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 153: Figure 6-6: Periphery Clock Networks (Ep3Sl110, Ep3Sl150, Ep3Se80, And Ep3Se110 Devices)
Q1 Q2 CLK[0..3] CLK[8..11] Q4 Q3 PCLK[22..32] PCLK[55..65] PCLK[33..43] PCLK[44..54] CLK[4..7] Figure 6–7. Periphery Clock Networks (EP3SL200 Devices) CLK[12..15] PCLK[77..87] PCLK[0..10] PCLK[11..21] PCLK[66..76] CLK[8..11] CLK[0..3] PCLK[22..32] PCLK[55..65] PCLK[33..43] PCLK[44..54] CLK[4..7] © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 154: Clocking Regions
You can utilize these clock resources to form the following three different types of clock regions: Entire device clock region ■ Regional clock region ■ ■ Dual-regional clock region Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 155: Clock Network Sources
CLK[15..0] for high fan-out control signals such as asynchronous clears, presets, and clock enables for protocol signals such as TRDY and IRDY for PCI through global or regional clock networks. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 156: Table 6-2: Clock Input Pin Connectivity To Global Clock Networks
— — GCLK13 — — — — — — — — — — — — GCLK14 — — — — — — — — — — — — GCLK15 Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 157: Table 6-3: Clock Input Pin Connectivity To Regional Clock Networks (Quadrant 1)
— — — — — — — — — — — — RCLK48 — — — — — — — — — — — — — — — RCLK49 © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 158 — — — — — — — — — — — — RCLK36 — — — — — — — — — — — — — — — RCLK37 Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 159: Table 6-6: Clock Input Pin Connectivity To Regional Clock Networks (Quadrant 4)
— — — — — — — — CLK10 — — — — — — — — CLK11 — — — — — — — — — — CLK12 © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 160: Clock Output Connections
— GCLK8 — — — — — — — — GCLK9 — — — — — — — — GCLK10 — — — — — — — — GCLK11 Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 161: Clock Source Control For Plls
[.pof]) only. Once programmed, this block cannot be changed without loading a new configuration file (.sof or .pof). The Quartus II software automatically sets the multiplexer select signals depending on the clock sources selected in the design. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 162: Clock Control Block
When selecting the clock source dynamically, you can either select two PLL outputs (such as CLK0 or CLK1), or a combination of clock pins or PLL outputs. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 163: Figure 6-13: Stratix Iii Global Clock Control Block
The unused global and regional clock networks are automatically powered down through configuration bit settings in the configuration file (.sof or .pof) generated by the © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 164: Figure 6-15: Stratix Iii External Pll Output Clock Control Block
(2) The clock control block feeds to a multiplexer within the PLL_<#>_CLKOUT pin's IOE. The PLL_<#>_CLKOUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 165: Clock Enable Signals
R2 not bypassed Note to Figure 6–17: (1) You can use the clkena signals to enable or disable the global and regional networks or the PLL_<#>_CLKOUT pins. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 166: Plls In Stratix Iii Devices
(1) PLLs T2, B2, L3, and R3 are not available in the F780 package. (2) PLLs L1, L4, R1, and R4 are not available in the H780, F1152, and H1152 packages. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 167: Table 6-11: Stratix Iii Pll Features
(3) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Stratix III device can shift all output frequencies in increments of at least 45 degrees. Smaller degree increments are possible depending on the frequency and divide parameters. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 168: Stratix Iii Pll Hardware Overview
Conversely, if the charge pump receives a down signal, current is drawn from the loop filter. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 169: Pll Clock I/O Pins
2nd pair: 2 single-ended I/O, 1 differential external feedback input (FBp/FBn), or ■ 1 single-ended external feedback input (FBp) ■ 3rd pair: 2 single-ended I/O or 1 differential input © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 170: Figure 6-20: External Clock Outputs For Top/Bottom Plls
I/Os, one of them can be the clock output while the other pin is the external feedback input (FB) pin. Hence, Left/Right PLLs only support external feedback mode for single-ended I/O standards. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 171: Figure 6-21: External Clock Outputs For Left/Right Plls
Stratix III PLLs can also drive out to any regular I/O pin through the global or regional clock network. You can use the external clock output pins as user I/O pins if external PLL clocking is not needed. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 172: Stratix Iii Pll Software Overview
Clock switchover circuit clkswitch clkswitch = 0, inclk0 is selected. If clkswitch = 1, inclk1 is selected. Both inclk0 and inclk1 must be switched in order for manual switchover to function. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 173: Table 6-13: Pll Output Signals
PLL. If this signal is high, inclk1 drives the PLL. Output of the last shift register in PLL scan chain Logic array scandataout the scan chain. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 174: Clock Feedback Modes
CLK12, CLK13, CLK14, or CLK15. When an RCLK or GCLK network drives the PLL, the input and output delays may not be fully compensated in the Quartus II software. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 175: Source Synchronous Mode
Set the input pin to register delay chain within the IOE to zero in the Quartus II software for all data pins clocked by a source-synchronous mode PLL. Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II software. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 176: Source-Synchronous Mode For Lvds Compensation
In normal mode, the delay introduced by the GCLK or RCLK network is fully compensated. Figure 6–26 shows an example waveform of the PLL clocks’ phase relationship in this mode. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 177: Zero-Delay Buffer Mode
The bi-directional I/O pin that you instantiate in your design should always be assigned a single-ended I/O standard. Figure 6–27. Zero-Delay Buffer Mode in Stratix III PLLs inclk ÷n PLL_<#>_CLKOUT# ÷C0 CP/LF ÷C1 PLL_<#>_CLKOUT# fbout ÷m bi-directional I/O pin fbin © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 178: External Feedback Mode
PLLs in external feedback mode. Figure 6–29. External Feedback Mode in Stratix III Devices inclk ÷n PLL_<#>_CLKOUT# ÷C0 CP/LF PLL_<#>_CLKOUT# ÷C1 fbout ÷m external board fbin trace Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 179: Clock Multiplication And Division
The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the ALTPLL megafunction. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 180: Post-Scale Counter Cascading
If the PLL is in external feedback mode, you must set the duty cycle for the counter driving the fbin pin to 50%. Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 181: Pll Control Signals
Altera recommends that you use the areset and locked signals in your designs to control and observe the status of your PLL.
Page 182: Automatic Clock Switchover
PLL. When using the automatic switchover mode, you can switch back and forth between inclk0 and inclk1 clocks any number of times, when one of the two clocks fails and the other clock is available. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 183: Figure 6-33: Automatic Switchover Upon Loss Of Clock Detection
100%, the clock sense block will detect when a clock stops toggling, but the PLL may lose lock after the switchover is completed and need time to re-lock. Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover.
Page 184: Figure 6-34: Clock Switchover Using The Clkswitch (Manual) Control
If the clock is not available, the state machine waits until the clock is available. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 185: Manual Clock Switchover
Both inclk0 and inclk1 must be running when the clkswitch signal goes high to instantiate the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 186: Figure 6-36: Vco Switchover Operating Frequency
When the PFD is re-enabled, output clock-enable signals (clkena) can disable clock outputs during the switchover and resynchronization period. Once the lock indication is stable, the system can re-enable the output clocks. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 187: Programmable Bandwidth
Figure 6–37. Open- and Closed-Loop Response Bode Plots Open-Loop Reponse Bode Plot Increasing the PLL's bandwidth in effect pushes the open loop response out. 0 dB Gain Frequency Closed-Loop Reponse Bode Plot Gain Frequency © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 188: Implementation
Quartus II software. The components are the loop filter resistor, R, the high frequency capacitor, C , and the charge pump current, I or I Figure 6–38. Loop Filter Programmable Components Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 189: Phase-Shift Implementation
0phase from the VCO but has the C value for the counter set to three. This arrangement creates a delay of 2Φ (two complete VCO periods). coarse © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 190: Pll Reconfiguration
(t ) delays in real time by changing the PLL output clock phase shift. This approach eliminates the need to regenerate a configuration file with the new PLL settings. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 191: Pll Reconfiguration Hardware Implementation
The counter is physically located after the VCO. The counter settings are updated synchronously to the clock frequency of the individual counters. Therefore, all counters are not updated simultaneously. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 192: Table 6-15: Real-Time Pll Reconfiguration Ports
6. Reset the PLL using the areset signal if you make any changes to the M, N, or post-scale C counters or the I , R, or C settings. 7. Steps 1 through 5 can be repeated to reconfigure the PLL any number of times. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 193: Post-Scale Counters (C0 To C9)
VCO output clock. However, a 4 and 6 setting for the high- and low-count values, respectively, would produce an output clock with 40-60% duty cycle. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 194: Scan Chain Description
Table 6–16. Top/Bottom PLL Reprogramming Bits (Part 1 of 2) Number of Bits Block Name Total Counter Other Charge Pump Current VCO Post-Scale divider (K) Loop Filter Capacitor Loop Filter Resistor Unused CP/LF Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 195: Figure 6-42: Scan-Chain Order Of Pll Components For Top/Bottom Plls (Note 1)
Stratix III PLLs. Figure 6–43. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix III PLLs DATAIN rbypass rselodd DATAOUT © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 196: Charge Pump And Loop Filter
CP[2] CP[1] CP[0] Setting Table 6–18. loop_filter_r Bit Settings Decimal Value for LFR[4] LFR[3] LFR[2] LFR[1] LFR[0] Setting Table 6–19. loop_filter_c Bit Settings LFC[1] LFC[0] Decimal Value for Setting Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 197: Bypassing Pll
PLL reconfiguration circuit PHASEUPDOWN is registered in the PLL on the rising edge of SCANCLK. Logic high enables dynamic phase Logic array or I/O pin PLL reconfiguration circuit PHASESTEP shifting. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 198: Table 6-22: Phase Counter Select Mapping
5. Repeat steps 1 through 4 as many times as required to perform multiple phase-shifts. All signals are synchronous to scanclk. They are latched on scanclk edges and must meet t requirements with respect to scanclk edges. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 199: Figure 6-44: Dynamic Phase Shifting Waveform
After phasedone goes from low to high, you can perform another dynamic phase shift. Phasestep pulses must be at least one scanclk cycle apart. For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer to the ALTPLL_RECONFIG Megafunction User Guide. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 200: Pll Cascading And Clock Network Guidelines
PLL bandwidth which is specified in the fitter report. Stratix III devices cannot internally generate spread-spectrum clocks. PLL Specifications For information about PLL timing specifications, refer to the DC and Switching Characteristics of Stratix III Devices chapter. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 201: Chapter Revision History
Updated notes to Figure 6–17. ■ Updated notes to Figure 6–22. ■ Updated notes to Figure 6–27. ■ Updated Figure 6–43. ■ November 2007 Updated “pfdena” on page 6–42. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 202 Changed frequency difference between inclk0 and inclk1 to more than 20% instead of May 2007 100% on page 42. Updated Table 6–16, note to Figure 6–17, and Figure 6–19. November 2006 Initial Release. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 203: Chapter Ii. I/O Interfaces
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 204 II–2 Section II: I/O Interfaces Revision History Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 205: Chapter 7. Stratix Iii Device I/O Features
Programmable bus-hold Programmable pull-up resistor ■ Open-drain output ■ ■ Serial, parallel, and dynamic on-chip termination (OCT) ■ Differential OCT ■ Programmable pre-emphasis Programmable differential output voltage (V ■ © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 206: Stratix Iii I/O Standards Support
Differential HSTL-15 Class I Clock interfaces Differential HSTL-15 Class II Clock interfaces Differential HSTL-12 Class I Clock interfaces Differential HSTL-12 Class II Clock interfaces LVDS High-speed communications RSDS Flat panel display Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 207: I/O Standards And Voltage Levels
0.90 HSTL-18 Class II JESD8-6 0.90 0.90 HSTL-15 Class I JESD8-6 0.75 0.75 HSTL-15 Class II JESD8-6 — 0.75 0.75 HSTL-12 Class I JESD8-16A HSTL-12 Class II JESD8-16A — © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 208: Table 7-2: I/O Standards And Voltage Levels For Stratix Iii Devices
HSTL-12 Class I Differential JESD8-16A — — 0.60 HSTL-12 Class II ANSI/TIA/ LVDS (6), — — EIA-644 RSDS (6), (7), — — — mini-LVDS (6), — — — (7), Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 209: Stratix Iii I/O Banks
(OCT R ) options. For the number of channels available for the LVDS I/O standard, refer to the High-Speed Differential I/O Interface with DPA in Stratix III Devices chapter. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 210: Figure 7-1: I/O Banks For Stratix Iii Devices
It is a graphical representation only. (9) 3.0-V PCI/PCI-X and 3.3-V LVTTL/LVCMOS outputs are not supported in the same I/O bank. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 211: Modular I/O Banks
Increase in Bank Size (number of I/O) — Column I/O — — Row I/O — Note to Table 7–3: (1) Number of I/O shown does not include dedicated clock input pins CLK[1,3,8,10][p,n]. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 212 Transceiver pins and dedicated configuration pins are not included in the pin count. Figure 7–2 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 213: Figure 7-3: Number Of I/Os In Each Bank In The 780-Pin Fineline Bga Package
(3) Number of I/Os in each Bank in EP3SL50,EP3SL70, EP3SL110, EP3SL150, EP3SE50, EP3SE80 and EP3SE110 in the 780-pin FineLine BGA package. (4) Number of I/Os in each Bank in EP3SL200 and EP3SE260 in the 780-pin Hybrid FineLine BGA package. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 214: Figure 7-4: Number Of I/Os In Each Bank In The 1152-Pin Fineline Bga Package
(3) Number of I/Os in Each Bank in EP3SL110, EP3SL150, EP3SL200, EP3SE80, EP3SE110, and EP3SE260 Devices in the 1152-pin FineLine BGA package. (4) Number of I/Os in Each Bank in EP3SL340 in the 1152-pin Hybrid FineLine BGA package. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 215: Figure 7-5: Number Of I/Os In Each Bank In Ep2Sl200, Ep3Se260, And Ep3Sl340 Devices In The 1517-Pin Fineline Bga Package (Note 1)
Dedicated configuration pins are not included in the pin count. Figure 7–5 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 216: Stratix Iii I/O Structure
■ ■ Programmable output-current strength ■ Programmable slew rate ■ Programmable output delay Programmable bus-hold ■ Programmable pull-up resistor ■ ■ Open-drain output ■ On-chip series termination with calibration Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 217: Figure 7-7: Ioe Structure For Stratix Iii Devices
HDR blocks. You can bypass each block of the output and OE path. For more information about I/O registers and how they are used for memory applications, refer to the External Memory Interfaces in Stratix III Devices chapter. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 218: 3.3-V I/O Interface
For device reliability and proper operation when interfacing with a 3.3 V I/O system using Stratix III devices, ensure that the absolute maximum ratings of Stratix III devices are not violated. Altera recommends performing IBIS simulation to determine that the overshoot and undershoot voltages are within the guidelines.
Page 219: High-Speed Differential I/O With Dpa Support
The LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of current strength that you can control. Table 7–5 lists information about programmable current strength. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 220: Programmable Slew Rate Control
HSTL/SSTL class I I/O standards. The default setting is 25-Ω OCT R without calibration for HSTL/SSTL class II I/O standards. Altera recommends performing IBIS or SPICE simulations to determine the right current strength setting for your specific application. Programmable Slew Rate Control...
Page 221: Programmable Delay
You can use faster slew rates to improve the available timing margin in memory-interface applications or when the output pin has high-capacitive loading. Altera recommends performing IBIS or SPICE simulations to determine the right slew rate setting for your specific application.
Page 222: Bus Hold
The default setting is low. For more information about programmable pre-emphasis, refer to the High-Speed Differential I/O Interfaces with DPA in the Stratix III Devices chapter. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 223: Programmable Differential Output Voltage
, either 1.2, 1.5, 1.8, or 3.0 V. The LVDS I/O standard ccio requires that a V of 2.5 V cannot be assigned in a same bank with a 3.0-V or 3.3-V output signal. CCIO © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 224: Oct Support
The values are 25 Ω and 50 Ω. When matching impedance is selected, current typical R strength is no longer selectable. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 225: On-Chip Series Termination With Calibration
Figure 7–9. On-Chip Series Termination with Calibration for Stratix III Devices Stratix III Driver Receiving Series Termination Device CCIO = 50 Ω Table 7–8 lists I/O standards that support OCT R with calibration. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 226: Expanded On-Chip Series Termination With Calibration
25- Ω OCT R with calibration setting in the Quartus II software to get the closest timing and IBIS model information. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 227: Left Shift Series Termination Control
I/O with 25- Ω calibrated OCT R and 50- Ω parallel OCT. For more information about how to enable left shift series termination in the ALTIOBUF megafunction, refer to the ALTIOBUF Megafunction User Guide. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 228: On-Chip Parallel Termination With Calibration
Differential SSTL-18 Class I, II Ω Differential SSTL-15 Class I, II Ω Differential HSTL-18 Class I, II Ω Differential HSTL-15 Class I, II Ω Differential HSTL-12 Class I, II Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 229: Dynamic Oct
= 50 Transmitter Stratix III OCT Stratix III OCT For more information about tolerance specifications for OCT with calibration, refer to DC and Switching Characteristics of Stratix III Devices chapter. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 230: Lvds Input On-Chip Termination
HSTL/SSTL standards as Series 25 Ω with calibration well as differential HSTL/SSTL Series 40 Ω with calibration standards. Series 50 Ω with calibration Series 60 Ω with calibration Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 231: Oct Calibration
Note to Figure 7–13: Figure 7–13 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 232: Figure 7-14: Oct Calibration Block (Cb) Location In Ep3Sl110, Ep3Sl150, Ep3Se80, And Ep3Se110 Devices
Note to Figure 7–15: Figure 7–15 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 233: Sharing An Oct Calibration Block In Multiple I/O Banks
Power-Up Mode In power-up mode, OCT calibration is automatically performed at power up and calibrated codes are shifted to selected I/O buffers before transitioning to user mode. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 234: User Mode
Note to Figure 7–17: Figure 7–17 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 235: Oct Calibration
7–19, when nCLRUSR is set to 0 for the second time to initialize OCT calibration block 0, this does not affect OCT calibration block 1, whose calibration is already in progress. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 236: Rs Calibration
). The reference voltage of the receiving device tracks the termination voltage of the transmitting device. Figure 7–20 Figure 7–21 show the details of SSTL and HSTL I/O termination on Stratix III devices. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 237: Figure 7-20: Sstl I/O Standard Termination For Stratix Iii Devices
Stratix III Note to Figure 7–20: (1) In Stratix III devices, series and parallel OCT cannot be used simultaneously. For more information, refer to “Dynamic OCT” on page 7–25. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 238: Differential I/O Standards Termination
I/O termination on Stratix III devices. Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as inverted. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 239: Figure 7-22: Differential Sstl I/O Standard Termination For Stratix Iii Devices
100 Ω 100 Ω V TT V CCIO V CCIO 50 Ω 100 Ω 100 Ω = 50 Ω = 50 Ω 100 Ω 100 Ω Receiver Receiver Transmitter Transmitter © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 240: Lvds
=120 Ω for LVDS_E_3R. (1) R (2) Row I/O banks support true LVDS output buffers. (3) Column and row I/O banks support LVDS_E_1R and LVDS_E_3R I/O standards using two single-ended output buffers. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 241: Differential Lvpecl
= 50 = 50 0.1 F Note to Figure 7–25: (1) The LVPECL AC-coupled termination is applicable only when an Altera FPGA LVPECL transmitter is used. Figure 7–26. LVPECL DC Coupled Termination (Note 1) Stratix III LVPECL LVPECL Input Buffer...
Page 242: Mini-Lvds
50Ω ------------------- - ----- - Altera recommends that you perform additional simulations using IBIS models to validate that custom resistor values meet the RSDS requirements. For more information about the RSDS I/O standard, refer to the RSDS Specification from the National Semiconductor website.
Page 243: Design Considerations
------------------- - 50Ω ----- - Altera recommends that you perform additional simulations using IBIS models to validate that custom resistor values meet the RSDS requirements. For more information about the mini-LVDS I/O standard, refer to the mini-LVDS Specification from the Texas Instruments website.
Page 244: I/O Termination
CCIO For example, an I/O bank with a 2.5-V V setting can support 2.5-V standard inputs CCIO and outputs and 3-V LVCMOS inputs (not output or bi-directional pins). Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 245: Voltage-Referenced Standards
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs), and HSTL and HSTL-15 I/O standards with a 1.5-V V and 0.75-V V CCIO For pin connection guidelines, refer to the Stratix III Device Family Pin Connection Guidelines. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 246: Chapter Revision History
“RSDS”, “mini-LVDS”, “Voltage-Referenced Standards”, “Stratix III I/O Banks”, “MultiVolt I/O Interface”, and “On-Chip Parallel Termination with Calibration” sections. Updated Figure 7–1. ■ Added Table 7–3. ■ Updated New Document Format. ■ Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 247 Updated “LVDS Input On-Chip Termination (RD)” on page 7–29. ■ May 2007 Updated Figure 7–3 through Figure 7–7. ■ Updated Figure 7–23, Figure 7–24. ■ Minor text edits to page 14. ■ November 2006 Initial Release. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 248 7–44 Chapter 7: Stratix III Device I/O Features Chapter Revision History Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 249 While this chapter describe the silicon capability of Stratix III devices, for more information about the external memory system specifications, implementation, board guidelines, timing analysis, simulation, and design debugging, refer to the Literature: External Memory Interfaces section of the Altera website. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 250: Figure 8-1: Package Bottom View For Stratix Iii Devices
(1) The number of I/O banks and PLLs available depends on the device density. (2) There is only one PLL in the center of each side of the device in EP3SL50, EP3SL70, and EP3SE50 devices. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 251: Memory Interfaces Pin Support
This section describes how Stratix III devices support all these different pins. For more information on memory interfaces, refer to the Stratix III Pin Connection Guidelines. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 252: Data And Data-Strobe/Clock Pins
I/Os. In addition, you can use any DQSn or CQn pins not used for clocking as DQ (data) pins. Table 8–1 lists pin support per DQS/DQ bus mode, including the DQS/CQ and DQSn/CQn pin pair. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 253: Using Rup /Rdn Pins In A Dqs/Dq Group Used For Memory Interfaces
×32/×36 DQS/DQ groups that include the ×4 groups whose pin members are being used as RUP and RDN pins, because there are enough extra pins that you can use as DQS pins. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 254: Table 8-2: Number Of Dqs/Dq Groups In Stratix Iii Devices Per Side
Left/ Right 1517-pin FineLine BGA Top/ Bottom Left/ Right 780-pin Hybrid FineLine BGA Top/ Bottom Left/ Right EP3SE260 1152-pin FineLine BGA Top/ Bottom Left/ Right 1517-pin FineLine BGA Top/ Bottom Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 255 (2) To interface with a ×36 QDR II+/QDR II SRAM device in a Stratix III FPGA that does not support the ×32/×36 DQS/DQ group, refer to the Device, Pin, and Board Layout Guidelines in volume 2 of the External Memory Interface Handbook. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 256: Figure 8-3: Number Of Dqs/Dq Groups Per Bank In Ep3Se50, Ep3Sl50, And Ep3Sl70 Devices In The 484-Pin Fineline Bga Package (Note 1)
(3) Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your configuration scheme. (4) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 257: Figure 8-4: Number Of Dqs/Dq Groups Per Bank In Ep3Se50, Ep3Sl50, Ep3Sl70, Ep3Se80, Ep3Se110
(3) Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your configuration scheme. (4) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n). © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 258: Figure 8-5: Number Of Dqs/Dq Groups In Ep3Se80, Ep3Se110, Ep3Sl110, Ep3Sl150, Ep3Sl200
(3) Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your configuration scheme. (4) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n). Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 259: Figure 8-6: Number Of Dqs/Dq Groups Per Bank In Ep3Sl200, Ep3Se260 And Ep3Sl340 Devices In The
(3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, and PLL_R1_CLKn) that can be used for data inputs. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 260: Figure 8-7: Dqs/Dq Bus Mode Support Per Bank In Ep3Sl340 Devices In The 1760-Pin Fineline Bga Pack
(3) Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your configuration scheme. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 261 The parity, DM, BWSn, NWSn, ECC, and QVLD pins are shown as DQ pins in the pin table. When not used as memory interface pins, these pins are available as regular I/O pins. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 262: Figure 8-8: Dqs Pins In Stratix Iii I/O Banks
10 DQ pins (including parity or DM and QVLD pins) and a pair of DQS and DQSn/CQn pins. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 263: Combining ×16/×18 Dqs/Dq Groups For ×36 Qdr Ii+/Qdr Ii Sram Interface
Other QDR II+/QDR II SRAM interface rules for Stratix III devices also apply for this implementation. Altera’s ALTMEMPHY megafunction does not use the QVLD signal, so you can leave the QVLD signal unconnected as in any QDR II+/QDR II SRAM interfaces in the Stratix III devices.
Page 264: Table 8-4: I/O Sub-Bank Combinations For Stratix Iii Devices That Do Not Have ×36 Groups To Form Two ×36
Similarly, crossing a bank number (for example combining groups from I/O banks 6C and 5C) is not supported in this package. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 265: Optional Parity, Dm, Bwsn, Nwsn, Ecc And Qvld Pins
There is no special circuitry required for the address and control/command pins. You can use any of the user I/O pins in the same I/O bank as the data pins. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 266: Memory Clock Pins
This section describes each Stratix III device feature that is used in external memory interfaces from the DQS phase-shift circuitry, DQS logic block, leveling multiplexers, dynamic OCT control block, IOE registers, IOE features, and PLLs. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 267: Dqs Phase-Shift Circuitry
® instantiated for you. The ALTMEMPHY megafunction and the Altera memory controller MegaCore functions can run at half the frequency of the I/O interface of the memory devices to allow better timing management in high-speed memory interfaces. Stratix III devices have built-in registers to convert data from full-rate (I/O frequency) to half-rate (controller frequency) and vice versa.
Page 268: Figure 8-10: Dqs And Cqn Pins And Dqs Phase-Shift Circuitry (Note 1)
DQS phase-shift circuitry is connected to the DQS logic blocks that control each DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be updated concurrently at every DQS/CQ or CQn pin. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 269: Dll
Stratix III device to have eight different DLL phase shift settings. Figure 8–11 shows the DLL and I/O bank locations in Stratix III devices from a package bottom view. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 270: Figure 8-11: Stratix Iii Dll And I/O Bank Locations (Package Bottom View)
DQS1L can get its phase-shift settings from DLL0, while DQS2L can get its phase-shift settings from DLL1. Table 8–5 lists the DLL location and supported I/O banks for Stratix III devices. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 271: Table 8-5: Dll Location And Supported I/O Banks
DLL1 PLL_B1 PLL_L2 CLK6P CLK2P CLK7P CLK3P CLK4P CLK8P CLK5P CLK9P DLL2 PLL_B1 PLL_R2 CLK6P CLK10P CLK7P CLK11P CLK12P CLK8P CLK13P CLK9P DLL3 PLL_T1 PLL_R2 CLK14P CLK10P CLK15P CLK11P © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 272: Table 8-8: Dll Reference Clock Input For Ep3Se80, Ep3Se110, Ep3Sl110, And Ep3Sl150 Devices In The
DLL1 PLL_B1 PLL_L3 CLK6P CLK2P CLK7P CLK3P CLK4P CLK8P CLK5P CLK9P DLL2 PLL_B2 PLL_R3 CLK6P CLK10P CLK7P CLK11P CLK12P CLK8P CLK13P CLK9P DLL3 PLL_T2 PLL_R2 CLK14P CLK10P CLK15P CLK11P Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 273: Table 8-9: Dll Reference Clock Input For Ep3Sl200, Ep3Se260 And Ep3Sl340 Devices
6-bit delay setting (DQS delay settings) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay element chain in phase. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 274: Figure 8-12: Simplified Diagram Of The Dqs Phase Shift Circuitry (Note 1)
In frequency modes 4, 5, 6, and 7, only 5 bits of the DQS delay settings vary with PVT to implement a phase-shift delay; the most significant bit of the DQS delay setting is set to 0. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 275: Phase Offset Control
64 for frequency modes 0, 1, 2, and 3, and setting 32 for frequency modes 4, 5, 6, and 7 so the actual physical offset setting range is 64 or 32 subtracted by the DQS delay settings from the DLL. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 276 When you want to both add and subtract dynamically, you control the addnsub signal in addition to the dll_offset[5..0] signals. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 277: Dqs Logic Block
The amount of delay is equal to the sum of the delay element’s intrinsic delay and the product of the number of delay steps and the value of the delay steps. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 278: Update Enable Circuitry
In addition to the dedicated postamble register, Stratix III devices also have an HDR block inside the postamble enable circuitry. These registers are used if the controller is running at half the frequency of the I/Os. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 279: Leveling Circuitry
The difference in arrival time between the first DDR3 SDRAM device and the last device on the module can be as long as 1.6 ns. Figure 8–16 shows the clock topology in DDR3 SDRAM unbuffered modules. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 280: Figure 8-16: Ddr3 Sdram Unbuffered Module Clock Topology
(1) There is only one leveling delay chain per I/O bank with the same I/O number (for example, I/O banks 1A, 1B, and 1C). You can only have one memory controller in these I/O banks when you use leveling delay chains. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 281: Dynamic Oct Control
OCT R during a read and turn OCT R off during a write. For more information about dynamic OCT control, refer to the Stratix III Device I/O Features chapter. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 282: Ioe Registers
Stratix III input path. The input path consists of the DDR input registers, resynchronization registers, and HDR block. You can bypass each block of the input path. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 283: Figure 8-20: Stratix Iii Ioe Input Registers (Note 1)
Figure 8–20. Stratix III IOE Input Registers (Note 1) DDR Input Registers Input Reg A neg_reg_out directin Differential Half Data Rate Registers Alignment & Synchronization Registers Input Reg C Input Input Reg B DQS/CQ (3), (9) Buffer To Core DQSn (9) dataout[2] (7) CQn (4) datain [0]...
Page 284 (8) You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data rate register to feed dataout. (9) You must invert the strobe signal needs for DDR, DDR2, and DDR3 interfaces, except for QDR II or QDR II+ SRAM interfaces. This inversion is automatically done if you use the Altera external memory interface IPs.
Page 285 Stratix III output and output-enable paths. The path is divided into the HDR block, resynchronization registers, and output/output-enable registers. The device can bypass each block of the output and output-enable path. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 286: Figure 8-21: Stratix Iii Ioe Output And Output-Enable Path Registers (Note 1)
Figure 8–21. Stratix III IOE Output and Output-Enable Path Registers (Note 1) Half Data Rate to Single Data Rate Output-Enable Registers Alignment Registers (4) From Core (2) Double Data Rate Output-Enable Registers From Core (2) OE Reg A Half Data Rate to Single Data Rate Output Registers Alignment Registers (4) OE Reg B From Core (wdata0) (2)
Page 287: Delay Chain
One delay chain between the input buffer and input register ■ ■ Two delay chains between the output enable and output buffer ■ Two delay chains between the OCT R enable control register and output buffer © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 288: Figure 8-22: Delay Chain
Figure 8–24. Delay Chains in the DQS Input Path (dqsbusoutdelaysetting + dqsbusoutfinedelaysetting) Enable Delay D4 Delay dqsin dqsbusout Chain Chain dqsenable T11 Delay (dqsenabledelaysetting + Chain dqsenablefinedelaysetting) Enable Control Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 289: I/O Configuration Block And Dqs Configuration Block
I/O configuration block bit sequence. Table 8–11. I/O Configuration Block Bit Sequence Bit Name 0..3 outputdelaysetting1[0..3] 4..6 outputdelaysetting2[0..2] 7..10 padtoinputregisterdelaysetting[0..3] outputfinedelaysetting1 outputfinedelaysetting2 padtoinputregisterfinedelaysetting outputonlyfinedelaysetting2 15..17 outputonlydelaysetting2[2..0] dutycyclecorrectionmode 19..22 dutycyclecorrectionsetting[3..0] © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 290: Ioe Features
For more information about the features listed below, refer to the Stratix III Device I/O Features chapter. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 291: Oct
Use this delay chain to add delay to the data and data clock/strobe to better match the memory system clock delay. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 292: Programmable Slew Rate Control
The VCO and counter setting combinations may be limited for high-performance memory interfaces. For more information about the Stratix III PLL, refer to the Clock Networks and PLLs in Stratix III Devices chapter. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 293: Chapter Revision History
■ Added new “Supporting ×36 QDR II+/QDR II SRAM Interfaces in the F780 ■ and F1152-Pin Packages” section. Updated “Data and Data Clock/Strobe Pins”. ■ Updated “Referenced Documents”. ■ © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 294 Added memory support information for -4L in Table 8–1, Table 8–8, ■ Table 8–10, and Table 8–11. Added new material to section “Phase Offset Control” on page 8–32. ■ November 2006, Initial Release. — version 1.0 Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 295 For high-speed differential interfaces, Stratix III devices support the following differential I/O standards: Low voltage differential signaling (LVDS) ■ ■ Mini-LVDS ■ Reduced swing differential signaling (RSDS) ■ High-speed Transceiver Logic (HSTL) Stub Series Terminated Logic (SSTL) ■ © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 296: I/O Banks
(5) Row I/O supports PCI/PCI-X without on-chip clamping diodes. (6) The PLL blocks are shown for location purposes only and are not considered additional banks. The PLL input and output uses the I/Os in adjacent banks. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 297: Lvds Channels
(4) The EP3SL200 and EP3SL260 FPGAs are offered in the H780 package, instead of the F780 package. (5) The EP3SL340 FPGA is offered in the H1152 package, instead of the F1152 package. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 298: Differential Transmitter
×6, ×7, ×8, ×9, or ×10 with the Quartus II software. The load enable signal is derived from the serialization factor setting. Figure 9–2 shows a block diagram of the Stratix III transmitter. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 299: Figure 9-2: Transmitter Block Diagram For Stratix Iii Devices
Stratix III transmitter in clock output mode. Figure 9–3. Transmitter in Clock Output Mode for Stratix III Devices Transmitter Circuit Parallel Series Txclkout+ Txclkout– Internal Logic diffioclk PLL_Lx / PLL_Rx load_en © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 300: Differential Receiver
IOE can come from any routing resource, from the left/right PLLs or from the top/bottom PLLs. Figure 9–5 shows the block of the Stratix III receiver. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 301: Receiver Data Realignment Circuit (Bit Slip)
The minimum low time between pulses is one period of parallel clock ■ There is no maximum high or low time Valid data is available two parallel clock cycles after the rising edge of ■ RX_CHANNEL_DATA_ALIGN © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 302: Dynamic Phase Aligner (Dpa)
You can prevent the DPA from selecting a new clock phase by asserting the optional RX_DPLL_HOLD port, which is available for each channel. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 303: Soft-Cdr Mode
PLL to track parts per million (PPM) differences between the reference clock and incoming data. In Stratix III devices, you can use every LVDS channel in soft-CDR mode and can drive the core via the PCLK network. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 304: Synchronizer
RX_DPA_LOCKED signal gets asserted and before valid data is received. For more information about how to use the differential receiver, refer to the ALTLVDS Megafunction User Guide. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 305: Programmable Pre-Emphasis And Programmable V
The default setting is medium low. In the Quartus II Assignment Editor, programmable V settings are represented in numbers with 0 (low), 1 (medium low), 2 (medium high) and 3 (high). © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 306: Differential I/O Termination
Clock switchover and dynamic left/right PLL reconfiguration is available in high-speed differential I/O support mode. For more information, refer to the Clock Network and PLLs in Stratix III Devices chapter. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 307: Figure 9-12: Pll Block Diagram For Stratix Iii Devices
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal or general purpose I/O pin cannot drive the PLL. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 308: Clocking
PLL_L1 LVDS LVDS Clock Clock Clock Clock Quadrant Quadrant Center Center PLL_L2 PLL_R2 Center Center PLL_L3 PLL_R3 Quadrant Quadrant LVDS LVDS Clock Clock Clock Clock Corner Corner PLL_L4 PLL_R4 Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 309: Source-Synchronous Timing Budget
Implemented in hard SERDES ■ For other serialization factors, use the Quartus II software tools and find the bit position within the word and the bit positions after deserialization. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 310: Figure 9-16: Bit-Order And Word Boundary For One Differential Channel (Note 1)
The MSB and LSB positions increase with the number of channels used in a system. Table 9–3. Differential Bit Naming (Part 1 of 2) Internal 8-Bit Parallel Data Receiver Channel Data Number MSB Position LSB Position Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 311: Receiver Skew Margin For Non-Dpa
For instance, the receiver skew is why each input with DPA selects a different phase of the clock, thus removing the requirement for this margin. In the timing diagram, TSW represents time for the sampling window. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 312: Figure 9-17: Differential High-Speed Timing Diagram And Timing Budget For Non-Dpa
(max) Bit n Clock Bit n Falling Edge Timing Budget External Clock Clock Placement Internal Clock Synchronization Transmitter Output Data RSKM RSKM TCCS TCCS Receiver Input Data Sampling Window Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 313: Differential Pin Placement Guidelines
CCIO DPA-Enabled Channel Driving Distance If the number of DPA channels driven by each left/right PLL exceeds 25 LAB rows, Altera recommends implementing data realignment (bit-slip) circuitry for all the DPA channels. Using Corner and Center Left/Right PLLs If a differential bank is being driven by two left/right PLLs, where the corner...
Page 314: Figure 9-18: Corner And Center Left/Right Plls Driving Dpa-Enabled Differential I/Os In The Same Bank
Diff I/O Channel for Buffer DPA-enabled Diff I/O DPA-enabled Diff I/O Channels DPA -enabled driven by Diff I/O Center Left/Right DPA- enabled Diff I/O Reference Center Left /Right PLL Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 315: Using Both Center Left/Right Plls
Left/Right PLL (PLL_L3/PLL_R3) (PLL_L3/PLL_R3) Reference Reference DPA-enabled DPA-enabled Diff I/O Diff I/O DPA-enabled DPA-enabled Diff I/O Diff I/O DPA-enabled DPA-enabled Diff I/O Diff I/O DPA-enabled DPA-enabled Diff I/O Diff I/O © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 316: Figure 9-20: Invalid Placement Of Dpa-Enabled Differential I/Os Driven By Both Center Left/Right Plls
DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O Reference Center Left /Right Center Left /Right Reference DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 317: Guidelines For Dpa-Disabled Differential Channels
PLL are not interleaved. No separation is necessary between the group of channels driven by the corner and center left/right PLLs. Refer to Figure 9–21 Figure 9–22. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 318: Figure 9-21: Corner And Center Left/Right Plls Driving Dpa-Disabled Differential I/Os In The Same Bank
Diff RX Diff TX Diff I/O driven by DPA-disabled Center Diff RX Diff TX Diff I/O Left/Right DPA-disabled Diff RX Diff TX Diff I/O Reference Reference Center Left/Right Center Left/Right Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 319: Figure 9-22: Invalid Placement Of Dpa-Disabled Differential I/Os Due To Interleaving Of Channels Driven
Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Reference CLK Center Left/Right © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 320: Using Both Center Left/Right Plls
DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Reference Center Left/Right PLL Center Left/Right PLL Reference DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 321: Chapter Revision History
Minor edits to “DPA-Enabled Channel Driving Distance” section. ■ Minor changes to second paragraph of the section “Differential I/O ■ Termination”. May 2007 Added Table 9–1 and Table 9–2. ■ November 2006 Initial release. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 322 9–28 Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Chapter Revision History Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 323: Chapter Iii. Hot Socketing, Configuration, Remote Upgrades, And Testing
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 324 III–2 Section III: Hot Socketing, Configuration, Remote Upgrades, and Testing Revision History Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 325: Stratix Iii Hot-Socketing Specifications
Stratix III devices before or during power up or power down without damaging the device. Stratix III devices support power up or power down of the power supplies in any sequence in order to simplify system-level design. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 326: I/O Pins Remain Tri-Stated During Power Up
Switching Characteristics of Stratix III Devices chapter and the Hot-Socketing and Power-Sequencing Feature and Testing for Altera Devices White Paper. A possible concern regarding hot socketing is the potential for “latch-up”. Nevertheless, Stratix III devices are immune to latch-up when hot socketing. Latch-up can occur when electrical subsystems are hot socketed into an active system.
Page 327: Figure 10-1: Hot-Socketing Circuitry For Stratix Iii Devices
CCPGM I/O pins from driving out when the device is not in user mode. Altera uses GND as reference for hot-socketing operation and I/O buffer designs. To ensure proper operation, you must connect the GND between boards before connecting the power supplies. This will prevent the GND on your board from being pulled up inadvertently by a path to power through other components on your board.
Page 328: Power-On Reset Circuitry
POR block for the final POR trip. A simplified block diagram of the POR block is shown in Figure 10–3. All configuration-related dedicated and dual function I/O pins must be powered by CCPGM Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 329: Power-On Reset Specifications
1.8, 2.5, 3.0, 3.3 C CP GM To ensure proper device operation, all power supplies listed in Table 10–2 are required to be powered up at all times during device operation. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 330: Table 10-3: Power Supplies That Are Not Monitored By The Por Circuitry
PORSEL is set to high, the POR signal pulse width is set to 12 ms. A POR pulse width of 12 ms allows time for power supplies to ramp-up to full rail. For more information about the POR specification, refer to the DC and Switching Characteristics chapter. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 331: Chapter Revision History
October 2007 Added live links for references. ■ All instances of VCCR changed to VCCPT in text, and in Figure 10–3, and May 2007 Table 10–1. November 2006 Initial Release. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 332 10–8 Chapter 10: Hot Socketing and Power-On Reset in Stratix III Devices Chapter Revision History Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 333: Chapter 11. Configuring Stratix Iii Devices
To avoid any problems with detecting an incorrect configuration scheme, hard-wire the MSEL[] pins to V and GND, without any pull-up or pull-down resistors. Do CCPGM not drive the MSEL[] pins with a microprocessor or another device. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 334: Table 11-1: Stratix Iii Configuration Schemes
For more information about setting device configuration options or creating configuration files, refer to the Device Configuration Options Configuration File Formats chapters in volume 2 of the Configuration Handbook. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 335: Configuration Features
For more information about PFL, refer to AN 386: Using the MAX II Parallel Flash Loader with the Quartus II Software. For more information about programming Altera serial configuration devices, refer to “Programming Serial Configuration Devices” on page 11–25. © March 2011 Altera Corporation...
Page 336: Configuration Data Decompression
2. In the Family list, select Stratix III and then click the Device and Pin Options button. 3. On the Configuration tab, turn on the Generate compressed bitstreams option(Figure 11–1). Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 337: Figure 11-1: Enabling Compression For Stratix Iii Bitstreams In Compiler Settings
Stratix III devices in the chain must either enable or disable the decompression feature. You cannot selectively enable the compression feature for each device in the chain because of the DATA and DCLK relationship. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 338: Design Security Using Configuration Bitstream Encryption
Stratix III device that has neither the design security nor the decompression feature enabled. For more information about this feature, refer to the Design Security in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 339: Remote System Upgrade
For more information about the configuration pins power supply, refer to “Device Configuration Pins” on page 11–43. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 340: Fast Passive Parallel Configuration
The maximum DCLK frequency is 100 MHz, which results in a maximum data rate of 200 Mbps. If you are not using the Stratix III decompression or design security features, the data rate is the same as the DCLK frequency. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 341: Figure 11-3: Single Device Fpp Configuration Using An External Host
DCLK cycle. After the configuration data is latched in, it is processed during the following three DCLK cycles. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 342 Stratix III device. If you are using the Stratix III device without decompression or design security feature, the DCLK can only be stopped two clock cycles after the last data byte was latched into the Stratix III device. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 343 CONF_DONE low and all I/O pins are tri-stated. After nCONFIG returns to a logic high level and nSTATUS is released by the device, reconfiguration begins. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 344: Figure 11-4: Multi-Device Fpp Configuration Using An External Host
If this option is turned off, the MAX II device must generate a low-to-high transition (with a low pulse of at least 2 μs) on nCONFIG to restart the configuration process. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 345: Figure 11-5: Multiple-Device Fpp Configuration Using An External Host When Both Devices Receive The
You can use a single configuration chain to configure Stratix III devices with other Altera devices that support FPP configuration, such as other types of Stratix devices. To ensure that all devices in the chain complete configuration at the same time, or that an error flagged by one device initiates reconfiguration in all devices, tie all of the device CONF_DONE and nSTATUS pins together.
Page 346: Fpp Configuration Timing
— ST2C K Data setup time before rising edge on DCLK — Data hold time after rising edge on DCLK — DCLK high time — DCLK low time — Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 347: Figure 11-7: Fpp Configuration Timing Waveform With Decompression Or Design Security Feature En
(7) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to sending the first DCLK rising edge. (8) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 348: Fpp Configuration Using A Microprocessor
“FPP Configuration Using a MAX II Device as an External Host” on page 11–8 is also applicable when using a microprocessor as an external host. Refer to this section for all configuration and timing information. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 349: Fast Active Serial Configuration (Serial Configuration Devices)
Serial configuration devices have a four-pin interface: serial clock input (DCLK), serial data output (DATA), AS data input (ASDI), and an active-low chip select (nCS). This four-pin interface connects to Stratix III device pins, as shown in Figure 11–8. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 350: Figure 11-8: Single Device Fast As Configuration
DCLK. The serial configuration device responds to the instructions by driving out configuration data on the falling edge of DCLK. Then the data is latched into the Stratix III device on the following falling edge of DCLK. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 351 (maximum of 100 μs), and retries configuration. If this option is turned off, the system must monitor nSTATUS for errors and then pulse nCONFIG low for at least 2 μs to restart configuration. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 352 The remaining Stratix III devices are configuration slaves. You must connect their MSEL pins to select the PS configuration scheme. Any other Altera device that supports PS configuration can also be part of the chain as a configuration slave.
Page 353: Figure 11-9: Multi-Device Fast As Configuration
10 μs to a maximum pulse width of 500 μs, as defined in the t specification. STATUS While you can cascade Stratix III devices, you cannot cascade or chain together serial configuration devices. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 354 During the configuration cycle, the master device reads its configuration data from the serial configuration device and transmits the second copy of the configuration data to all three slave devices, configuring all of them simultaneously. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 355: Estimating Active Serial Configuration Time
RBF Size × (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum configuration time Example 11–1. 15 Mbits × (25 ns / 1 bit) = 375 ms © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 356: Figure 11-11: Fast As Configuration Timing
— Data hold time after falling edge on DCLK — — DCLK high time — — DCLK low time — — μs CONF_DONE high to user mode — CD2UM Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 357: Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash-memory-based devices. You can program these devices in-system using the USB-Blaster™ or ByteBlaster™ II download cable. Alternatively, you can program them using the Altera programming unit (APU), supported third-party programmers, or a microprocessor with the SRunner software driver.
Page 358: Figure 11-12: In-System Programming Of Serial Configuration Devices
In production environments, you can program serial configuration devices using multiple methods. You can use Altera programming hardware or other third-party programming hardware to program blank serial configuration devices before they are mounted onto PCBs. Alternatively, you can use an on-board microprocessor to program the serial configuration device in-system using C-based software drivers provided by Altera.
Page 359: Passive Serial Configuration
CCPGM high enough to meet the V specification of the I/O on the external host. It is recommended to power up all configuration systems’ I/O with V CCPGM © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 360 . After this time period elapses, Stratix III devices require 4,436 clock CD2CU cycles to initialize properly and enter user mode. Stratix III devices support a CLKUSR of 100 MHz. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 361 If you use the optional CLKUSR pin and nCONFIG is pulled low to restart configuration during device initialization, you must ensure that CLKUSR continues toggling during the time nSTATUS is low (maximum of 100 µs). © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 362: Figure 11-14: Multi-Device Ps Configuration Using An External Host
For example, if the first device flags an error on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This behavior is similar to a single device detecting an error. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 363: Figure 11-15: Multiple-Device Ps Configuration When Both Devices Receive The Same Data
You can use a single configuration chain to configure Stratix III devices with other Altera devices. To ensure that all devices in the chain complete configuration at the same time, or that an error flagged by one device initiates reconfiguration in all devices, all of the device CONF_DONE and nSTATUS pins must be tied together.
Page 364: Ps Configuration Timing
Data hold time after rising edge on DCLK — DCLK high time — DCLK low time — DCLK period — DCLK frequency — M AX Input rise time — Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 365: Ps Configuration Using A Microprocessor
PS Configuration Using a Download Cable In this section, the generic term download cable includes the Altera USB-Blaster USB port download cable, MasterBlaster™ serial/USB communications cable, ByteBlaster II parallel port download cable, ByteBlasterMV™ parallel port download cable, and the EthernetBlaster download cable.
Page 366 Quartus II programmer and a download cable. Figure 11–17 shows PS configuration for Stratix III devices using a USB-Blaster, MasterBlaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 367: Figure 11-17: Ps Configuration Using A Download Cable
The Auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the Quartus II software when an error occurs. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 368: Figure 11-18: Multi-Device Ps Configuration Using A Download Cable
MasterBlaster Serial/USB Communications Cable User Guide ■ ■ ByteBlaster II Parallel Port Download Cable User Guide ■ ByteBlasterMV Parallel Port Download Cable User Guide ■ EthernetBlaster Download Cable User Guide Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 369: Jtag Configuration
JTAG chain with multiple voltages across the devices in the chain, refer to the IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Devices chapter of the Stratix III Device Handbook. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 370: Table 11-11: Dedicated Jtag Pins
. This ensures that CCPD the TAP controller is not reset. The JRunner™ software driver is developed to configure Altera FPGA devices in JTAG mode through the ByteBlaster II or ByteBlasterMV download cables for embedded configurations. For more information, refer to...
Page 371: Figure 11-19: Jtag Configuration Of A Single Device Using A Download Cable
If CONF_DONE is high, the software indicates that configuration was successful. After the configuration bitstream is transmitted serially through the JTAG TDI port, the TCK port is clocked an additional 1,094 cycles to perform device initialization. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 372: Table 11-12: Dedicated Configuration Pin Connections During Jtag Configuration
The number of devices in the JTAG chain is limited only by the drive capability of the download cable. When four or more devices are connected in a JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board buffer.
Page 373: Figure 11-20: Jtag Configuration Of Multiple Devices Using A Download Cable
When the CONF_DONE and nSTATUS signals are shared among all the devices, you must configure every device when JTAG configuration is performed. If you only use JTAG configuration, Altera recommends that you connect the circuitry as shown in Figure 11–20, where each of the CONF_DONE and nSTATUS signals are...
Page 374: Figure 11-21: Jtag Configuration Of A Single Device Using A Microprocessor
Chapter 11: Configuring Stratix III Devices JTAG Configuration You can place other Altera devices that have JTAG support in the same JTAG chain for device programming and configuration. JTAG configuration support has been enhanced and allows more than 17 Stratix III devices to be cascaded in a JTAG chain.
Page 375: Jam Stapl
For more information about JTAG and Jam STAPL in embedded environments, refer AN 425: Using Command-Line Jam STAPL Solution for Device Programming. To download the jam player, visit the Altera web site at www.altera.com. Device Configuration Pins The following tables describe the connections and functionality of all the configuration-related pins on the Stratix III devices.
Page 376: Table 11-14: Dedicated Configuration Pins On The Stratix Iii Device
The PORSEL input buffer is powered by VCCPGM and has an internal 5-kΩ pull-down resistor that is always active. You should tie the PORSEL pin directly to VCCPGM or GND. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 377 Returning this pin to a logic high level will initiate a Input nCONFIG reconfiguration. Configuration is possible only if this pin is high, except in JTAG programming mode when nCONFIG is ignored. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 378 When POR trips after V and V CC PGM C CIO are powered up, nSTATUS is released and pulled high. At that point, reconfiguration is triggered and the device is configured. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 379 Output control signal from the Stratix III device to the serial configuration device in AS mode that enables the configuration device. Output nCSO In AS mode, nCSO has an internal pull-up resistor that is always active. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 380 To set Data0 to a different setting, for example to use Data0 pin as a regular I/O in user mode, turn off Enable input tri-state on active configuration pins in user mode option and set your desired setting from the Dual-purpose Pins Setting menu. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 381: Table 11-15: Optional Configuration Pins
When this pin is driven high, all registers Input DEV_CLRn if option is off. behave as programmed. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Quartus II software. © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 382: Table 11-16: Dedicated Jtag Pins
You should hold TMS at 1 or you should keep TCK static while TRST is changed TRST from 0 to 1. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting the TRST pin to GND. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 383: Table 11-17: Chapter Revision History
■ Updated (Note 3) to Figure 11–17. ■ Updated (Note 3) to Figure 11–18. ■ Updated (Note 3) to Figure 11–19. ■ Updated (Note 3) to Figure 11–20. ■ © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 384 Removed text regarding enhanced configuration device support. Removed ■ Figure 11–19. Added live links for references. ■ Added section “Referenced Documents” ■ May 2007 Removed Bank Column from Table 11–13. November 2006 Initial Release Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation...
Page 385 (UDP), universal asynchronous receiver/transmitter (UART), or a proprietary interface. 2. The Nios II processor (or user logic) stores this new configuration data in non-volatile configuration memory. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 386: Figure 12-1: Functional Diagram Of Stratix Iii Remote System Upgrade
For more information about standard configuration schemes supported in Stratix III devices, refer to the Configuring Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 387: Chapter 12. Remote System Upgrades With Stratix Iii Devices Functional Description
4. From the Configuration scheme list, select Active Serial (can use Configuration Device) (Figure 12–3). 5. From the Configuration Mode list, select Remote. (Figure 12–3). 6. Click OK. 7. In the Setting dialog box, click OK. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 388: Configuration Image Types
The factory configuration is written to the serial configuration device only once by the system manufacturer and should not be remotely updated. On the other hand, application configurations may be remotely updated in the system. Both images can initiate system reconfiguration. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 389: Remote System Upgrade Mode
■ ■ Instruct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle Figure 12–4 shows the transitions between the factory and application configurations in remote update mode. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 390: Figure 12-4: Transitions Between Configurations In Remote Update Mode
Actions that cause the remote system upgrade status register to be written: ■ nSTATUS driven low externally ■ Internal CRC error User watchdog timer time out ■ Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 391: Dedicated Remote System Upgrade Circuitry
The remote system upgrade circuitry contains the remote system upgrade registers, a watchdog timer, and a state machine that controls those components. Figure 12–5 shows the remote system upgrade block's data path. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 392: Remote System Upgrade Registers
When a reconfiguration cycle is initiated, the contents of the update register are written into the control register. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 393: Remote System Upgrade Control Register
Table 12–3. Remote System Upgrade Control Register Contents (Part 1 of 2) Remote System Control Register Bit Value Definition Upgrade Mode Remote update 1'b0 Application not factory AS configuration start address Remote update 24'b0×000000 PGM[23..0] (StAdd[23..0]) © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 394: Remote System Upgrade Status Register
(1) Logic array reconfiguration forces the system to load the application configuration data into the Stratix III device. This occurs after the factory configuration specifies the appropriate application configuration page address by updating the update register. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 395: Remote System Upgrade State Machine
The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. The system uses the timer to detect functional errors after an application configuration is successfully loaded into the Stratix III device. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 396: Quartus Ii Software Support
Quartus II software is for the interface between the remote system upgrade circuitry and the device logic array interface. Using the megafunction block instead of creating your own logic saves design time and offers more efficient logic synthesis and device implementation. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 397: Altremote_Update Megafunction
Figure 12–8. Interface Signals Between the ALTREMOTE_UPDATE Megafunction and the Nios II Processor For more information about the ALTREMOTE_UPDATE Megafunction and the description of ports listed in Figure 12–8, refer to the ALTREMOTE_UPDATE Megafunction User Guide. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 398: Chapter Revision History
“Parameter Settings for the altremote_update Megafunction” in section “altremote_update Megafunction” on page 12–15. Removed “System Design Guidelines Using Remote System Upgrade With Serial Configuration Devices” section. November 2006 Initial Release. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 399: Ieee Std. 1149.1 Bst Architecture
For recommendations about how to connect a JTAG chain with multiple voltages across the devices in the chain, refer to “I/O Voltage Support in JTAG Chain” on page 13–17. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 400: Table 13-1: Ieee Std. 1149.1 Pin Descriptions
TCK. Therefore, you must set up TMS before the rising edge of TCK. TMS is evaluated on the rising edge of TCK. During non-JTAG operation, Altera recommends you drive TMS high. The clock input to the BST circuitry. Some operations occur at the rising edge, while Test clock input others occur at the falling edge.
Page 401: Figure 13-2: Ieee Std. 1149.1 Circuitry
TDO pins provide the serial path for the data registers. The TDI pin also provides data to the instruction register, which then generates control logic for the data registers. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 402: Ieee Std. 1149.1 Boundary-Scan Register
Table 13–2. Stratix III Boundary-Scan Register Length Device Boundary-Scan Register Length EP3SL50 1506 EP3SL70 1506 EP3SL110 2274 EP3SL150ES 2274 EP3SL150 2274 EP3SL200 2970 EP3SL340 3402 EP3SE50 1506 EP3SE80 2274 EP3SE110 2274 EP3SE260 2970 Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 403: Boundary-Scan Cells Of A Stratix Iii Device I/O Pin
Registers Registers PIN_IN INPUT INPUT To or From PIN_OE Device I/O Cell Circuitry and/or Logic Array OUTJ PIN_OUT Output OUTPUT OUTPUT Buffer Global SHIFT CLOCK UPDATE HIGHZ MODE Signals © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 404: Table 13-3: Stratix Iii Device Boundary Scan Cell Descriptions (Note 1)
(2) This includes pins PLL_ENA, nCONFIG, MSEL0, MSEL1, MSEL2, nCE, PORSEL, and nIO_PULLUP. (3) This includes pins CONF_DONE and nSTATUS. (4) This includes pin DCLK. (5) This includes pin nCEO. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 405: Ieee Std. 1149.1 Bst Operation Control
The IEEE Std. 1149.1 TAP controller, a 16-state machine clocked on the rising edge of TCK, uses the TMS pin to control IEEE Std. 1149.1 operation in the device. Figure 13–5 shows the TAP controller state machine. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 406: Figure 13-5: Ieee Std. 1149.1 Tap Controller State Machine
TMS is held high (while TCK is clocked) or TRST is held low. Figure 13–6 shows the timing requirements for the IEEE Std. 1149.1 signals. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 407: Figure 13-6: Ieee Std. 1149.1 Timing Waveforms
SHIFT_IR state is active. The TAP controller remains in the SHIFT_IR state as long as TMS remains low. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 408 The three serially shift test data instruction modes are discussed in the following sections: ■ “SAMPLE/PRELOAD Instruction Mode” on page 13–11 ■ “EXTEST Instruction Mode” on page 13–13 ■ “BYPASS Instruction Mode” on page 13–15 Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 409: Sample/Preload Instruction Mode
UPDATE clock. The data stored in the OUTJ update registers can be used for the EXTEST instruction. Capture Update Registers Registers UPDATE MODE SHIFT CLOCK © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 410: Figure 13-9: Sample/Preload Shift Data Register Waveforms
(1) Data stored in boundary-scan register is shifted out of TDO. (2) After boundary-scan register data has been shifted out, data entered into TDI will shift out of TDO. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 411: Extest Instruction Mode
The update registers OUTJ then drive the PIN_OUT, INJ, and allow the I/O pin to tri-state or drive a signal out. Capture Update Registers Registers UPDATE MODE SHIFT CLOCK © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 412: Figure 13-11: Extest Shift Data Register Waveforms
(1) Data stored in the boundary-scan register is shifted out of TDO. (2) After boundary-scan register data has been shifted out, data entered into TDI will shift out of TDO. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 413: Bypass Instruction Mode
Note to Figure 13–12: (1) Data shifted into TDI on the rising edge of TCK is shifted out of TDO on the falling edge of the same TCK pulse. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 414: Idcode Instruction Mode
TDI and TDO ports. The states of all signals driven from the pins are completely defined by the data held in the boundary-scan register. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 415: Highz Instruction Mode
This way, a level shifter is used only to shift the TDO level to CCIO a level acceptable to the JTAG tester. Figure 13–13 shows the JTAG chain of mixed voltages and how a level shifter is inserted in the chain. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 416: Ieee Std. 1149.1 Bst Circuitry
For more information about using the IEEE Std.1149.1 circuitry for device configuration, refer to the Configuring Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 417: Ieee Std. 1149.1 Bst Circuitry (Disabling)
Do NOT use the following private instructions as they may render the device inoperable: 11 0001 0000 00 1100 1001 11 0001 0011 11 0001 0111 You should take precautions to avoid invoking these instructions at any time. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 418: Boundary-Scan Description Language (Bsdl) Support
ICR, but not during ICR. Use the CONFIG_IO instruction to interrupt configuration and then perform testing, or wait for configuration to complete. ■ If performing testing before configuration, hold the nCONFIG pin low. For more information about boundary scan testing, contact Altera Application at ® www.altera.com.
Page 419: Chapter Revision History
■ May 2007 Removed opening paragraph and footnote for “IEEE Std. 1149.1 BST Operation ■ Control” on page 13–9. Added warning on page 13-22. ■ November 2006 Initial Release. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 420 13–22 Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Chapter Revision History Stratix III Device Handbook, Volume 1 © July 2010 Altera Corporation...
Page 421: Chapter Iv. Design Security And Single Event Upset (Seu) Mitigation
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 422 IV–2 Section IV: Design Security and Single Event Upset (SEU) Mitigation Revision History Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 423: Introduction
The security key is securely stored in the Stratix III device and cannot be read out through any interfaces. In addition, as configuration file read-back is not supported in Stratix III devices, the design information cannot be copied. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 424: Security Against Reverse Engineering
You can program the non-volatile key to the Stratix III device without an external battery. Also, there are no additional requirements to any of the Stratix III power supply inputs. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 425: Stratix Iii Design Security Solution
3. Configure the Stratix III device. At system power-up, the external memory device sends the encrypted configuration file to the Stratix III device. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 426: Security Modes Available
Secure operation in tamper resistant mode with OTP security key programmed—only encrypted configuration bitstreams are allowed to configure the device. Tamper protection disables JTAG configuration with unencrypted configuration bitstream. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 427: No Key Operation
Supported Configuration Schemes Setting the tamper protection bit disables test mode in Stratix III devices. This process is irreversible and prevents Altera from carrying-out failure analysis if test mode is disabled. Contact Altera Technical Support to set the tamper protection bit.
Page 428: Figure 14-2: Stratix Iii Security Modes - Sequence And Restrictions
Remote update fast AS with AES (and/or with decompression) ■ Fast AS (and/or with decompression) ■ Board-level testing with Unencrypted All configuration modes that do not engage the design security feature. non-volatile key Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 429: Table 14-5: Design Security Configuration Schemes Availability
Quartus II software. During configuration, the Stratix III device first decrypts and then decompresses the configuration file. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 430: Conclusion
Updated “Security Modes Available” section. ■ Added new section “Referenced Documents”. ■ October 2007, Minor update version 1.1 Added live links for references. ■ November 2006, Initial Release. — version 1.0 Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation...
Page 431 This section describes how to activate and use the error detection CRC feature when your Stratix III device is in user mode and describes how to recover from configuration errors caused by CRC errors. Information about SEU is located on the Products page of the Altera website at ®...
Page 432: Chapter 15. Seu Mitigation In Stratix Iii Devices
2 to 256 (at powers of 2) to be used as the clock source during the error detection process. Set the clock divide factor in the option setting in the Quartus II software. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 433 MLAB memory blocks, they are ignored during error detection verification. Thus, the CRC_ERROR signal may stay solid high or low depending on the error status of the previous checked CRAM frame. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 434: Table 15-1: Ederror_Inject Jtag Instruction
Quartus II software. For the testing of the CRC detection block with the frequency lower than 50 MHz, contact Altera Technical Support at www.altera.com/support. You can create Jam™ files (.jam) to automate the testing and verification process. This allows you to verify the CRC functionality in-system, on-the-fly, without having to reconfigure the device.
Page 435: Automated Single Event Upset Detection
(1) Bit[20] and Bit[19] cannot both be set to 1 as this is not a valid selection. The error detection circuitry decodes it as no error injection. After the test completes, Altera recommends that you reconfigure the device. Automated Single Event Upset Detection Stratix III devices offer on-chip circuitry for automated checking of single-event upset detection.
Page 436: Error Detection Pin Description
WYSIWYG is a design primitive that corresponds to device features and can be directly instantiated into your RTL design. The CRC_ERROR pin information for Stratix III devices is reported in Device Pin-Outs on the Literature page of the Altera website (www.altera.com). Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 437: Error Detection Block
CRC signature. A non-zero value on the syndrome register causes the CRC_ERROR pin to be set high. Figure 15–1 shows the block diagram of the error detection circuitry, syndrome registers, and error injection block. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 438: Figure 15-1: Error Detection Block Diagram
User Update Register Register is not being written into by the contents of the Error Message Register at exactly the same time that the User Shift Register is reading its contents. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 439: Error Detection Timing
The error detection frequency reflects the frequency of the error detection process for a frame because the CRC calculation in Stratix III devices is done on a per-frame basis. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 440: Table 15-6: Minimum Update Interval For Error Message Register (Note 1)
52.00 14.36 EP3SL70 52.00 14.36 EP3SL110 110.00 30.38 EP3SL150 110.00 30.38 EP3SL200 212.00 58.72 EP3SL260 212.00 58.72 EP3SL340 270.00 74.87 EP3SE50 59.00 16.41 EP3SE80 113.00 31.28 EP3SE110 113.00 31.28 Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 441: Software Support
7. In the Divide error check frequency by box, enter a valid divisor as documented Table 15–5 on page 15–9. The divide value divides the frequency of the configuration oscillator output clock that clocks the CRC circuitry. 8. Click OK. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 442: Recovering From Crc Errors
When the data bit is rewritten with the correct value by reconfiguring the device, the device functions correctly. While soft errors are uncommon in Altera devices, certain high-reliability applications may require a design to account for these errors. Chapter Revision History Table 15–8...
Page 443: Chapter V. Power And Thermal Management
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 444 V–2 Section V: Power and Thermal Management Revision History Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 445: Chapter 16. Programmable Power And Temperature-Sensing Diodes
The following section provides details about Stratix III selectable core voltage and programmable power technology. Selectable Core Voltage Altera offers a series of low-voltage Stratix products that have the ability to power the core logic of the device with either a 0.9-V or 1.1-V power supply. This power supply, called V...
Page 446: Programmable Power Technology
Unused DSP blocks, memory blocks, and I/O elements are set to low-power mode to minimize static power. Clock networks do not support programmable power technology. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 447: Relationship Between Selectable Core Voltage And Programmable Power Technology
Some of the power supply pins can be supplied with the same external power supply, provided they need the same voltage level, as noted in the recommended board connection column. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 448: Table 16-2: Stratix Iii Power Supply Requirements
(3) This scheme is for VCCIO = 2.5 V. (4) There is one VREF pin per I/O bank. Use an external power supply or a resistor divider network to supply this voltage. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 449: Temperature Sensing Diode
Use an external analog-to-digital converter that measures the voltage difference across the TSD and then converts it to a temperature reading. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 450: External Pin Connections
The interfacing device registers temperature based on milivolts of difference as seen at the TSD. Switching I/O near the TSD pins can affect the temperature reading. Altera recommends you take temperature readings during periods of no activity in the device (for example, standby mode where no clocks are toggling in the device), such as when the nearby I/Os are at a DC state and the clock networks in the device are disabled.
Page 451: Chapter Revision History
Added new section “Referenced Documents”. ■ Added live links for references. ■ May 2007, Replaced all instances of VCCR with VCCPT Minor update. version 1.1 November 2006, Initial Release. — version 1.0 © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 452 16–8 Chapter 16: Programmable Power and Temperature-Sensing Diodes in Stratix III Devices Chapter Revision History Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation...
Page 453: Chapter Vi. Packaging Information
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 454 VI–2 Section VI: Packaging Information Revision History Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...
Page 455: Table 17-1: Fineline And Hybrid Fineline Bga Packages For Stratix Iii Devices
17. Stratix III Device Packaging Information SIII51017-1.7 This chapter provides thermal resistance values and package information for Altera ® Stratix III devices, including: ® ■ “Thermal Resistance” on page 17–2 “Package Outlines” on page 17–2 ■ Table 17–1 lists which Stratix III device, are available in FineLine BGA or Hybrid FineLine BGA packages.
Page 456: Thermal Resistance
■ October 2007 Added live links for references. ■ Removed thermal resistance and package outline information and replaced May 2007 with links referencing this information. November 2006 Initial Release. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation...

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Altera Stratix III Series Device Handbook

Table of Contents

List of Figures

Chapter 1. Stratix III Device Family Overview Features Summary

Chapter 2 .Logic Array Blocks and Adaptive Logic Modules in Stratixiii Devices

Chapter 3 .Multitrack Interconnect in Stratixiii Devices

Chapter 4 .Trimatrix Embedded Memory Blocks in Stratixiii Devices

Chapter 5. DSP Blocks in Stratix III Devices

Chapter 6 Plls in Stratix III Devices

Chapter 7. Stratix III Device I/O Features

Chapter 8 External Memory Interfaces

Chapter 9 .High-Speed Differential I/O Interfaces and DPA in Stratix III Devices

Chapter 10 . Hot Socketing and Power-On Reset in Stratix III Devices

Chapter 11. Configuring Stratix III Devices

Chapter 12. Remote System Upgrades with Stratix III Devices Functional Description

Chapter 13 .IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratixiii Devices

Chapter 14. Design Security in Stratix III Devices

Chapter 15. SEU Mitigation in Stratix III Devices

Chapter 16. Programmable Power and Temperature-Sensing Diodes

Chapter 17. Stratix III Device Packaging Information

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Chapters

Summary of Contents for Altera Stratix III Series