Alpha PCI 64-275 Manuals

Manuals and User Guides for Alpha PCI 64-275. We have 1 Alpha PCI 64-275 manual available for free PDF download: Design Manual

Alpha PCI 64-275 Design Manual (198 pages)

Brand: Alpha | Category: Motherboard | Size: 0 MB

Table of Contents
3
Document Content
13
Preface
13
Technical Support
14
Register Field Type Notation
16
Unnamed Register Field Notation
17
Data Units
17
Signal References
18
Alpha PCI 64-275 Introduction
19
System Components and Features
19
Memory Subsystem
20
Decchip 21072 Support Chipset
20
PAL Control Set
20
Alpha PCI 64-275 Functional Block Diagram
21
Level 2 Cache Subsystem Overview
22
Clock Subsystem Overview
22
PCI Interface Overview
22
ISA Interface Overview
22
L2 Cache SIMM Sizes
22
Software Support
23
Board Uses
24
Alpha PCI 64-275 Component Layout and Board Dimensions
25
System Jumpers and Connectors
27
Configuration Jumpers
27
Software Configuration Jumpers
27
Alpha PCI 64-275 Board Jumpers
28
J3 Connector
29
Jumper Position Descriptions
29
Hardware Configuration Jumpers
31
Alpha PCI 64-275 Board Connectors
32
Alpha PCI 64-275 Board Jumpers
32
Alpha PCI 64-275 Board Connectors
33
Module Connector Descriptions (See Figure 2-3)
34
List of Connector and Jumper Part Numbers
39
Functional Description
41
Chipset Introduction
41
21071-CA Introduction
42
Maximum and Minimum SIMM Bank Layouts
43
21071-DA Introduction
44
Basic Cache and Memory Subsystem Address and Data Paths
44
Basic I/O Subsystem Address and Data Paths
45
21071-BA Introduction
47
21071-CA Functional Overview
48
Sysbus Interface
48
Sysbus Arbitration
49
L2 Cache Control
49
Cache Subsystem for an 8MB Cache
49
Sysbus Control
50
Address Decoding
50
Error Handling
50
Memory Controller
51
Memory Organization
51
Memory Address Generation
51
Memory Page Mode Support
51
Read Latency Minimization
51
Transaction Scheduler
52
Programmable Memory Timing
52
Presence Detect Logic
52
21071-DA Functional Overview
53
Decchip 21071-DA Block Diagram
53
Sysbus Interface
54
Address Decode
54
I/O Write Transaction Buffering
54
I/O Read Data Buffering
54
Wrapping Mode
54
PCI Interface
54
DMA Address Translation
54
DMA Write Buffer
55
DMA Read Buffer
55
PCI Burst Length and Prefetching
55
PCI Burst Order
56
PCI Parity Support
56
PCI Exclusive Access
56
PCI Bus Parking
56
PCI Retry Timeout
57
PCI Master Timeout
57
Address Stepping in Configuration Cycles
57
Data Coherency
57
Deadlock Resolution
58
Guaranteed Access-Time Mode
59
Interrupts
59
21071-BA Functional Overview
60
Sysdata Bus
60
Decchip 21071-BA Block Diagram
60
Memdata Bus
61
Epidata Bus
61
Memory Read Buffer
61
I/O Read Buffer and Merge Buffer
61
I/O Write Buffer and DMA Read Buffer
61
DMA Write Buffer
62
Memory Write Buffer
62
Error Checking
62
Epibus Data Path
62
Sysbus Output Selectors
62
Error Handling
63
Clock Subsystem
64
Triquint PLL Clock Oscillator
64
Triquint Clock Generator
64
Triquint Operating Frequencies
64
System Clock Distribution
65
Primary Clock Distribution Network
66
Distribution of 66-Mhz Clock Signals
67
Distribution of 33-Mhz Shifted Clock Signals
67
Buffered Clock Distribution Network
68
Distribution of 33-Mhz Clock Signals
68
PCI Interrupts and Arbitration
69
System Interrupts
69
CPU Interrupt Assignment
69
Interrupt Control and PCI Arbitration
70
PCI/ISA Arbitration
72
Interrupt and Interrupt Mask Registers
72
PCI Devices
73
Intel Saturn IO Chip
73
PCI Expansion Slots
73
PCI Graphics Interface
73
ISA Devices
74
Keyboard and Mouse Controller
74
Combination Controller
75
Time-Of-Year Clock
76
Utility Bus Memory Devices
76
ISA Expansion Slots
77
Serial ROM
77
SROM Serial Port
77
DC Power Distribution
78
Reset and Initialization
78
DC Power Distribution
79
System Software
80
Serial ROM Code
80
System Reset and Initialization
81
Flash ROM Code
82
Operating Systems
82
System Address Mapping
83
CPU Address Mapping to PCI Space
83
Sysbus Address Map
84
Sysbus Address Space Description
85
Cacheable Memory Space (0 0000 0000 to 0 FFFF FFFF)
86
Noncacheable Memory Space (1 0000 0000 to 1 7FFF FFFF)
86
Decchip 21071-CA CSR Space (1 8000 0000 to 1 9FFF FFFF)
87
Tag Enable Register
87
Ldx_L Low Address Register
87
Ldx_L High Address Register
87
Decchip 21071-CA CSR Register Addresses
87
Decchip 21071-DA CSR Space (1 A000 0000 to 1 AFFF FFFF)
89
Host Address Extension Register 0
89
Host Address Extension Register 1
89
Host Address Extension Register 2
89
Decchip 21071-DA CSR Register Addresses
89
Sysbus Error Address Register
89
PCI Error Address Register
89
PCI Interrupt Acknowledge/Special Cycle Space (1 B000 0000 to 1 BFFF FFFF)
90
PCI Sparse I/O Space (1 C000 0000 to 1 DFFF FFFF)
91
PCI Sparse I/O Space Address Translation
92
PCI Sparse I/O Space Byte Enable Generation
93
PCI Configuration Space (1 E000 0000 to 1 FFFF FFFF)
94
PCI Configuration Space Definition
94
PCI Address Decoding for Primary Bus Configuration Accesses
95
PCI Configuration Cycles to Primary Bus Targets
96
PCI Configuration Cycles to Secondary Bus Targets
96
PCI Sparse Memory Space
97
Ffff Ffff
97
PCI Memory Space Address Translation
98
PCI Sparse Memory Space Byte Enable Generation
99
PCI Dense Memory Space (3 0000 0000 to 3 FFFF FFFF)
100
PCI-To-Physical Memory Addressing
101
PCI Target Window Enables
102
PCI Target Window Compare Scheme
103
PCI Target Address Translation-Direct Mapped
104
SG Map Page Table Entry in Memory
105
Scatter-Gather Map Address
106
SG Map Translation of PCI to Sysbus Address
107
Board Requirements and Parameters
109
Power Requirements
109
Power Supply DC Current Requirements for Motherboard (275 Mhz) Without I/O
109
Environmental Characteristics
110
Physical Board Parameters
110
Board Component Layout
111
Board Component Descriptions
112
A System Register Descriptions
115
Decchip 21071-CA CSR Descriptions
115
General Control Register
115
General Control Register
116
Error and Diagnostic Status Register
118
Tag Enable Register
121
Cache Size Tag Enable Values
122
Maximum Memory Tag Enable Values
122
Error Low Address Register
123
Error High Address Register
123
Ldx_L Low Address Register
124
Ldx_L High Address Register
124
Memory Control Registers
125
Video Frame Pointer Register
125
Presence Detect Low-Data Register
126
Presence Detect High-Data Register
127
Base Address Registers
127
Bank Set 0 Base Address Register
127
Configuration Registers
128
Bank Set 0 to 7 Configuration Register
129
Bank Set 8 Configuration Register
130
Bank Set 8 Configuration Register
131
Bank Set Timing Registers a and B
132
Bank Set Timing Register a
133
Bank Set Timing Register B
134
Bank Set Timing Register B
135
Global Timing Register
137
Refresh Timing Register
138
Decchip 21071-DA CSR Descriptions
139
Diagnostic Control and Status Register
140
Sysbus Error Address Register
141
Diagnostic Control and Status Register
141
PCI Error Address Register
142
Diagnostic Control and Status Register Field D_BYP<1:0
143
PCI Error Address Register
145
Translated Base Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . PCI Base Registers 1 and
146
PCI Mask Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . A.2.8 Host Address Extension Register 0
148
PCI Mask Registers 1 and 2
148
Host Address Extension Register
149
Host Address Extension Register
151
PCI Master Latency Timer Register
152
TLB Tag Registers 0 through
153
TLB Data Registers 0 through
154
SROM Initialization
155
Firmware Interface
156
Output Parameter Descriptions
156
Automatic CPU Speed Detection
158
CPU Bus Interface Timing
158
Cache Loop Delay Characteristics
158
SRAM Timing Specification Definitions
159
L2 Cache Read and Write Calculations
160
Worst-Case SRAM Timing Specifications
160
CPU Specifications
160
Write Cycle Timing
161
Memory Initialization
162
L2 Cache Initialization
163
Flash ROM (System ROM)
164
Special Flash ROM Headers
164
Special Header Content
164
Special Header Entry Descriptions
165
Flash ROM Structure
166
Higher 512KB Flash ROM Image Selection
167
Flash ROM Access
169
Icache Flush Code
170
Alpha PCI 64-275 Configuration Jumpers
170
C PCI Address Maps
171
PCI Interrupt Acknowledge/Special Cycle Address Space
171
PCI Sparse I/O Address Space
171
SIO PCI-To-ISA Bridge Operating Register Address Space
171
SIO PCI-To-ISA Bridge Operating Register Address Space Map
171
PCI Configuration Address Space
175
Address Bits and PCI Device Idsel Pins
175
SIO PCI-To-ISA Bridge Configuration Address Space
176
SIO PCI-To-ISA Bridge Configuration Address Space Map
176
PCI Sparse Memory Address Space
177
PCI Dense Memory Address Space
177
PC87312 Combination Controller Register Address Space
177
PC87312 Combination Controller Register Address Space Map
178
Utility Bus Device Address
180
Integrated Device Electronics (IDE) Register Addresses
180
Utility Bus Device Decode
181
Interrupt Control PLD Addresses
182
Keyboard and Mouse Controller Addresses
182
Time-Of-Year Clock Device Addresses
182
Flash ROM
183
Flash Memory Segment Select Register
184
Flash Memory Addresses
184
Flash ROM Configuration Registers
184
Flash Memory Addresses (Within Segment
184
Flash ROM Memory Map
185
Flash ROM Configuration Registers
185
Technical Support
187
Ordering Associated Literature
188
Ordering Third-Party Documentation
189

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