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Alpha PCI 64-275 Design Manual

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Alpha PCI 64-275
Design Guide
Order Number: EK–AL275-UG. A01
This manual describes the Alpha PCI 64-275 motherboard, order number
EBP30–AN, configured for the Microsoft Windows NT operating system.
Revision/Update Information:
This is a new manual.
Digital Equipment Corporation
Maynard, Massachusetts

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  • Page 1 Alpha PCI 64-275 Design Guide Order Number: EK–AL275-UG. A01 This manual describes the Alpha PCI 64-275 motherboard, order number EBP30–AN, configured for the Microsoft Windows NT operating system. Revision/Update Information: This is a new manual. Digital Equipment Corporation Maynard, Massachusetts...
  • Page 2 Digital Equipment Corporation. Digital Semiconductor is a Digital Equipment Corporation business. Digital UNIX Version 3.2 for Alpha is a UNIX 93 branded product. ABT is a registered trademark of Applied Business Technologies, Inc. AMD and MACH are registered trademarks of Advanced Micro Devices, Inc.

  • Page 3: Table Of Contents

    Hardware Configuration Jumpers ..... 2.1.2 2–5 Alpha PCI 64-275 Board Connectors ..... . 2–6 3 Functional Description Chipset Introduction .
  • Page 4 3.2.1 sysBus Interface ........3–8 3.2.1.1 sysBus Arbitration .
  • Page 5 3.4.7 DMA Write Buffer ....... . . 3–22 3.4.8 Memory Write Buffer ....... 3–22 Error Checking .
  • Page 6 4.1.7 PCI Configuration Space (1 E000 0000 to 1 FFFF FFFF) . . . 4–12 4.1.7.1 PCI Configuration Cycles to Primary Bus Targets ..4–14 PCI Configuration Cycles to Secondary Bus Targets ..4.1.7.2 4–14 PCI Sparse Memory Space (2 0000 0000 to...
  • Page 7 Icache Flush Code ....... . . B–16 Alpha PCI 64-275 Configuration Jumpers ....B.1.9 B–16...
  • Page 8 Dimensions ........1–7 2–1 Alpha PCI 64-275 Board Jumpers ..... 2–2 2–2 J3 Connector .
  • Page 9 4–6 SG Map Translation of PCI to SysBus Address ... 4–25 Board Component Layout ......5–1 5–3 A–1...
  • Page 10 2–3 2–2 Alpha PCI 64-275 Board Jumpers ....2–5 Module Connector Descriptions (See Figure 2–3) ..
  • Page 11 A–9 Bank Set Timing Register B ......A–22 Global Timing Register ......A–10 A–23 A–11...
  • Page 12 C–13 Memory Map of Flash Memory ..... . . C–16...

  • Page 13: Document Content

    Digital’s Alpha family of microprocessors. Scope This guide describes the features, configuration, functional operation, and interfaces of the Alpha PCI 64-275. Appendix D provides a list of related documentation for technical information. Document Content This guide contains the following chapters and appendixes: •...

  • Page 14: Technical Support

    It also includes information about the firmware interface, timing considerations, SROM header, and configuration jumpers. • Appendix C, PCI Address Maps, provides the Alpha PCI 64-275 operating register address space maps. • Appendix D, Technical Support and Documentation Ordering Information, describes how to order associated literature.
  • Page 15 Ranges and Extents Ranges are specified by a pair of numbers separated by two periods (..) and are inclusive. For example, a range of integers 0..4 includes the integers 0, 1, 2, 3, and 4. Extents are specified by a pair of numbers in angle brackets (<>) separated by a colon ( : ) and are inclusive.

  • Page 16: Register Field Type Notation

    Register Field Notation Register figures and tabulated descriptions have a mnemonic that indicates the bit or field as described in Table 1. Table 1 Register Field Type Notation Notation Description A read/write bit or field. The value may be read and written by software, microcode, or hardware.

  • Page 17: Unnamed Register Field Notation

    Other register fields that are unnamed may be labeled as specified in Table 2. Table 2 Unnamed Register Field Notation Notation Description A 0 in a bit position indicates a register bit that is read as a 0 and is ignored on a write transaction.

  • Page 18: Signal References

    Signal Names Signal names in text are printed in boldface lowercase type. As Table 4 shows, mixed-case and uppercase signal naming conventions are ignored. Table 4 Signal References This Guide Other Documentation cwmask7 cWMask7, CWMASK7 In addition, where a group of signals are referenced, the signal names are combined.

  • Page 19: Alpha Pci 64-275 Introduction

    Alpha PCI 64-275 Introduction The Alpha PCI 64-275 module is for constructing computing systems based on the Alpha 21064A microprocessor. The Alpha PCI 64-275 provides a single-board hardware and software development platform for the design, integration, and analysis of supporting logic and subsystems.

  • Page 20: Memory Subsystem

    It provides flexible and generic functions to allow its use in a wide range of systems. 1.1.3 PAL Control Set The Alpha PCI 64-275 contains a 4-PAL control set and includes the following: • Two 16V8-5 PALs provide L2 cache output-enable and write-enable functions.

  • Page 21: Alpha Pci 64-275 Functional Block Diagram

    Figure 1–1 Alpha PCI 64-275 Functional Block Diagram 21064A Support L2 Cache Interface - L2 Cache PALs - TriQuint PLL L2 Cache SIMMs Clock L2 Cache buff_ - Address Buffers - External Clock Control address Oscillator Alpha 21064A - Serial Boot ROM...

  • Page 22: Level 2 Cache Subsystem Overview

    4MB, or 8MB cache sizes using a 128-bit data bus. The L2 cache size can be reconfigured through onboard hardware and software jumpers. The Alpha PCI 64-275 supports the L2 cache SIMM sizes shown in Table 1–1. Two SIMMs are required per system. The Alpha PCI 64-275 comes with a 2MB, 12-ns L2 cache.

  • Page 23: Software Support

    Perform full source-level debugging by using DECladebug software running on a host communicating through an Ethernet connection. Development code can be generated on a host system and loaded into the Alpha PCI 64-275 through the serial line, optional Ethernet port, diskette, or flash ROM.

  • Page 24: Board Uses

    1.2 Board Uses The Alpha PCI 64-275 has a remote debug capability and a software debug monitor for loading code into the system and for performing other software debug functions such as memory read, memory write, and instruction breakpoint. When combined with a hardware interface, the debug monitor can be used to write and debug software (for example, device drivers) for workstation and PC products.

  • Page 25: Alpha Pci 64-275 Component Layout And Board Dimensions

    Figure 1–2 Alpha PCI 64-275 Component Layout and Board Dimensions 22.1 cm (8.7 in ± 0.05 in) Scale = 90% LJ-04458.sgw Alpha PCI 64-275 Introduction 1–7...

  • Page 27: System Jumpers And Connectors

    flash ROM enable, Level 2 Bcache speed, and sizes and boot options. The Alpha PCI 64-275 is shipped with 2Mb of L2 cache, but the system designer can reconfigure the module to support a variety of cache sizes and speeds to assist in the debugging of new option designs.

  • Page 28: Alpha Pci 64-275 Board Jumpers

    Figure 2–1 Alpha PCI 64-275 Board Jumpers Scale = 90% LJ-04459.AI5 2–2 System Jumpers and Connectors...

  • Page 29: J3 Connector

    Figure 2–2 J3 Connector sysclkdiv jmp_irq2 jmp_irq1 jmp_irq0 (not used) sp_bit0 sp_bit1 sp_bit2 sp_bit3 sp_bit4 sp_bit5 sp_bit6 sp_bit7 reset_button hd_act_l hd_led_l spkr key_lock To Speaker (not used) power_led_l LJ-04132.SW Table 2–1 Jumper Position Descriptions Register Bit Select Bit Name Function sp_bit7 BOOT_OPTION Jumper out—Boot first image in flash ROM.
  • Page 30 Table 2–1 (Cont.) Jumper Position Descriptions Register Bit Select Bit Name Function sp_bit6 MINI_DEBUG Jumper out (default)—Boot selected image in flash ROM. Jumper in—Trap to SROM debug port (J2). sp_bit<5:3> BC_SPEED<2:0> L2 cache speed selection is shown here. BC_SPEED <2> <1>...

  • Page 31: Hardware Configuration Jumpers

    2.1.2 Hardware Configuration Jumpers Hardware configuration jumpers are shown in Figure 2–1 and are described in Table 2–2. Table 2–2 Alpha PCI 64-275 Board Jumpers Connector Pins Description L2 Cache Address Lines Adr<22:19> L2 cache; pins 22:19 are identified on the board.

  • Page 32: Alpha Pci 64-275 Board Connectors

    J3-5 J3-7 sysclkdiv jmp_irq2 jmp_irq1 jmp_irq0 Divisor Divisor 9 is used for 275 MHz (default). 2.2 Alpha PCI 64-275 Board Connectors The module connectors are shown in Figure 2–3 and are described in Table 2–3. 2–6 System Jumpers and Connectors...

  • Page 33: Alpha Pci 64-275 Board Connectors

    Figure 2–3 Alpha PCI 64-275 Board Connectors J10 J11 Scale = 90% LJ-04457.AI5 System Jumpers and Connectors 2–7...

  • Page 34: Module Connector Descriptions (See Figure 2-3)

    Table 2–3 Module Connector Descriptions (See Figure 2–3) Connector Pins Description PCI Slots PCI expansion slot 3 PCI expansion slot 2 PCI expansion slot 1 PCI expansion slot 0 (shared slot) ISA Slots ISA expansion slot 2 (shared slot) ISA expansion slot 1 ISA expansion slot 0 L2 Cache SIMM Slots L2 cache SIMM slot 1, data<127:64>...
  • Page 35 Table 2–3 (Cont.) Module Connector Descriptions (See Figure 2–3) Connector Pins Description Memory SIMMs Bank 0, DRAM 0 SIMM Bank 0, DRAM 1 SIMM Bank 0, DRAM 2 SIMM Bank 0, DRAM 3 SIMM Bank 1, DRAM 0 SIMM Bank 1, DRAM 1 SIMM Bank 1, DRAM 2 SIMM Bank 1, DRAM 3 SIMM SROM Test...
  • Page 36 Table 2–3 (Cont.) Module Connector Descriptions (See Figure 2–3) Connector Pins Description Power Connectors Module power connector (GND, +3.3 V) Voltage/Signal Ground Ground Ground +3.3 V +3.3 V +3.3 V Module power connector (+3.3 V, GND) Voltage/Signal +3.3 V +3.3 V +3.3 V Ground Ground...
  • Page 37 –12 V Ground Ground Note: Power for the Alpha PCI 64-275 is provided by a user-supplied, standard PC power supply that includes 3.3 Vdc. Digital does not provide this power supply. CPU fan power and sensor. Pin 1 is +12 V. Pin 2 is sensor;...
  • Page 38 Table 2–3 (Cont.) Module Connector Descriptions (See Figure 2–3) Connector Pins Description Enclosure Fan Enclosure fan connector. Pins 1 and 3 are ground. Pin 2 is +12 V. Power LED J3 Pins 38, 40 Power LED connector. Pin 38 is +5 V with a built-in 150-ohm resistor.

  • Page 39: List Of Connector And Jumper Part Numbers

    Table 2–4 List of Connector and Jumper Part Numbers Vendor Part Number Designation Description or Equivalent Note: Specific vendor part numbers are for reference only and should not be construed as a recommendation by Digital. Fan power (connector) Molex 22–27–2031 Serial port (connector) DUPONT 65611–110 (Jumpers)

  • Page 41: Functional Description

    Functional Description This chapter describes the functional operation of the Alpha PCI 64-275. The description introduces the ASIC support chipset and describes its implementation with the 21064A microprocessor and its supporting memory and I/O devices. Information, such as bus timing and protocol, found in other specifications, data sheets, and reference documentation is not duplicated.

  • Page 42: 21071-Ca Introduction

    L2 cache RAMs during a CPU cache miss and direct memory access (DMA) transactions. On the Alpha PCI 64-275, the 21071-CA controls two banks of DRAM SIMMs. The SIMMs can range in size from 1M x 36 to 16M x 36. Each bank can accommodate four 36-bit SIMMs to support a 128-bit data path with longword parity.

  • Page 43: Maximum And Minimum Simm Bank Layouts

    Figure 3–1 Maximum and Minimum SIMM Bank Layouts Maximum 512MB DRAM Layout - Populated with 16M x 36 SIMMs DRAM 2 - 64MB SIMM DRAM 0 - 64MB SIMM memData64 - 95 + Parity memData0 - 31 + Parity Bank 0 256MB DRAM 3 - 64MB SIMM DRAM 1 - 64MB SIMM...

  • Page 44: 21071-Da Introduction

    Figure 3–2 Basic Cache and Memory Subsystem Address and Data Paths Tag Adr Ctrl L2 Cache Ctrl 21071-CA Memory Address and Control SysAdr Cache Memory DRAMs sysData <127:0> Check <21, 14, 7, 0> 32 Bits 32 Bits 32 Bits 32 Bits 21071-BA 0 21071-BA 1 21071-BA 2...

  • Page 45: Basic I/O Subsystem Address And Data Paths

    The 21071-DA provides all controls and interfaces to the PCI and sysBus and contains the following components and functions: • sysBus interface state machine • sysBus address decoder and translator • epiBus arbitration and control • PCI interface, state machines, and parity generation •...
  • Page 46 The following list summarizes the major features of the 21071-DA: • Scatter-gather mapping from the 32-bit PCI address to the 34-bit physical address, with an onchip, 8-entry translation lookaside buffer (TLB) for fast address translations. To reduce cost, the scatter-gather tables are stored in memory and are automatically read by the 21071-DA when a translation misses in the TLB.

  • Page 47: 21071-Ba Introduction

    3.1.3 21071-BA Introduction The 21071-BA chip provides a 32-bit data path from the 21064A to main memory and I/O. Four chips are required for the 128-bit interface. The chip contains the cache and memory interface data path, which includes buffers for victim, noncacheable write, and DMA write operations. It also contains the I/O subsystem data path, which provides buffering for DMA read and write data, and I/O read and write data.

  • Page 48: 21071-Ca Functional Overview

    3.2 21071-CA Functional Overview The 21071-CA provides second-level cache and memory control functions. It also controls the cache and memory data path located on the 21071-BA. Figure 3–4 shows a block diagram of the 21071-CA. Figure 3–4 21071-CA Block Diagram Write tagadr<31:17>...

  • Page 49: Sysbus Arbitration

    3.2.1.1 sysBus Arbitration The 21071-CA arbitrates between the CPU and 21071-DA, which requests use of the sysBus and the L2 cache when they have a transaction to perform. The CPU has default ownership of the sysBus so that it can access the L2 cache whenever the 21071-DA is not requesting the bus.

  • Page 50: Sysbus Control

    On DMA-initiated transactions, the L2 cache controller provides control for probing the cache and extracting or invalidating the cache line when required. The 21071-CA supports a write-back cache. 3.2.1.3 sysBus Control The sysBus controller consists of a sequencer that receives CPU and DMA command fields for decode, results from the sysBus arbiter logic, and status from the memory controller logic.

  • Page 51: Memory Controller

    DRAMs, implemented with SIMMs. The SIMM implementation requires more than one SIMM to form one memory bank. For example, four 33-bit SIMMs are required to form the 128-bit bank width. On the Alpha PCI 64-275, the 21071-CA supports 16MB to 512MB of DRAM.

  • Page 52: Transaction Scheduler

    3.2.2.5 Transaction Scheduler The memory interface does memory refresh, cache-line read and write transactions, and shift register loads to VRAM bank set 8. The memory controller has a scheduler that prioritizes transactions and selects one to be serviced. If the selected transaction is waiting for row address strobe (RAS) precharge, and another higher priority transaction is initiated, the scheduler deselects the previously chosen transaction and selects the higher priority transaction.

  • Page 53: 21071-Da Functional Overview

    3.3 21071-DA Functional Overview The 21071-DA is a bridge between the PCI local bus and the 21064A microprocessor and its L2 cache and memory. The 21071-DA contains all control functions of the bridge and some data path functions. Other data path functions reside in the 21071-BA.

  • Page 54: Sysbus Interface

    3.3.1 sysBus Interface The sysBus interface includes the sysBus control state machine, the address decode for CPU-initiated transactions, buffering for CPU-initiated transactions, and the 21071-DA control and status registers. 3.3.1.1 Address Decode The 21071-DA provides logic for translating and extending between the 21064A 34-bit physical address space and the 32-bit PCI address space.

  • Page 55: Dma Write Buffer

    3.3.2.2 DMA Write Buffer The PCI interface has a write buffer for buffering DMA write data. The DMA write buffer is made up of four entries. Each entry contains the cache-line address, eight longwords of data, the byte enables corresponding to each longword, and a valid bit for the entry.

  • Page 56: Pci Burst Order

    3.3.2.5 PCI Burst Order PCI address bits ad<1:0> specify the burst ordering requested by the master during memory transactions. When the 21071-DA is a master of the PCI, it will always indicate a linear incrementing burst order (ad<1:0> = 0) on read and write transactions.

  • Page 57: Pci Retry Timeout

    The 21071-DA also supports PCI bus parking during reset. If the iogrant signal is asserted by the PCI arbiter (req_l is always tristated by the 21071-DA during reset), the 21071-DA will drive ad<31:0>, cbe<3:0>, and (one clock cycle later) par. When iogrant is deasserted, the 21071-DA tristates these signals.

  • Page 58: Deadlock Resolution

    • I/O transfers from the CPU to the PCI or to 21071-DA CSRs are performed in order. This policy guarantees a coherent view of PCI I/O space from the CPU. • The 21071-DA flushes DMA write data to memory before acknowledging a barrier command from the CPU.

  • Page 59: Guaranteed Access-Time Mode

    ISA bus. The flushreq_l and memreq_l signals are outputs from the bridge; memack_l is an input to the bridge. Note The Alpha PCI 64-275 does not support guaranteed access-time mode. 3.3.2.15 Interrupts The 21071-DA interrupts the CPU by using the int_hw0 signal when it has errors to report.

  • Page 60: 21071-Ba Functional Overview

    3.4 21071-BA Functional Overview This section describes the data bus configurations and provides a functional overview of the 21071-BA. Figure 3–7 shows a block diagram of the 21071-BA. Figure 3–7 DECchip 21071-BA Block Diagram Memory Read Buffer sysData <127:0> Memory Merge Write memData...

  • Page 61: Memdata Bus

    3.4.2 memData Bus With a memData bus of 128 bits, four 21071-BA chips are required, that is: • 21071-BA0 connects to longword 0 (memdata<31:0>) • 21071-BA1 connects to longword 1 (memdata<63:32>) • 21071-BA2 connects to longword 2 (memdata<95:64>) • 21071-BA3 connects to longword 3 (memdata<127:64>) 3.4.3 epiData Bus Each 21071-BA has 32 epiData bus pins.

  • Page 62: Dma Write Buffer

    3.4.7 DMA Write Buffer The DMA write buffer has four entries. Each entry contains four longwords for each 21071-BA and corresponding byte masks. However, only half the storage for each entry is used. The extra storage is not accessible. The DMA write buffer is loaded by the 21071-DA and is unloaded by the 21071-CA during a DMA write transaction on the sysBus.

  • Page 63: Error Handling

    3.5 Error Handling The first error causes CSR error bits and the associated error address register to be set and locked. If another error occurs, only the lost error bit is set and int_hw0 is asserted to interrupt the processor. The int_hw0 signal is held asserted as long as the corresponding error bit is set.

  • Page 64: Clock Subsystem

    3.6 Clock Subsystem The system clocks can be divided into three areas: the input clocks required by the CPU, CPU clock distribution to the system logic, and miscellaneous oscillators and clocks required for the peripheral interfaces and functions. The 21064A CPU clock input is provided by a TriQuint phase-locked loop (PLL) clock oscillator.

  • Page 65: System Clock Distribution

    2 to 17 as specified in the description of the J3 connector jumpers in Table 2–2. Note For other clocks generated by the CPU and not used on the board, refer to the Alpha 21064 and Alpha 21064A Microprocessors Hardware Reference Manual. 3.6.2 System Clock Distribution Figure 3–9 shows the primary clock distribution network for both phase-locked...

  • Page 66: Primary Clock Distribution Network

    Figure 3–9 Primary Clock Distribution Network sysclk_pll90 AMCC 21064A sysclkout1 sysclk_pll0 S4402 sysclk_pll0_2x 74FCT 805CT pciclk_sio sysclk_pll90 Buffer 1 33-MHz Clocks pciclk_slot<3:0> (Shifted 90°) clk1x2_dec<1:4> sysclk_pll0_2x 66-MHz Clocks Buffer 2 clk1x2_com_epic 74FCT 805CT clk2xref_pal clk2xref_dec1_dec2 clk2xref_dec3_dec4 33-MHz Clocks Buffer 1 (Shifted 90°) clk2xref_com_epic pciclk_epic...

  • Page 67: Distribution Of 66-Mhz Clock Signals

    U40 generates six 66-MHz clock signals, which are distributed as shown in Table 3–2. Table 3–2 Distribution of 66-MHz Clock Signals Clock Signal Name Destination clk1x2_dec1 21071-BA0 clk1x2_dec2 21071-BA1 clk1x2_dec3 21071-BA2 clk1x2_dec4 21071-BA3 clk1x2_com_epic 21071-DA U39 generates thirteen 33-MHz clock signals. These 33-MHz clock signals are shifted 90 degrees.

  • Page 68: Buffered Clock Distribution Network

    U25 (L2 cache PAL) clk1_fb U39 (provide feedback to S4402 PLL) There are two additional oscillators that provide 14.3-MHz and 24-MHz clocks for the Alpha PCI 64-275, as shown in Figure 3–10. Figure 3–10 Buffered Clock Distribution Network kclk 8242...

  • Page 69: Pci Interrupts And Arbitration

    The PLDs also allow the current state of the interrupt lines to be read. The Alpha PCI 64-275 has 17 PCI interrupts: four from each of the four PCI slots (16) and one from the SIO bridge.

  • Page 70: Interrupt Control And Pci Arbitration

    Figure 3–11 Interrupt Control and PCI Arbitration sys_irq0 21071-DA System pci_isa_irq<0> Interrupt PLDs pci_inta<3:0> rtc_irq_l<1> pci_intb<3:0> pci_intc<3:0> nmi <2> pci_intd<3:0> PCI Bus sio_int cpu_irq 5, pci_req_s0_l <2:0> pci_gnt_s0_l Slot 0 pci_req_s1_l pci_gnt_s1_l Slot 1 irq_resetd_l PCI-to-ISA pci_req_s2_l Bridge jmp_irq<2:0> pci_gnt_s2_l Slot 2 Clock Multiplier...
  • Page 71 IRQ14 IRQ15 16-bit ISA The Alpha PCI 64-275 timer interrupt is generated by the real-time clock by means of cpu_irq1, rather than by the timer within the SIO, which would route the interrupt through the ISA bus interrupts. Interrupt PLDs Function The MACH210 PLD acts as 8-bit I/O slave on the ISA bus at addresses 804, 805, and 806.

  • Page 72: Pci/Isa Arbitration

    Each interrupt can be individually masked by setting the appropriate bit in the mask register. An interrupt is disabled by writing a 1 to the desired position in the mask register. An interrupt is enabled by writing a 0. For example, bit <7>...

  • Page 73: Pci Devices

    3.8 PCI Devices The Alpha PCI 64-275 uses the PCI bus as the main I/O bus for the majority of peripheral functions. The board implements the ISA bus as an expansion bus for system support functions and peripheral devices. 3.8.1 Intel Saturn IO Chip The SIO chip provides the bridge between the PCI bus and the Industry Standard Architecture (ISA) bus.

  • Page 74: Isa Devices

    3.9 ISA Devices Figure 3–13 shows the Alpha PCI 64-275 ISA bus implementation with peripheral devices and connectors. Also shown is the utility bus with system support devices. Figure 3–13 ISA Devices PCI Bus la<23:17> sd<15:0> sd<7:0> ubus<7:0> Transceiver PCI-to-ISA...

  • Page 75: Combination Controller

    Microcontroller • Peripheral Components 3.9.2 Combination Controller The Alpha PCI 64-275 uses the National PC87312 as the combination controller chip (see Figure 3–13). It is packaged in a 100-pin PQFP configuration. The chip provides the following ISA peripheral functions: •...

  • Page 76: Time-Of-Year Clock

    PLD. 3.9.4 Utility Bus Memory Devices The Alpha PCI 64-275 utility bus drives the Intel 28F008SA flash ROM. This 1MB flash ROM provides nonvolatile memory for operating system and firmware support. The flash ROM is split into two 512KB segments. Selection between the two segments is determined by the value of flash_adr19.

  • Page 77: Isa Expansion Slots

    Refer to the Intel Flash Memory document for additional information about pin assignments and signal descriptions, register descriptions, and a functional description (including timing, electrical characteristics, and mechanical data). 3.9.5 ISA Expansion Slots Three ISA expansion slots are provided for plug-in ISA peripherals. One of the slots is shared with the PCI and can be used for a PCI or ISA device.

  • Page 78: Dc Power Distribution

    3.11 dc Power Distribution The Alpha PCI 64-275 derives its system power from a user-supplied, industry- standard PC power supply. The power supply must provide +12 V dc, –12 V dc, –5 V dc, +5 V dc, and 3.3 V dc. The dc power is supplied through power connectors J27, J28, J29, and J31 (see Figure 3–15).

  • Page 79: Dc Power Distribution

    Figure 3–15 dc Power Distribution Power Connectors: p_dcok +12 V dc -12 V dc Devices Slots Slots Clocks -5 V dc 3 V dc Logic 3 V dc 21064 Ground Ground 3 V dc LJ04143A.SGW Functional Description 3–39...

  • Page 80: System Software

    3.13 System Software The Alpha PCI 64-275 software is divided into the following categories: • Serial ROM code • Flash ROM code • Operating systems 3.13.1 Serial ROM Code The serial ROM code is contained in the Xilinx XC1765D serial configuration ROM.

  • Page 81: System Reset And Initialization

    Figure 3–16 System Reset and Initialization dc Power p_dcok b_dcok Gate Fan Sensor fan_ok_l Reset Switch pre_reset button_1 Gate p_dcok sys_reset1_l Reset Functions: sys_reset2_l - PCI-to-ISA Bridge sys_reset3_l pre_reset - PCI Interrupt rst_l sys_reset4_l +3 V dc Power 74ACT244 Controller sense_dis Sense Gate...

  • Page 82: Flash Rom Code

    File load • Read and write memory and registers • Memory image dump • Transfer control to program • Breakpoints 3.13.3 Operating Systems The Alpha PCI 64-275 is designed to run the Microsoft Windows NT operating system. 3–42 Functional Description...

  • Page 83: System Address Mapping

    System Address Mapping This chapter describes the mapping of the 34-bit processor physical address space into memory and I/O space addresses. It also includes the translations of the processor-initiated address into a PCI address, and PCI-initiated addresses into physical memory addresses. 4.1 CPU Address Mapping to PCI Space The 34-bit physical sysBus address space is composed of the following: •...

  • Page 84: Sysbus Address Map

    Figure 4–1 sysBus Address Map 0 0000 0000 Cacheable Memory Space 0 FFFF FFFF 1 0000 0000 Noncacheable Memory Space 1 7FFF FFFF 1 8000 0000 21071-CA CSR Space 1 9FFF FFFF 1 A000 0000 21071-DA CSR Space 1 AFFF FFFF 1 B000 0000 PCI Interrupt Acknowledge Special Cycle Space...

  • Page 85: Sysbus Address Space Description

    Table 4–1 sysBus Address Space Description sysAdr sysAdr <33:32> <31:28> Address Space Description xxxx Cacheable memory Accessed by the CPU instruction space stream (Istream) or data stream (Dstream). Accessed by DMA. The 21071-DA does not respond to addresses in this space. 0xxx Noncacheable Accessed by the CPU (Istream or...

  • Page 86: Cacheable Memory Space (0 0000 0000 To 0 Ffff Ffff)

    Table 4–1 (Cont.) sysBus Address Space Description sysAdr sysAdr <33:32> <31:28> Address Space Description xxxx PCI sparse memory 128MB addressable PCI space. space The lower address bits are used to determine byte masks and transaction length information. The 4GB space is reduced to a 128MB sparse space.

  • Page 87: Decchip 21071-Ca Csr Space (1 8000 0000 To 1 9Fff Ffff)

    4.1.3 DECchip 21071-CA CSR Space (1 8000 0000 to 1 9FFF FFFF) The DECchip 21071-CA responds to all CSR accesses in this space. Table 4–2 specifies the registers and associated register addresses. Appendix A contains the register descriptions. Table 4–2 DECchip 21071-CA CSR Register Addresses Address Register Name 1 8000 0000...
  • Page 88 Table 4–2 (Cont.) DECchip 21071-CA CSR Register Addresses Address Register Name 1 8000 0A00 Bank 0 configuration register 1 8000 0A20 Bank 1 configuration register 1 8000 0A40 Bank 2 configuration register 1 8000 0A60 Bank 3 configuration register 1 8000 0A80 Bank 4 configuration register 1 8000 0AA0 Bank 5 configuration register...

  • Page 89: Decchip 21071-Da Csr Space (1 A000 0000 To 1 Afff Ffff)

    4.1.4 DECchip 21071-DA CSR Space (1 A000 0000 to 1 AFFF FFFF) The DECchip 21071-DA responds to all accesses in this space. Table 4–3 specifies the registers and associated register addresses. Appendix A contains the register descriptions. Table 4–3 DECchip 21071-DA CSR Register Addresses Address Register Name 1 A000 0000...

  • Page 90: Pci Interrupt Acknowledge/Special Cycle Space (1 B000 0000 To 1 Bfff Ffff)

    Table 4–3 (Cont.) DECchip 21071-DA CSR Register Addresses Address Register Name 1 A000 0300 TLB 0 data register 1 A000 0320 TLB 1 data register 1 A000 0340 TLB 2 data register 1 A000 0360 TLB 3 data register 1 A000 0380 TLB 4 data register 1 A000 03A0 TLB 5 data register...

  • Page 91: Pci Sparse I/O Space (1 C000 0000 To 1 Dfff Ffff)

    4.1.6 PCI Sparse I/O Space (1 C000 0000 to 1 DFFF FFFF) The PCI sparse I/O space is similar to the PCI sparse memory space. This 512MB sysBus address space maps to 16MB of PCI I/O address space. A read or write transaction to this space causes a PCI I/O read or PCI I/O write command respectively.

  • Page 92: Pci Sparse I/O Space Address Translation

    Figure 4–2 PCI Sparse I/O Space Address Translation 29 28 23 22 08 07 05 04 03 02 sysBus Address 1 1 0 0 0 0 0 0 0 Length in Bytes HAXR0 Byte Offset 24 23 03 02 PCI I/O Address Address Translation for Lower 256K Bytes of PCI I/O Space 29 28 23 22...

  • Page 93: Pci Sparse I/O Space Byte Enable Generation

    Table 4–4 PCI Sparse I/O Space Byte Enable Generation PCI Byte Address Address Length <6:5> <4:3> Enable PCI ad<2:0> Byte 1110 CPU address<7>, 00 1101 CPU address<7>, 01 1011 CPU address<7>, 10 0111 CPU address<7>, 11 Word 1100 CPU address<7>, 00 1001 CPU address<7>, 01 0011...

  • Page 94: Pci Configuration Space (1 E000 0000 To 1 Ffff Ffff)

    4.1.7 PCI Configuration Space (1 E000 0000 to 1 FFFF FFFF) A read or write access to this space causes a configuration read or write cycle on the PCI. There are two classes of targets: devices on the primary PCI bus and devices on the secondary PCI buses that are accessed through PCI-to-PCI bridge chips.

  • Page 95: Pci Address Decoding For Primary Bus Configuration Accesses

    Table 4–6 translates sysAdr<20:16> to PCI primary bus addresses. Table 4–6 PCI Address Decoding for Primary Bus Configuration Accesses Device Number (sysAdr<20:16>) PCI ad<31:11> 00000 0000 0000 0000 0000 0000 1 00001 0000 0000 0000 0000 0001 0 00010 0000 0000 0000 0000 0010 0 00011 0000 0000 0000 0000 0100 0 00100...

  • Page 96: Pci Configuration Cycles To Primary Bus Targets

    4.1.7.1 PCI Configuration Cycles to Primary Bus Targets Primary PCI bus devices are selected during a PCI configuration cycle if their IDSEL# pin is asserted, if the PCI bus command indicates a configuration read or write transaction, and if ad<1:0> are 00. Bits ad<7:2>, which are taken from sysAdr<12:7>, select a longword register in the device’s 256-byte configuration address space.

  • Page 97: Pci Sparse Memory Space

    4.1.8 PCI Sparse Memory Space (2 0000 0000 to 2 FFFF FFFF) Access to PCI sparse memory space can have byte, word, tribyte, longword, or quadword granularity. The Alpha architecture does not provide byte, word, or tribyte granularity, which the PCI requires. To provide this granularity, the byte enable and byte length information is encoded in the lower address bits of this space (ad<7:3>).

  • Page 98: Pci Memory Space Address Translation

    Figure 4–3 shows the sysBus to PCI memory address translation. Table 4–7 shows the generation of the byte enables and PCI address ad<2:0> from sysBus<6:3>. Figure 4–3 PCI Memory Space Address Translation 32 31 29 28 08 07 04 03 02 0 0 0 Length in Bytes HAXR0...

  • Page 99: Pci Sparse Memory Space Byte Enable Generation

    Table 4–7 PCI Sparse Memory Space Byte Enable Generation PCI Byte Length Address<6:5> Address<4:3> Enable PCI ad<2:0> Byte 1110 CPU address<7>, 00 1101 CPU address<7>, 00 1011 CPU address<7>, 00 0111 CPU address<7>, 00 Word 1100 CPU address<7>, 00 1001 CPU address<7>, 00 0011 CPU address<7>, 00...

  • Page 100: Pci Dense Memory Space (3 0000 0000 To 3 Ffff Ffff)

    Accesses in this space are no more than a quadword. Software must ensure that the processor does not merge consecutive write transactions in its write buffers by using memory barriers after each write transaction. Architecturally, if a byte, word, tribyte, or longword is written on the PCI, an STL instruction must be executed to the lower longword in the corresponding quadword address.

  • Page 101: Pci-To-Physical Memory Addressing

    The address generation in dense space is as follows: • Bits sysBus<31:5> are sent out on ad<31:5>. • On read transactions, ad<4:3> is generated from cpucwmask<1:0>; ad<2> is always 0. • On write transactions, ad<4:2> is generated from cpucwmask<7:0>. If the lower longword is to be written, ad<2>...

  • Page 102: Pci Target Window Enables

    Table 4–8 PCI Target Window Enables PCI_MASK<31:20> Window Size Value of n 0000 0000 0000 0000 0000 0001 0000 0000 0011 0000 0000 0111 0000 0000 1111 16MB 0000 0001 1111 32MB 0000 0011 1111 64MB 0000 0111 1111 128MB 0000 1111 1111 256MB 0001 1111 1111...

  • Page 103: Pci Target Window Compare Scheme

    Note The window base addresses must be on naturally aligned address boundaries, depending on the size of the window. Figure 4–4 PCI Target Window Compare Scheme 20 19 13 12 PCI Address Peripheral Page Number Offset Compare PCI Base Register PCI Mask 0000000 (Determines ) n...

  • Page 104: Pci Target Address Translation-Direct Mapped

    If SGEN is cleared, the DMA address is direct mapped. The translated address is generated by concatenating bits from the matching window translated base register with bits from the incoming PCI address. The PCI mask register determines which bits of the translated base register and PCI address are used to generate the translated address as shown in Table 4–9.

  • Page 105: Sg Map Page Table Entry In Memory

    Each SG map entry maps an 8KB page of PCI address space into an 8KB page of processor address space. Each SG map entry is a quadword. Each entry has a valid bit in position 0. Address bit ad<13> is at bit position 1 of the map entry.

  • Page 106: Scatter-Gather Map Address

    Table 4–10 Scatter-Gather Map Address SG Map PCI_MASK<31:20> Table Size SG Map Address<32:3> 0000 0000 0000 T_BASE<32:10>:PCI ad<19:13> 0000 0000 0001 T_BASE<32:11>:PCI ad<20:13> 0000 0000 0011 T_BASE<32:12>:PCI ad<21:13> 0000 0000 0111 T_BASE<32:13>:PCI ad<22:13> 0000 0000 1111 16KB T_BASE<32:14>:PCI ad<23:13> 0000 0001 1111 32KB T_BASE<32:15>:PCI ad<24:13>...

  • Page 107: Sg Map Translation Of Pci To Sysbus Address

    Figure 4–6 SG Map Translation of PCI to SysBus Address 13 12 05 04 PCI Address Peripheral Page Number Offset Compare sysBus Base Address T_Base 0000 (Translated Base Register) Scatter-Gather Map Address Driven on sysBus Scatter-Gather Entry Scatter-Gather Map in Main Memory 13 12 Physical Memory...

  • Page 109: Board Requirements And Parameters

    5.1 Power Requirements The Alpha PCI 64-275 derives its dc power from a user-supplied, industry- standard PC power supply. The board has a total power dissipation of 96.2 W, excluding PCI and ISA devices. Table 5–1 lists the power requirements of each dc supply voltage.

  • Page 110: Environmental Characteristics

    If the fan stops, the loss of the sensor signal puts the Alpha PCI 64-275 into a low power standby mode. This protects the Alpha PCI 64-275 under fan-failure conditions. 5.2 Environmental Characteristics The Alpha PCI 64-275 board environmental characteristics are: •...

  • Page 111: Board Component Layout

    Figure 5–1 Board Component Layout Scale = 90% LJ-04460.AI5 Board Requirements and Parameters 5–3...

  • Page 112: Board Component Descriptions

    Table 5–2 Board Component Descriptions Number Device Component Description Alpha 21064A–275 microprocessor—431 PGA, 275 MHz DECchip 21071–BA0, 208-pin PQFP, ASIC DECchip 21071–BA1, 208-pin PQFP, ASIC DECchip 21071–BA2, 208-pin PQFP, ASIC DECchip 21071–BA3, 208-pin PQFP, ASIC DECchip 21071–DA, 208-pin PQFP, ASIC DECchip 21071–CA, 208-pin PQFP, ASIC...
  • Page 113 Table 5–2 (Cont.) Board Component Descriptions Number Device Component Description 32, 33 U22, U23 74F08 AND gate PALCE22V10H–25JC, 28-pin PLCC, 25 ns 74ACT244 S82378ZB—208-pin PQFP, PCI-to-ISA bridge chip 24-MHz crystal oscillator PC87312VF combination diskette controller chip— 100-pin PQFP 39, 41, 43 U48, U50, U52 SN75189 receiver 40, 42...

  • Page 115: A System Register Descriptions

    System Register Descriptions This appendix describes the control and status registers (CSRs) of the DECchip 21071-CA (Sections A.1 and A.1.8) and DECchip 21071-DA (Section A.2). A.1 DECchip 21071-CA CSR Descriptions The CSRs are 16 bits wide and are addressed on cache-line boundaries. Write transactions to read-only registers could result in UNPREDICTABLE behavior;...

  • Page 116: General Control Register

    Figure A–1 General Control Register 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BC_BADAP BC_FRCP BC_FRCV BC_FRCD BC_FRCTAG BC_IGNTAG BC_LONGWR BC_NOALLOC BC_EN WIDEMEM SYSARB LJ-04178.AI Table A–1 General Control Register Field Name Type Description <15:14>...
  • Page 117 Table A–1 (Cont.) General Control Register Field Name Type Description <9> BC_FRCTAG RW, 0 L2 cache force tag. When set, the LE cache will be probed for victims, and the line will be invalidated using the values in the BC_FRCD, BC_FRCV, and BC_FRCP fields.

  • Page 118: Error And Diagnostic Status Register

    A.1.2 Error and Diagnostic Status Register The error and diagnostic register is shown in Figure A–2 and is defined in Table A–2. The register contains read-only status information for diagnostics and error analysis. The occurrence of an error sets one or more error bits (BC_TAPERR, BC_TCPERR, NXMERR) and locks the address of the error.
  • Page 119 Table A–2 (Cont.) Error and Diagnostic Status Register Field Name Type Description <14> LDXLLOCK — LDx_L locked. When set, indicates that the lock bit for LDx_L is set and that the next STx_C may succeed. Writing to any CSR or I/O space location clears this lock bit.
  • Page 120 Table A–2 (Cont.) Error and Diagnostic Status Register Field Name Type Description <0> LOSTERR RW1C, 0 Lost error, multiple errors. When set, indicates that additional errors occurred after an error address was locked. No address or cause information is latched for the error. A–6 System Register Descriptions...

  • Page 121: Tag Enable Register

    A.1.3 Tag Enable Register The tag enable register, shown in Figure A–3, indicates which bits of the cache tag are to be compared with sysadr<33:5>. If a bit is 1, the corresponding bits in sysadr<33:5> and systag<31:17> are compared. If a bit is 0, there is no comparison for those bits, and the systag bit is assumed to be tied low on the module (through a resistor).

  • Page 122: Cache Size Tag Enable Values

    Table A–3 Cache Size Tag Enable Values Compared TAGEN<15:0> Bits Cache Size 0000 0000 0000 0000 None 1000 0000 0000 0000 <31> 1100 0000 0000 0000 <31:30> 1110 0000 0000 0000 <31:29> 512MB 1111 0000 0000 0000 <31:28> 256MB 1111 1000 0000 0000 <31:27>...

  • Page 123: Error Low Address Register

    Table A–4 (Cont.) Maximum Memory Tag Enable Values Compared TAGEN<15:0> Bits Memory Size 0000 0011 1111 1110 <25:17> 64MB 0000 0001 1111 1110 <24:17> 32MB 0000 0000 1111 1110 <23:17> 16MB 0000 0000 0111 1110 <22:17> 0000 0000 0011 1110 <21:17>...

  • Page 124: Ldx_L Low Address Register

    Figure A–5 Error High Address Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ERR_HADR<33:21> LJ-04182.AI A.1.6 LD x _L Low Address Register The LDx_L low address register is shown in Figure A–6. The register stores the low-order bits of the last locked address.

  • Page 125: Memory Control Registers

    A.1.8 Memory Control Registers This section describes and defines 21071-CA registers that control memory configuration and timing. Each bank set of memory has one configuration register and two timing registers. The global timing register and refresh timing register apply to all bank sets. The video frame pointer is used for video transactions to bank set 8.

  • Page 126: Presence Detect Low-Data Register

    Table A–5 (Cont.) Video Frame Pointer Register Field Name Type Description <13:5> VFP_ROWADR Video frame row address pointer. Row address of the start of the frame buffer. <4:0> VFP_COLADR Video frame column address pointer. Used as column address <6:2> for all serial register loads. A.1.8.2 Presence Detect Low-Data Register The presence detect low-data register is shown in Figure A–9.

  • Page 127: Presence Detect High-Data Register

    A.1.8.3 Presence Detect High-Data Register The presence detect high-data register is shown in Figure A–10. The register stores the high-order bits of the presence detect data that was shifted in after reset. Bits <15:0> in the register represent data bits <31:16> that were shifted Note After deassertion of reset, it takes 148 system clock cycles for this data to become valid.

  • Page 128: Configuration Registers

    The number of bits that are compared depends on the size of the corresponding bank set. Bank sets 7 to 0 have an 11-bit field, limiting the minimum DRAM bank set size to 8MB. Bits <15:5> in the register correspond to sysadr<33:23>. Bank set 8, which can contain video RAMs and has a minimum size of 1MB, has the same 11-bit field, where bits <15:5>...

  • Page 129: Bank Set 0 To 7 Configuration Register

    Bank Set 0 to 7 Configuration Registers Bank set 0 to 7 configuration registers have the same format and also have the same limits on bank set size and type of DRAMs used. With the exception of the valid bit, these registers are not initialized. Bank set 0 to 7 registers are shown in Figure A–12 and are defined in Table A–6.

  • Page 130: Bank Set 8 Configuration Register

    Table A–6 (Cont.) Bank Set 0 to 7 Configuration Register Field Name Type Description <5> S0_SUBENA RW, 0 Enable subbanks. When set, subbanks are enabled and are determined according to S0_SIZE. When clear, subbanks are disabled, and the <3:0>_rasb0_l pins will be asserted only during refreshes. <4:1>...

  • Page 131: Bank Set 8 Configuration Register

    Figure A–13 Bank Set 8 Configuration Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 S8_CHECK S8_COLSEL S8_SUBENA S8_SIZE S8_VALID LJ-04190.AI Table A–7 Bank Set 8 Configuration Register Field Name Type Description <15:10>...

  • Page 132: Bank Set Timing Registers A And B

    Table A–7 (Cont.) Bank Set 8 Configuration Register Field Name Type Description <5> S8_SUBENA RW, 0 Enable subbanks. When set, subbanks are enabled and determined according to S8_SIZE. When clear, subbanks are disabled, and the b<1:0>_rasb0_l pins will be asserted only during refresh. <4:1>...

  • Page 133: Bank Set Timing Register A

    On reset, all the parameters are set to the maximum value. This may not result in correct operation on the memory interface. Therefore, the timing registers should be programmed by software before setting the corresponding bank set valid bit in the configuration register. All the timing parameters are in multiples of memclk cycles.

  • Page 134: Bank Set Timing Register B

    Table A–8 (Cont.) Bank Set Timing Register A Field Name Type Description <11:9> S8_RDLYROW RW, 1 Read delay from row address. Delay from row address to latching first valid read data. P rogrammed value desired value <8:7> S8_COLHOLD RW, 1 Column hold.

  • Page 135: Bank Set Timing Register B

    Figure A–15 Bank Set Timing Register B 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 S8_WHOLD0COL S8_WHOLD0ROW S8_TCP S8_WTCAS S8_RTCAS LJ-04192.AI System Register Descriptions A–21...
  • Page 136 Table A–9 Bank Set Timing Register B Field Name Type Description <15:14> Reserved — <13:11> S8_WHOLD0COL RW, 1 Write hold time from column address. Used only for the first data when starting in page mode. Write data is valid with the column address and is held valid S8_WHOLD0COL + 2 cycles after the column address.

  • Page 137: Global Timing Register

    A.1.8.7 Global Timing Register The global timing register contains parameters that are common to all memory bank sets. Each parameter counts memclk cycles. All pins on the memory interface are referenced to memclk rising. The global timing register is shown in Figure A–16 and is defined in Table A–10.

  • Page 138: Refresh Timing Register

    A.1.8.8 Refresh Timing Register The refresh timing register contains refresh timing information used to simultaneously refresh all bank sets using CAS-RAS refresh. Therefore, these parameters should be programmed to the most conservative values across all sets. All the timing parameters are in multiples of memclk cycles. The parameters have a minimum value that is added to the programmed value.

  • Page 139: Decchip 21071-Da Csr Descriptions

    Table A–11 (Cont.) Refresh Timing Register Field Name Type Description <6:4> REF_RASWIDTH RW, 1 Refresh RAS width. Refresh RAS assertion width from b<3:0>_ras0_l assertion to b<3:0>_ras0_l deassertion. b<3:0>_cas0_l is deasserted with b<3:0>_ras0_l for refresh. Corresponds to DRAM parameter P rogrammed value desired value <3:1>...

  • Page 140: Diagnostic Control And Status Register

    A.2.2 Diagnostic Control and Status Register The diagnostic control and status register (DCSR) provides control of operational and diagnostic modes, and it reports status and error conditions. The register is shown in Figure A–18 and is defined in Table A–12. Figure A–18 Diagnostic Control and Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PASS2...

  • Page 141: Sysbus Error Address Register

    Table A–12 Diagnostic Control and Status Register Field Name Type Description <31> PASS2 Pass 2. Chip version reads low on pass 1 and high on pass 2. <30:22> Reserved — <21:18> PCMD PCI command. This field indicates the PCI type when a PCI-initiated error is logged in the DCSR.

  • Page 142: Pci Error Address Register

    (address and data cycles, DMA and I/O transactions). Parity generation is not affected. <3> DCEI RW, 0 Disable correctable error interrupt. Not applicable. Longword parity is implemented on the Alpha PCI 64-275. <2> PENB RWC, 0 Prefetch enable bit. If this bit is set, the sysBus master state machine will enable prefetching on DMA read transactions.

  • Page 143: Diagnostic Control And Status Register Field D_Byp<1:0

    Table A–12 (Cont.) Diagnostic Control and Status Register Field Name Type Description <0> TENB RW, 0 TLB enable. When this bit is set, the entire TLB is enabled. When the bit is cleared, the TLB will be turned off and subsequent scatter-gather read transactions will not result in allocation of TLB entries.
  • Page 144 A.2.3 sysBus Error Address Register The sysBus error address register holds the sysBus address that was being used when an error happened. The register is shown in Figure A–19 and is defined in Table A–14. Figure A–19 sysBus Error Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SYS_ERR<33:5>...

  • Page 145: Pci Error Address Register

    A.2.4 PCI Error Address Register The PCI error address register holds the PCI address ad<31:0> that was being used when an error happened. The register is shown in Figure A–20 and is defined in Table A–15. Figure A–20 PCI Error Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_ERR<31:0>...

  • Page 146: Translated Base Registers 1 And 2 . . . . . . . . . . . . . . . . . . . . . Pci Base Registers 1 And

    A.2.5 Translated Base Registers 1 and 2 The translated base registers 1 and 2 provide the base address when mapping is enabled or disabled. The registers are shown in Figure A–21 and are defined in Table A–16. Figure A–21 Translated Base Registers 1 and 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 T_BASE<32:10>...
  • Page 147 A.2.6 PCI Base Registers 1 and 2 PCI base registers 1 and 2 provide the base address of the target window. The registers are shown in Figure A–22 and are defined in Table A–17. Figure A–22 PCI Base Registers 1 and 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_BASE<31:20>...

  • Page 148: Pci Mask Registers 1 And 2 . . . . . . . . . . . . . . . . . . . . . . . . . A.2.8 Host Address Extension Register 0

    A.2.7 PCI Mask Registers 1 and 2 PCI mask registers 1 and 2 define the size of the target window. The registers are shown in Figure A–23 and are defined in Table A–18. Figure A–23 PCI Mask Registers 1 and 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_MASK<31:20>...

  • Page 149: Host Address Extension Register

    A.2.8 Host Address Extension Register 0 The host address extension register is hardcoded to zero. A read transaction from this register returns zero; a write transaction has no effect. The register is shown in Figure A–24. Figure A–24 Host Address Extension Register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hardcoded to Zero LJ-04201.AI...
  • Page 150 Table A–19 (Cont.) Host Address Extension Register 1 Field Name Type Description <26:0> Reserved — A–36 System Register Descriptions...

  • Page 151: Host Address Extension Register

    A.2.10 Host Address Extension Register 2 The host address extension register 2 generates ad<31:24> on CPU-initiated transactions addressing PCI I/O space. It also generates ad<1:0> during PCI configuration read and write transactions. The register is shown in Figure A–26 and is defined in Table A–20. Figure A–26 Host Address Extension Register 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 EADDR<7:0>...

  • Page 152: Pci Master Latency Timer Register

    A.2.11 PCI Master Latency Timer Register The PCI master latency timer register contains a value that determines the latency timer period. It should be programmed to be nonzero during system configuration. The register is shown in Figure A–27 and is defined in Table A–21.

  • Page 153: Tlb Tag Registers 0 Through

    A.2.12 TLB Tag Registers 0 Through 7 The TLB tag registers contain the PCI page address associated with the CPU page address in the TLB data registers. The registers are shown in Figure A–28 and are defined in Table A–22. Figure A–28 TLB Tag Registers 0 Through 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_PAGE<31:13>...

  • Page 154: Tlb Data Registers 0 Through

    A.2.13 TLB Data Registers 0 Through 7 The TLB data registers contain the CPU page address associated with the PCI page address in the TLB tag registers. The registers are shown in Figure A–29 and are defined in Table A–23. Figure A–29 TLB Data Registers 0 Through 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CPU_PAGE<32:13>...

  • Page 155: Srom Initialization

    SROM Initialization The Alpha 21064A microprocessor provides a mechanism for loading the initial instruction stream (Istream) from a compact serial ROM (SROM) to start the bootstrap procedure. The SROM executable image is limited to the size of the CPU instruction cache (Icache). This code is limited to performing the system initialization necessary to boot the next level of firmware contained in the...

  • Page 156: Firmware Interface

    9. Copy the contents of the flash ROM to memory and begin code execution. 10. Pass parameters up to the next level of firmware to provide a predictable firmware interface. B.1.1 Firmware Interface A firmware interface provides a mechanism for passing critical information about the state of the system and CPU to the next level of firmware.
  • Page 157 Note that this may be a multiple of the actual internal cycle count of the microprocessor as specified in the Alpha Architecture Reference Manual. (A microprocessor will increment the processor cycle count a multiple of the microprocessor clock where the multiple is a power of 2, including 2 = 1.)

  • Page 158: Automatic Cpu Speed Detection

    B.1.3 CPU Bus Interface Timing The Alpha PCI 64-275 L2 cache timing is based on CPU speed in addition to fixed delays associated with the L2 cache subsystem. The pertinent L2 cache delays used in the calculations result from the logic devices used in the L2 cache subsystem, SRAM specifications, and board etch delays.

  • Page 159: Sram Timing Specification Definitions

    Table B–3 SRAM Timing Specification Definitions Parameter Definition Tacc Access from address valid to data valid Write cycle time Write pulse width Data setup to write pulse deassertion Data hold from write pulse deassertion Address setup to write pulse deassertion Address hold from write pulse deassertion Address setup to write pulse assertion SROM Initialization B–5...

  • Page 160: L2 Cache Read And Write Calculations

    Table B–4 Worst-Case SRAM Timing Specifications Typical SRAM Timing Specifications 6-ns 8-ns 10-ns 12-ns 15-ns Parameter SRAM SRAM SRAM SRAM SRAM Tacc 6 ns 8 ns 10 ns 12 ns 15 ns 6 ns 8 ns 10 ns 12 ns 15 ns 6 ns 8 ns...

  • Page 161: Write Cycle Timing

    Write Cycle Calculations WRsetup is the earliest from the beginning of a write cycle that the write pulse can be asserted (see Figure B–1). Figure B–1 Write Cycle Timing WRsetup WRpulse WRhold LJ-04207.AI W Rsetup T adr T buf T adr skew Taddress, based on the address path, and Tdata, based on the data path determine the earliest from the beginning of a write cycle that the write pulse...

  • Page 162: Memory Initialization

    B.1.5 Memory Initialization The memory banks must be configured such that they are naturally aligned. For example, a bank configured with 32MB must have a base address of zero or some multiple of 32MB. Therefore, to ensure that both banks are contiguous (no gaps), the larger bank should be set to a base of zero, and the smaller bank should be set to the address immediately following the last location in the larger bank.

  • Page 163: L2 Cache Initialization

    B.1.6 L2 Cache Initialization These steps initialize L2 cache: 1. Set the BIU_CTL register in the CPU to ignore the L2 cache. 2. Set the general control register in the memory controller to enable the L2 cache while ignoring tag parity. 3.

  • Page 164: Flash Rom (System Rom)

    B.1.7 Flash ROM (System ROM) The flash ROM, sometimes called the system ROM, is a 1MB, nonvolatile, writable ROM. After the SROM code initializes the Alpha PCI 64-275 system, flash ROM code prepares the system for booting. The flash ROM headers, structure, and access methods are described here.

  • Page 165: Special Header Entry Descriptions

    Table B–6 describes each entry in the special header. Table B–6 Special Header Entry Descriptions Entry Description Validation and inverse This quadword contains a special signature pattern used to validation pattern validate that the special ROM header has been located. The pattern is 5A5AC3C3A5A53C3C.

  • Page 166: Flash Rom Structure

    first image if the jumper is not installed (BOOT_OPTION is 0). If the jumper is installed, the Alpha PCI 64-275 will read the value at location 3F in the TOY RAM. The Alpha PCI 64-275 uses that value found at TOY RAM location 3F to determine which image is selected (see Table B–7).

  • Page 167: Higher 512Kb Flash Rom Image Selection

    If n=1,2, . . . , the SROM code loads the first image, second image, and so on. Operating system type. Found at TOY RAM address 3F. Note: The Alpha PCI 64-275 does not support OpenVMS. Found in image header.
  • Page 168 0 to 1. Use the debug monitor command to verify that the selected image bootopt has changed from 0 to 1. The Alpha PCI 64-275 uses the same firmware as the AlphaPC64, so the firmware AplhaPC64> prompts appear as B–14 SROM Initialization...

  • Page 169: Flash Rom Access

    The address range for the higher bank is 3 FFF8 0000 to 3 FFFF FFFF, the same as for the lower bank. Access is now to the higher bank and will continue until the Alpha PCI 64-275 is reset or a 0 is written to the register at address 800.

  • Page 170: Icache Flush Code

    At this point r0 contains the starting address where the flash ROM image was loaded into memory. B.1.9 Alpha PCI 64-275 Configuration Jumpers The memory controller provides presence detect registers that contain the state of the presence detect pins at reset.

  • Page 171: C Pci Address Maps

    PCI Address Maps This appendix provides the Alpha PCI 64-275 PCI operating register address space maps. C.1 PCI Interrupt Acknowledge/Special Cycle Address Space The PCI interrupt acknowledge/special cycle address space comprises an address range from 1 B000 0000 through 1 BFFF FFFF.
  • Page 172 Table C–1 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address Space Offset Address Register 1 C000 00E0 DMA1 CH3 base and current count register 1 C000 0100 DMA1 status and command register 1 C000 0120 DMA1 write request register 1 C000 0140 DMA1 write single mask bit register 1 C000 0160 DMA1 write mode register...
  • Page 173 Table C–1 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address Space Offset Address Register 1 C000 1120 DMA channel 6 page register 1 C000 1140 DMA channel 7 page register 1 C000 1160 DMA channel 5 page register 1 C000 1180 DMA page register reserved 1 C000 11A0 DMA page register reserved...
  • Page 174 Table C–1 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address Space Offset Address Register 1 C000 1A40 DMA2 write request register 1 C000 1A80 DMA2 write single mask bit register 1 C000 1AC0 DMA2 write mode register 1 C000 1B00 DMA2 clear byte pointer register 1 C000 1B40 DMA2 master clear register 1 C000 1B80...

  • Page 175: Pci Configuration Address Space

    Table C–1 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address Space Offset Address Register 428–42B 1 C000 8518 CH2 scatter-gather descriptor table pointer register 42C–42F 1 C000 8598 CH3 scatter-gather descriptor table pointer register 434–437 1 C000 8698 CH5 scatter-gather descriptor table pointer register 438–43B 1 C000 8718 CH6 scatter-gather descriptor table pointer register...

  • Page 176: Sio Pci-To-Isa Bridge Configuration Address Space

    C.5 SIO PCI-to-ISA Bridge Configuration Address Space Table C–3 is a map of SIO PCI-to-ISA bridge configuration address space. PCI address bit pci_ad19 drives the idsel chip select pin for access to the configuration register space. Table C–3 SIO PCI-to-ISA Bridge Configuration Address Space Map Offset Address Register...

  • Page 177: Pci Sparse Memory Address Space

    Table C–3 (Cont.) SIO PCI-to-ISA Bridge Configuration Address Space Map Offset Address Register 80–81 1 E008 1008 BIOS timer base address register C.6 PCI Sparse Memory Address Space The PCI sparse memory address space comprises an address range from 2 0000 0000 through 2 7FFF FFFF. C.7 PCI Dense Memory Address Space The PCI dense memory address space comprises an address range from 3 0000 0000 through 3 FFFF FFFF.

  • Page 178: Pc87312 Combination Controller Register Address Space Map

    Table C–4 PC87312 Combination Controller Register Address Space Map Address Offset Physical Read/Write Address Register General Registers 1 C000 7300 Index address register 1 C000 7320 Data address register Index Register Function enable register Function address register Power and test register COM2 Serial Port Registers 2F8-R 0DLAB=0 1 C000 5F00...
  • Page 179 Table C–4 (Cont.) PC87312 Combination Controller Register Address Space Address Offset Physical Read/Write Address Register Diskette Registers 3F0-R 1 C000 7E00 Status A register 3F1-R 1 C000 7E20 Status B register 3F2-R/W 1 C000 7E40 Digital output register 3F3-R/W 1 C000 7E60 Tape drive register 3F4-R 1 C000 7E80...

  • Page 180: Utility Bus Device Address

    Table C–4 (Cont.) PC87312 Combination Controller Register Address Space Address Offset Physical Read/Write Address Register Parallel Port Registers 3BC-R/W 1 C000 7780 Data register 3BD-R 1 C000 77A0 Status register 3BE-R/W 1 C000 77C0 Control register 1 C000 77E0 None (tristate bus) Table C–5 Integrated Device Electronics (IDE) Register Addresses Address Physical...

  • Page 181: Utility Bus Device Decode

    Table C–6 Utility Bus Device Decode Device Address Select Bits Device Select Device Address ecsen_l ecasaddr_2 ecasaddr_1 ecasaddr_0 Signal Selected Decode rtcale_l TOY address 70, 72, 74, 76 rtccs_l TOY data 71, 73, 75, 77 kbcs_l Mouse/ 60, 62, Keyboard 64, 66 enable flashcs_l...

  • Page 182: Interrupt Control Pld Addresses

    C.10 Interrupt Control PLD Addresses Table C–7 lists the registers and memory addresses for the interrupt control PLD. Table C–7 Interrupt Control PLD Addresses Offset Physical Address Register 1 C001 0080 Interrupt status/interrupt mask register 1 1 C001 00A0 Interrupt status/interrupt mask register 2 1 C001 00C0 Interrupt status/interrupt mask register 3 C.11 8242PC Keyboard and Mouse Controller Addresses...

  • Page 183: Flash Rom

    Table C–9 Time-of-Year Clock Device Addresses Index Physical Offset Latched Address Register 1 C000 0E00 Seconds 1 C000 0E00 Seconds alarm 1 C000 0E00 Minutes 1 C000 0E00 Minutes alarm 1 C000 0E00 Hour 1 C000 0E00 Hour alarm 1 C000 0E00 Day of week 1 C000 0E00 Day of month...

  • Page 184: Flash Memory Segment Select Register

    C.13.1 Flash Memory Segment Select Register Table C–10 lists the register address for the flash ROM. The flash ROM is partitioned into two 512KB segments. Write a value of 0 to ISA address 800 to select the lower 512KB. Write a value of 1 to ISA address 800 to select the higher 512KB.

  • Page 185: Flash Rom Memory Map

    Intel Flash Memory document. Accessing the flash ROM registers requires byte access, which is only possible through use of PCI sparse memory space. The Alpha PCI 64-275 flash ROM resides in PCI memory address range FFF8 0000 to FFFF FFFF. See Section 4.1.8 for information about accessing this address range through sparse...
  • Page 186 Table C–13 Memory Map of Flash Memory Block Offset Physical Address Number Capacity 0 0000– 3 FFF8 0000– 64KB 0 FFFF 3 FFF8 FFFF 1 0000– 3 FFF9 0000– 64KB 1 FFFF 3 FFF9 FFFF 2 0000– 3 FFFA 0000– 2,10 64KB 2 FFFF...

  • Page 187: Technical Support

    Ordering Information D.1 Technical Support If you need technical support with your Alpha PCI Motherboard, contact your local Digital representative. Please provide your local representative with the model number and if possible a brief description of the problem you are encountering.

  • Page 188: Ordering Associated Literature

    Alpha PCI 64-275 documentation set EK–AL275–DK Alpha Microprocessors Motherboard Debug Monitor User’s Guide Alpha Microprocessors SROM Mini-Debugger User’s GUide Alpha PCI 64-275 User’s Manual Alpha PCI 64-275 User’s Guide Alpha PCI 64-275 Microsoft Windows NT Installation Guide D–2 Technical Support and Documentation Ordering Information...

  • Page 189: Ordering Third-Party Documentation

    D.3 Ordering Third-Party Documentation You can order the following documentation directly from the vendor: Documentation Order Number 82420/82430 PCIset ISA and EISA Bridges (includes Intel No 290483 82378ZB SIO) PC87311/PC87312 (Super I/O™ II/III) Floppy Disk National Semiconductor Controller with Dual UARTs, Parallel Port, and IDE No 11362 Interface UPI-41AH/42AH Universal Peripheral Interface 8-Bit...
  • Page 191 Address stepping in configuration cycles, CSR descriptions, A–25 to A–40 3–17 See also specific register entries Alpha documentation, D–2 CSR space, 4–7 Alpha PCI 64-275 introduction, 1–1 functional description, 3–13 Arbitration PCI interface, 3–14 PCI, 3–29 sysBus interface, 3–14 scheme, 3–32 overview, 3–4...
  • Page 192 Components, 1–1 Configuration registers, A–14 Connectors BA error checking, 3–22 board reset, 2–12 Bank set timing register A, A–18 COM1, 2–9 Bank set timing register B, A–18 COM2, 2–9 Base address registers, A–13 CPU fan, 2–11 BC_SIZE<2:0> jumpers, 2–4 disk access LED, 2–12 BC_SPEED<2:0>...
  • Page 193 Flash ROM (cont’d) Diagnostic control and status register, A–26 TOY RAM location 3F, B–13 Disk access LED connector, 2–12 update-enable jumper, B–15 Diskette drive connector, 2–9 DMA address translation, 3–14 DMA read buffer, 3–15 General control register, A–1 DMA write buffer, 3–15, 3–22 Global timing register, A–23 Document conventions, xiv Graphics interface, 3–33...
  • Page 194 ISA devices, 3–34 combination controller, 3–34, 3–35 ISA expansion slots, 3–37 memData bus, 3–21 time-of-year clock, 3–36 Memory address generation, 3–11 utility bus memory devices, 3–36 Memory and register contents radix, xv ISA expansion slots, 3–37 Memory control registers, A–11 to A–25 ISA interface overview, 1–4 bank set timing register A, A–18 bank set timing register B, A–18...
  • Page 195 PCI interface overview, 1–4 PCI interrupt acknowledge/special cycle, 4–8 PAL control set, 1–2 PCI interrupt logic, 3–29 Parallel port connector, 2–9 PCI mask register 1, A–34 Parameters, 5–1, 5–2 PCI mask register 2, A–34 PC87312 register address map, C–7, C–8 PCI master latency timer register, A–38 PCI master timeout, 3–17 arbitration, 3–29, 3–32...
  • Page 196 sysBus interface (cont’d) I/O write transaction buffering, 3–14 wrapping mode, 3–14 sysBus output selectors, 3–22 Saturn IO chip sysData bus, 3–20 See SIO chip System address mapping Serial ROM CPU-to-PCI address space, 4–1 See SROM System address space Serial ROM code, 1–5, 3–40 21071-CA CSR space, 4–5 Should be zero, xv 21071-DA CSR space, 4–7...
  • Page 197 See Ubus Ubus, 1–4 address decode, C–10 Video frame pointer register, A–11 memory devices, 3–36 UNDEFINED, xiv UNPREDICTABLE, xiv Wrapping mode, 3–14 Utility bus Index–7...

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