Sign In
Upload
Manuals
Brands
Active-Semi Manuals
Controller
PAC5223
User Manuals: Active-Semi PAC5223 Controller
Manuals and User Guides for Active-Semi PAC5223 Controller. We have
1
Active-Semi PAC5223 Controller manual available for free PDF download: Product User Manual
Active-Semi PAC5223 Product User Manual (360 pages)
Power Application Controller
Brand:
Active-Semi
| Category:
Controller
| Size: 6 MB
Table of Contents
Table of Contents
2
List of Figures
21
Styles and Formatting Conventions
24
Overview
24
Number Representation
24
Formatting Styles
24
Memory and Register Map
25
Memory Map
25
Figure 2-1. Memory Map
25
Register Map
26
Table 2-1. Embedded FLASH Register Map
26
Table 2-2. ROM Register Map
27
Table 2-3. System Clock Control Register Map
28
Table 2-4. FLASH Memory Controller Register Map
29
Table 2-5. Watchdog Timer Register Map
29
Table 2-6. General Purpose Timer Register Map
29
Table 2-7. GPIO Port a Register Map
29
Table 2-8. GPIO Port B Register Map
30
Table 2-9. GPIO Port AB Register Map
31
Table 2-10. GPIO Port C Register Map
31
Table 2-11. GPIO Port D Register Map
31
Table 2-12. GPIO Port CD Register Map
32
Table 2-13. GPIO Port E Register Map
32
Table 2-14. Timer a Register Map
33
Table 2-15. Timer B Register Map
34
Table 2-16. Timer C Register Map
34
Table 2-17. Timer D Register Map
35
Table 2-18. EMUX Register Map
35
Table 2-19. ADC Register Map
35
Table 2-20. ADC Auto-Sampling Sequencer 0 Register Map
35
Table 2-21. ADC Auto-Sampling Sequencer 1 Register Map
36
Table 2-22 . I2C Register Map
36
Table 2-23. UART Register Map
37
Table 2-24. SOC Bus Bridge Register Map
37
Table 2-25. SPI Register Map
38
Table 2-26. Multi-Mode Power Manager Register Map
38
Information Block
39
Register
39
Register Map
39
Rosc11
39
Adcgain
39
Adcoff
39
Table 3-1. Information Block Register Map
39
Register 3-1. ROSC11 (ROSC11 Frequency Value, 0X0010 0010)
39
Register 3-2. ADCGAIN (ADC Gain Value, 0X0010 0020)
39
Register 3-3. ADCOFF (ADC Offset, 0X0010 0024)
39
Fttemp
40
Temps
40
Clkref
40
Pacidr
40
Details of Operation
40
Overview
40
Register 3-4. FTTEMP (FT Temp Value, 0X0010 0028)
40
Register 3-5. TEMPS (Temperature Sensor Reading, 0X0010 002A)
40
Register 3-6. CLKREF (CLKREF Frequency Value, 0X0010 002C)
40
Register 3-7. PACIDR (PAC Part Number and Revision, 0X0010 0044)
40
Register 4-1. CCSCTL (System Clock Control, 0X4000 0000)
41
Pllctl
42
Oscctl
42
Xtalctl
42
System Clock Control
41
Register
41
Register Map
41
Ccsctl
41
Table 4-1. System Clock Control Register Map
41
Register 4-2. PLLCTL (PLL Control, 0X4000 0004)
42
Register 4-3. OSCCTL (Ring Oscillator Control, 0X4000 0008)
42
Register 4-4. XTALCTL (Crystal Driver Control, 0X4000 000C)
42
Details of Operation
43
Block Diagram
43
Configuration
43
Figure 4-1. System Clock Control
43
Rosc
44
Clkref
44
Xtal
44
Extclk
44
Pll
44
Frclk
45
Fclk
45
Hclk
45
Aclk
45
Clock Gating
45
Table 4-5. PLL Output Frequency Settings Using 4Mhz ROSC as Input
45
Register 5-1. WDTCTL (Watchdog Timer Control, 0X4003 0000)
46
Wdtcdv
47
Wdtctr
47
Watchdog Timer
46
Register
46
Register Map
46
Wdtctl
46
Table 5-1. Watchdog Timer Register Map
46
Register 5-2. WDTCDV (Watchdog Timer Count-Down Value, 0X4003 0004)
47
Register 5-3. WDTCTR (Watchdog Timer Counter, 0X4003 0008)
47
Details of Operation
48
Block Diagram
48
Configuration
48
Watchdog Timer
48
Access WDT Registers
48
WDT Clock Setting
48
General Purpose Timer Mode
48
Figure 5-1. WDT
48
Watchdog Timer Mode
49
GPIO Port a
50
Register
50
Register Map
50
Gpioao
50
Table 6-1. GPIO Port a Register Map
50
Register 6-1. GPIOAOUT (GPIO Port a Output, 0X4007 0000)
50
Gpioaouten
51
Gpioads
51
Register 6-2. GPIOAOUTEN (GPIO Port a Output Enable, 0X4007 0004)
51
Register 6-3. GPIOADS (GPIO Port a Output Drive Strength, 0X4007 0008)
51
Gpioapu
52
Register 6-4. GPIOAPU (GPIO Port a Weak Pull Up, 0X4007 000C)
52
Gpioapd
53
Gpioain
53
Register 6-5. GPIOAPD (GPIO Port a Weak Pull Down, 0X4007 0010)
53
Register 6-6. GPIOAIN (GPIO Port a Input, 0X4007 0014)
53
Gpioapsel
54
Register 6-7. GPIOAPSEL (GPIO Port a Peripheral Select, 0X4007 001C)
54
Gpioaintp
55
Gpioainte
55
Register 6-8. GPIOAINTP (GPIO Port a Interrupt Polarity, 0X4007 0020)
55
Register 6-9. GPIOAINTE (GPIO Port a Interrupt Enable, 0X4007 0024)
55
Gpioaintf
56
Register 6-10. GPIOAINTF (GPIO Port a Interrupt Flag, 0X4007 0028)
56
Gpioaintm
57
Register 6-11. GPIOAINTM (GPIO Port a Interrupt Mask, 0X4007 002C)
57
Details of Operation
58
Block Diagram
58
Configuration
58
GPIO a Block
58
Input
58
Output and Output Enable
58
Figure 6-1. GPIO Port a
58
Output Drive Strength
59
Weak Pull up and Pull down
59
Peripheral Select
59
Interrupt
59
GPIO Port B
60
Register
60
Register Map
60
Gpiobout
60
Gpiobouten
60
Table 7-1. GPIO Port B Register Map
60
Register 7-1. GPIOBOUT (GPIO Port B Output, 0X4007 0040)
60
Register 7-2. GIOBOUTEN (GPIO Port B Output Enable, 0X4007 0044)
60
Gpiobds
61
Gpiobpu
61
Register 7-3. GPIOBDS (GPIO Port B Output Drive Strength, 0X4007 0048)
61
Register 7-4. GPIOBPU (GPIO Port B Weak Pull Up, 0X4007 004C)
61
Gpiobpd
62
Gpiobin
62
Gpiobpsel
62
Register 7-5. GPIOBPD (GPIO Port B Weak Pull Down, 0X4007 0050)
62
Register 7-6. GPIOBIN (GPIO Port B Input, 0X4007 0054)
62
Register 7-7. GPIOBPSEL (GPIO Port B Peripheral Select, 0X4007 005C)
62
Gpiobintp
63
Register 7-8. GPGPIOIOBINTP (GPIO Port B Interrupt Polarity, 0X4007 0060)
63
Gpiobinte
64
Gpiobintf
64
Register 7-10. GPIOBINTF (GPIO Port B Interrupt Flag, 0X4007 0068)
64
Gpiobintm
65
Register 7-9. GPIOBINTE (GPIO Port B Interrupt Enable, 0X4007 0064)
64
Register 7-11. GPIOBINTM (GPIO Port B Interrupt Mask, 0X4007 006C)
65
Details of Operation
66
Block Diagram
66
Configuration
66
GPIO B Block
66
Input
66
Output and Output Enable
66
Output Drive Strength
66
Figure 7-1. GPIO Port B
66
Weak Pull up and Pull down
67
Peripheral Select
67
Interrupt
67
GPIO Port C
68
Register
68
Register Map
68
Gpiocout
68
Table 8-1. GPIO Port C Register Map
68
Register 8-1. GPIOCOUT (GPIO Port C Output, 0X4008 0000)
68
Gpiocouten
69
Gpiocin
69
Register 8-2. GPIOCOUTEN (GPIO Port C Output Enable, 0X4008 0004)
69
Register 8-3. GPIOCIN (GPIO Port C Input, 0X4008 0018)
69
Gpiocine
70
Register 8-4. GPIOCINE (GPIO Port C Input Enable, 0X4008 0014)
70
Gpiocintp
71
Gpiocinte
71
Register 8-5. GPIOCINTP (GPIO Port C Interrupt Polarity, 0X4008 0020)
71
Register 8-6. GPIOCINTE (GPIO Port C Interrupt Enable, 0X4008 0024)
71
Gpiocintf
72
Gpiocintm
72
Register 8-7. GPIOCINTF (GPIO Port C Interrupt, 0X4008 0028)
72
Register 8-8. GPIOCINTM (GPIO Port C Interrupt Mask, 0X4008 002C)
72
Details of Operation
74
Block Diagram
74
Configuration
74
GPIO C Block
74
Analog Input
74
Output and Output Enable
74
Interrupt
74
Figure 8-1. GPIO Port C
74
GPIO Port D
76
Register
76
Register Map
76
Gpiodo
76
Table 9-1. GPIO Port D Register Map
76
Register 9-1. GPIODO (GPIO Port D Output, 0X4008 0040)
76
Gpiodouten
77
Gpiodds
77
Register 9-2. GPIODOUTEN (GPIO Port D Output Enable, 0X4008 0044)
77
Register 9-3. GPIODDS (GPIO Port D Output Drive Strength, 0X4008 0048)
77
Gpiodpu
78
Register 9-4. GPIODPU (GPIO Port D Weak Pull Up, 0X4008 004C)
78
Gpiodpd
79
Gpiodin
79
Register 9-5. GPIODPD (GPIO Port D Weak Pull Down, 0X4008 0050)
79
Register 9-6. GPIODIN (GPIO Port D Input, 0X4008 0054)
79
Gpiodpsel
80
Gpiodintp
81
Gpiodinte
81
Gpiodintf
82
Gpiodintm
82
Details of Operation
84
Block Diagram
84
Configuration
84
GPIO D Block
84
Input
84
Output and Output Enable
84
Figure 9-1. GPIO Port D
84
Output Drive Strength
85
Weak Pull up and Pull down
85
Peripheral Select
85
Interrupt
85
GPIO Port E
86
Register
86
Register Map
86
Gpioeout
86
Table 10-1. GPIO Port E Register Map
86
Gpioeouten
87
Gpioeds
87
Gpioepu
88
Gpioepd
89
Gpioein
89
Gpioepsel
90
Gpioeintp
91
Gpioeinte
91
Gpioeintf
92
Gpioeintm
92
Details of Operation
94
Block Diagram
94
Configuration
94
GPIO E Block
94
Input
94
Output and Output Enable
94
Output Drive Strength
94
Figure 10-1. GPIO Port E
94
Weak Pull up and Pull down
95
Peripheral Select
95
Interrupt
95
General Purpose Timer
96
Register
96
Register Map
96
Rtcctl
96
Table 11-1. General Purpose Timer Register Map
96
Rtccdv
97
Rtcctr
97
Details of Operation
98
Block Diagram
98
Configuration
98
General Purpose Timer
98
Access GPT Registers
98
GPT Clock
98
General Purpose Timer Mode
98
Figure 11-1. GPT
98
Timer a
99
Register
99
Register Map
99
Table 12-1. Timer a Register Map
99
Tactl
100
Taprd
101
Tactr
101
Tacc0Ctrl
101
Tacc0Ctr
101
Tacc1Ctrl
102
Tacc1Ctr
102
Tacc2Ctrl
102
Tacc2Ctr
103
Tacc3Ctrl
103
Tacc3Ctr
103
Tacc4Ctrl
103
Tacc4Ctr
104
Tacc5Ctrl
104
Tacc5Ctr
104
Tacc6Ctrl
105
Tacc6Ctr
105
Tacc7Ctrl
105
Tacc7Ctr
106
Dtga0Ctl
106
Dtga0Led
106
Dtga0Ted
106
Dtga1Ctl
107
Dtga1Led
107
Dtga1Ted
107
Dtga2Ctl
107
Dtga2Led
108
Dtga2Ted
108
Dtga3Ctl
108
Dtga3Led
109
Dtga3Ted
109
Details of Operation
110
Block Diagram
110
Configuration
110
Timer a Block
110
Timer
110
Figure 12-1. Timer a
110
Register Update
111
Timer Modes
111
Single Shot Mode
111
Input Clock and Pre-Scaler
111
Timer Synchronization
111
Pwm/Compare Units
112
Timer and Pwm/Capture Interrupt
113
Figure 12-2. Pwma[X] and Pwma[X+4] Example Using Timer a up Mode and Up/Down Mode
113
Figure 12-3. Ca[X] and Ca[X+4] Capture Example
113
Dead-Time Generator
114
Figure 12-4. Dtgax Bypass Example
114
Figure 12-5. Dtgax Bypass and Inverting LS Example
115
Figure 12-6. Dtgax LED and TED Example
115
PWM Output and Capture Input Pin Selection
116
Table 12-2. Timer a Signal to Pin Mapping
116
Figure 12-7. Dtgax LED and TED with on Time Preservation Example
116
Timer B
117
Register
117
Register Map
117
Tbctl
117
Table 13-1. Timer B Register Map
117
Tbprd
118
Tbctr
118
Tbcc0Ctrl
118
Tbcc0Ctr
119
Tbcc1Ctrl
119
Tbcc1Ctr
119
Tbcc2Ctrl
120
Tbcc2Ctr
120
Tbcc3Ctrl
120
Tbcc3Ctr
121
Dtgb0Ctl
121
Dtgb0Led
121
Dtgb0Ted
122
Details of Operation
123
Block Diagram
123
Configuration
123
Timer B Block
123
Timer
123
Figure 13-1. Timer B
123
Register Update
124
Timer Modes
124
Single Shot Mode
124
Input Clock and Pre-Scaler
124
Timer Synchronization
124
Pwm/Compare Units
125
Timer and Pwm/Capture Interrupt
126
Figure 13-2. PWMB0 and PWMB1 Example Using Timer B up Mode and Up/Down Mode
126
Figure 13-3. CB0 and CB1 Capture Example
126
Dead-Time Generator
127
Figure 13-4. DTGB0 Bypass Example
127
Figure 13-5. DTGB0 Bypass and Inverting LS Example
128
Figure 13-6. DTGB0 LED and TED Example
128
PWM Output and Capture Input Pin Selection
129
Table 13-2. Timer B Signal to Pin Mapping
129
Figure 13-7. DTGB0 LED and TED with on Time Preservation Example
129
Timer C
130
Register
130
Register Map
130
Tcctl
130
Table 14-1. Timer C Register Map
130
Tcprd
131
Tcctr
131
Tccc0Ctrl
131
Tccc0Ctr
132
Dtgc0Ctl
133
Figure 14-1. Timer C
134
Details of Operation
134
Register Update
135
Pwm/Compare Units
136
Figure 14-2. PWMC0 and PWMC1 Example Using Timer C up Mode and Up/Down Mode
137
Figure 14-3. CC0 and CC1 Capture Example
137
Timer and Pwm/Capture Interrupt
137
Dead-Time Generator
138
Figure 14-4. DTGC0 Bypass Example
138
Figure 14-5. DTGC0 Bypass and Inverting LS Example
139
Figure 14-6. DTGC0 LED and TED Example
139
Figure 14-7. DTGC0 LED and TED with on Time Preservation Example
140
PWM Output and Capture Input Pin Selection
140
Table 14-2. Timer C Signal to Pin Mapping
140
Table 15-1. Timer D Register Map
141
Register
141
Tdprd
142
Tdcc0Ctr
143
Dtgd0Ctl
144
Figure 15-1. Timer D
145
Details of Operation
145
Register Update
146
Figure 15-2. PWMD0 and PWMD1 Example Using Timer D up Mode and Up/Down Mode
147
Pwm/Compare Units
147
Figure 15-3. CD0 and CD1 Capture Example
148
Timer and Pwm/Capture Interrupt
148
Figure 15-4. DTGD0 Bypass Example
149
Figure 15-5. DTGD0 Bypass and Inverting LS Example
149
Figure 15-6. DTGD0 LED and TED Example
150
Figure 15-7. DTGD0 LED and TED with on Time Preservation Example
150
PWM Output and Capture Input Pin Selection
150
Table 15-2. Timer D Signal to Pin Mapping
150
Table 16-1. FLASH Memory Controller Register Map
151
Flashctl
152
Flashperase
153
Flashbwdata
154
Figure 16-1. FLASH Memory Controller
155
Details of Operation
155
FLASH Page Erase
156
SWD Debug Access Disable
157
Table 17-1. Register Map - EMUX
158
Table 17-2. Register Map - ADC
158
Table 17-3. Register Map - ADC Auto Sequencer 0
158
ADC and AUTO SEQUENCER
158
Table 17-4. Register Map - ADC Auto Sequencer 1
159
Emuxctl
159
Emuxdata
160
Adcctl
161
Adcint
162
As0Ctl
163
As0S0
164
As0R1
165
As0S3
166
As0R4
167
As0S6
168
As0R7
169
As1S0
170
As1S1
171
As1R2
172
As1S4
173
As1R5
174
As1S7
175
Figure 17-1. ADC, EMUX, ASC0, ASC1
176
ADC, Autosequencer and EMUX
176
Figure 17-2. ADC Conversion (Single Shot)
177
Figure 17-3. ADC Conversion (Repeat Mode)
177
Emux
177
Figure 17-4. Ascx, ADCCTL.ADCMODE = 001B, 010B, 100B, 101B
178
Figure 17-5. Ascx, ADCCTL.ADCMODE = 011B, 110B
178
Figure 17-6. Ascx, ADCCTL.ADCMODE = 111B
179
Figure 17-7. Asxsy Sample with Asxsy.emuxs = 00B and Asxsy.delay = 11B
179
Figure 17-8. Asxsy Sample with Asxsy.emuxs = 01B and Asxsy.delay = 11B
180
Figure 17-9. Asxsy Sample with Asxsy.emuxs = 10B and Asxsy.delay = 11B
180
Figure 17-10. Ascx, 8 Samples, no Collision
180
Figure 17-11. Ascx 8 Samples, Collision
181
Figure 17-12. ASC0 8 Samples, ASC1 4 Samples, Collision
181
Table 18-1 . I2C Register Map
182
Register
182
I2Cie
184
I2Cmrxdata
185
I2Csltxdata
186
Figure 18-1. I2C
187
Details of Operation
187
Figure 18-2. I2C Master Read Transaction
188
I2C Addressing
188
Figure 18-3. I2C Master Read Waveforms
189
Table 19-1. UART Register Map
191
Uart
191
Uartier/Uartdl_H
192
Uartlcr
193
Uartsp
194
Uartier2
195
Figure 19-1. UART
197
Details of Operation
197
Data Settings
199
Table 20-1. SOC Bus Bridge Register Map
200
Socbclkdiv
201
Socbcsstr
202
Socbd
203
Figure 20-1. SOC Bridge
204
Details of Operation
204
Enable and Setup of SOC Bridge
205
Figure 20-2. Single Read from SOC Bridge
205
Figure 20-3. Single Write to SOC Bridge
205
Table 21-1. SPI Register Map
206
Register
206
Spicfg
207
Spiclkdiv
208
Spicsstr
210
Spid
211
Details of Operation
212
Figure 21-2. SPI Clock Polarity and Phase
213
Master Slave Mode
213
Data Format
214
Figure 21-3. SPIMOSI Early Transmit in Master Mode
214
Figure 21-4. SPIMISO Early Transmit in Slave Mode
214
Chip Select Settings
215
Figure 21-5. Spicsx
215
SPI Interrupt
216
Table 22-1. Multi-Mode Power Manager Register Map
217
Devid
218
Pwrstat
219
Imod
220
Table 23-1. Configurable Analog Front End Register Map
222
Soc.cfgaio0
223
Soc.cfgaio2
225
Soc.cfgaio4
227
Soc.cfgaio6
229
Soc.cfgaio7
230
Soc.cfgaio8
231
Soc.cfgaio9
232
Soc.sigset
233
Soc.adcscan
234
Soc.protstat
235
Soc.doutsig1
236
Soc.dinsig1
237
Soc.sigintf
238
Figure 23-1. Configurable Analog Front End
239
Details of Operation
239
Figure 23-2. AIO1, AIO0
240
AIO1, AIO0 Differential Amplifier Mode
241
Figure 23-3. AIO3, AIO2
243
AIO3, AIO2 Differential Amplifier Mode DAO32
244
Figure 23-4. AIO5, AIO4
246
AIO5, AIO4 Differential Amplifier Mode DAO54
247
Figure 23-5. AIO6
249
AIO6 Digital I/O Mode
250
AIO6 Special Mode
251
Figure 23-6. AIO7
253
AIO7 Single Ended Amplifier Mode
254
AIO7 Special Mode
255
Figure 23-7. AIO8
257
AIO8 Digital I/O Mode
258
AIO8 Special Mode
259
Figure 23-8. AIO9
261
AIO9 Digital I/O Mode
262
AIO9 Special Mode
263
Figure 23-9. EMUX
265
EMUX and ADMUX
265
Figure 23-10. EMUX Timing
266
Admux
266
Table 24-1. Application Specific Power Driver Register Map
268
Soc.cfgdrq6
269
Soc.doutdrv
270
Soc.endrv
271
Figure 24-1. Application Specific Power Driver
272
Details of Operation
272
Figure 24-2. ENHS1, ENLS1 Protection
273
Figure 24-3. DRL0
275
DRL0 Low Side Driver
275
Figure 24-4. DRL1
276
DRL1 Low Side Driver
276
Figure 24-5. DRL2
277
DRL2 Low Side Driver
277
Figure 24-6. DRH3
278
DRH3 High Side Driver
278
Figure 24-7. DRH4
279
DRH4 High Side Driver
279
Figure 24-8. DRH5
280
DRH5 High Side Driver
280
Figure 25-1. Cortex-M0 Implementation
281
Arm Cortex-M0 Reference
281
Table 25-1. Summary of Processor Mode and Stack Use Options
283
The Cortex-M0 Processor
283
Table 25-2. Core Register Set Summary
284
Figure 25-2. Core Registers
284
Figure 25-3. PSR
285
Table 25-4. APSR Bit Assignments
286
Table 25-5. IPSR Bit Assignments
286
Table 25-3. Core Register Set Summary
286
Table 25-6. EPSR Bit Assignments
287
Table 25-7. PRIMASK Register Bit Assignments
288
Figure 1-6. CONTROL
288
Table 25-8. CONTROL Register Bit Assignments
289
Memory Model
290
Figure 25-6. Memory Map
291
Figure 25-7. Memory Ordering Restrictions
292
Table 25-9. Memory Access Behavior
293
Figure 25-8. Little Endian Format
295
Exception Model
295
Table 25-10. Properties of the Different Exception Types
296
Figure 25-9. Vector Table
298
Figure 25-10. Exception Entry Stack Contents
300
Table 25-11. Execution Return Behavior
301
Fault Handling
301
Power Management
302
The Cortex-M0 Instruction Set
304
Table 25-12. Cortex-M0 Instructions
305
Table 25-13. CMSIS Intrinsic Functions to Generate some Cortex-M0 Instructions
306
Table 25-14. CMSIS Intrinsic Functions to Access Special Registers
307
About the Instruction Descriptions
307
Figure 25-11. ASR #3
308
Figure 25-12. LSR #3
309
Figure 25-13. LSL #3
310
Figure 25-14. ROR #3
310
Table 25-15. Condition Code Suffixes
312
Table 25-16. Memory Access Instructions
312
Table 25-17. Data Processing Instructions
319
Table 25-18. ADC, ADD, RSB, SBC, and SUB Operand Restrictions
321
Table 25-19. Branch and Control Instructions
331
Table 25-20. Branch Ranges
332
Table 25-21. Miscellaneous Instructions
333
Table 25-22. Core Peripheral Register Regions
343
Table 25-23. NVIC Register Summary
343
Cortex-M0 Peripherals
343
Table 25-24. CMSIS Access NVIC Functions
344
Table 25-25. ISER Bit Assignments
344
Figure 25-15. ISER
344
Table 25-26. ICER Bit Assignments
345
Figure 25-16. ICER
345
Figure 25-17. ISPR
345
Table 25-27. ISPR Bit Assignments
346
Table 25-28. ICPR Bit Assignments
346
Figure 25-18. ICPR
346
Table 25-29. IPR Bit Assignments
347
Figure 25-19. IPR
347
Table 25-30. CMSIS Access NVIC Functions
349
Table 25-31. Summary of the SCB Register
349
System Control Block
349
Table 25-32. CPUID Register Bit Assignments
350
Figure 25-20. CPUID
350
Table 25-33. ICSR Register Bit Assignments
351
Figure 25-21. ICSR
351
Table 25-34. AIRCR Register Bit Assignments
352
Figure 25-22. AIRCR
352
Table 25-35. SCR Register Bit Assignments
353
Figure 25-23. SCR
353
Table 25-36. CCR Register Bit Assignments
354
Figure 25-24. CCR
354
Table 25-37. System Fault Handler Priority Fields
355
Table 25-38. SHPR2 Register Bit Assignments
355
Table 25-39. SHPR3 Register Bit Assignments
355
Table 25-40. System Timer Register Summary
356
System Timer, Systick
356
Table 25-41. SYST_CSR Register Bit Assignments
357
Table 25-42. SYST_RVR Register Bit Assignments
357
Table 25-43. SYST_CVR Register Bit Assignments
358
Table 25-44. SYST_CALIB Register Bit Assignments
358
Legal Information
360
Advertisement
Advertisement
Related Products
Active-Semi PAC5222EVK1
Active-Semi PAC5532EVK1
Active-semi PAC5220WP WPC A11 5V
Active-semi HYDRA-X BLDC
Active-Semi Categories
Motherboard
Controller
Transmitter
Microcontrollers
Automobile Accessories
More Active-Semi Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL