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- Page 1 PRODUCT USER GUIDE PAC5223 Power Application Controller ® Multi-Mode Power Manager Configurable Analog Front End Application Specific Power Drivers © Cortex ® -M0 Controller Core www.active-semi.com Copyright © 2018 Active-Semi, Inc.
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Page 2: Table Of Contents
PAC5223 User Guide Power Application Controller TABLE OF CONTENTS 1. Styles and Formatting Conventions......................... 24 1.1. Overview..............................24 1.2. Number Representation........................... 24 1.3. Formatting Styles............................. 24 2. Memory and Register Map..........................25 2.1. Memory Map............................25 2.2. Register Map............................26 3. - Page 3 PAC5223 User Guide Power Application Controller 5.2.6. General Purpose Timer Mode......................48 5.2.7. Watchdog Timer Mode........................49 6. GPIO Port A..............................50 6.1. Register..............................50 6.1.1. Register Map............................ 50 6.1.2. GPIOAO............................50 6.1.3. GPIOAOUTEN..........................51 6.1.4. GPIOADS............................51 6.1.5. GPIOAPU............................52 6.1.6.
- Page 4 PAC5223 User Guide Power Application Controller 8.1.3. GPIOCOUTEN..........................69 8.1.4. GPIOCIN............................69 8.1.5. GPIOCINE............................70 8.1.6. GPIOCINTP............................. 71 8.1.7. GPIOCINTE............................. 71 8.1.8. GPIOCINTF............................72 8.1.9. GPIOCINTM............................. 72 8.2. Details of Operation..........................74 8.2.1. Block Diagram..........................74 8.2.2. Configuration............................ 74 8.2.3. GPIO C Block........................... 74 8.2.4.
- Page 5 PAC5223 User Guide Power Application Controller 10.2.2. Configuration..........................94 10.2.3. GPIO E Block..........................94 10.2.4. Input............................... 94 10.2.5. Output and Output Enable......................94 10.2.6. Output Drive Strength........................94 10.2.7. Weak Pull Up and Pull Down......................95 10.2.8. Peripheral Select..........................95 10.2.9.
- Page 6 PAC5223 User Guide Power Application Controller 12.1.32. DTGA3TED..........................109 12.2. Details of Operation..........................110 12.2.1. Block Diagram..........................110 12.2.2. Configuration..........................110 12.2.3. Timer A Block..........................110 12.2.4. Timer............................110 12.2.5. Register update..........................111 12.2.6. Timer Modes..........................111 12.2.7. Single Shot Mode......................... 111 12.2.8.
- Page 7 PAC5223 User Guide Power Application Controller 14.1.7. TCCC1CTRL..........................132 14.1.8. TCCC1CTR..........................132 14.1.9. DTGC0CTL..........................133 14.1.10. DTGC0LED..........................133 14.1.11. DTGC0TED..........................133 14.2. Details of Operation..........................134 14.2.1. Block Diagram..........................134 14.2.2. Configuration..........................134 14.2.3. Timer C Block..........................134 14.2.4. Timer............................134 14.2.5.
- Page 8 PAC5223 User Guide Power Application Controller 16.1.7. FLASHWSTATE........................... 153 16.1.8. FLASHBWRITE..........................153 16.1.9. FLASHBWDATA........................... 154 16.2. Details of Operation..........................155 16.2.1. Block Diagram..........................155 16.2.2. Configuration..........................155 16.2.3. FLASH Memory..........................155 16.2.4. Writing to FLASH Controller Registers..................155 16.2.5. FLASH Wait State........................155 16.2.6.
- Page 9 PAC5223 User Guide Power Application Controller 17.1.40. AS1R7............................175 17.2. Details of Operation..........................175 17.2.1. Block Diagram..........................175 17.3. Details of Operation..........................175 17.3.1. Basic Configuration........................175 17.3.2. ADC, Autosequencer and EMUX....................176 17.3.3. Clock Setting..........................176 17.3.4. ADC.............................. 177 17.3.5.
- Page 10 PAC5223 User Guide Power Application Controller 20. SOC Bus bridge............................200 20.1. Register..............................200 20.1.1. Register Map..........................200 20.1.2. SOCBCTL............................ 200 20.1.3. SOCBCFG........................... 200 20.1.4. SOCBCLKDIV..........................201 20.1.5. SOCBSTAT..........................201 20.1.6. SOCBCSSTR..........................202 20.1.7. SOCBD............................203 20.1.8. SOCBINT_EN..........................203 20.2. Details of Operation..........................204 20.2.1.
- Page 11 PAC5223 User Guide Power Application Controller 22.1.9. SCFG............................220 22.1.10. SCFG2............................220 23. Configurable Analog FRONT END....................... 222 23.1. Register..............................222 23.1.1. Register Map..........................222 23.1.2. SOC.CFGAIO0..........................223 23.1.3. SOC.CFGAIO1..........................223 23.1.4. SOC.CFGAIO2..........................225 23.1.5. SOC.CFGAIO3..........................225 23.1.6. SOC.CFGAIO4..........................227 23.1.7.
- Page 12 PAC5223 User Guide Power Application Controller 23.6.2. AIO6............................. 249 23.6.3. AIO6 digital I/O Mode........................250 23.6.4. AIO6 Single Ended Amplifier Mode....................250 23.6.5. AIO6 Comparator Mode....................... 250 23.6.6. AIO6 Special Mode........................251 23.6.7. AIO6 Push Button Mode....................... 251 23.7. AIO7..............................253 23.7.1.
- Page 13 PAC5223 User Guide Power Application Controller 24.5.1. Block Diagram..........................276 24.5.2. DRL1............................276 24.6. DRL2 Low Side Driver.......................... 277 24.6.1. Block Diagram..........................277 24.6.2. DRL2............................277 24.7. DRH3 High Side Driver........................278 24.7.1. Block Diagram..........................278 24.7.2. DRH3............................278 24.8. DRH4 High Side Driver........................279 24.8.1.
- Page 14 PAC5223 User Guide Power Application Controller LIST OF TABLES Table 2-1. Embedded FLASH Register Map......................26 Table 2-2. ROM Register Map..........................27 Table 2-3. System Clock Control Register Map....................28 Table 2-4. FLASH Memory Controller Register Map....................29 Table 2-5. Watchdog Timer Register Map......................29 Table 2-6.
- Page 15 PAC5223 User Guide Power Application Controller Table 21-1. SPI Register Map..........................206 Table 22-1. Multi-Mode Power Manager Register Map..................217 Table 23-1. Configurable Analog Front End Register Map.................222 Table 24-1. Application Specific Power Driver Register Map................268 Table 25-1. Summary of processor mode and stack use options...............283 Table 25-2.
- Page 16 PAC5223 User Guide Power Application Controller LIST OF REGISTERS Register 3-1. ROSC11 (ROSC11 Frequency Value, 0x0010 0010)..............39 Register 3-2. ADCGAIN (ADC Gain Value, 0x0010 0020)..................39 Register 3-3. ADCOFF (ADC Offset, 0x0010 0024).....................39 Register 3-4. FTTEMP (FT Temp value, 0x0010 0028)..................40 Register 3-5.
- Page 17 PAC5223 User Guide Power Application Controller Register 9-7. GPIODPSEL (GPIO Port D Peripheral Select, 0x4008 005C)............80 Register 9-8. GPIODINTP (GPIO Port D Interrupt Polarity, 0x4008 0060)............81 Register 9-9. GPIODINTE (GPIO Port D Interrupt Enable, 0x4008 0064)............81 Register 9-10. GPIODINTF (GPIO Port D Interrupt, 0x4008 0068)..............82 Register 9-11.
- Page 18 PAC5223 User Guide Power Application Controller Register 13-5. TBCC0CTR (Timer B PWMB0 Capture and Compare Counter, 0x400E 0044)......119 Register 13-6. TBCC1CTRL (Timer B PWMB1 Capture and Compare Control, 0x400E 0048)......119 Register 13-7. TBCC1CTR (Timer B PWMB1 Capture and Compare Counter, 0x400E 004C)......119 Register 13-8.
- Page 19 PAC5223 User Guide Power Application Controller Register 17-17. AS0S5 (Auto sequencer 0-sample 5 control 0x4015 006C)............167 Register 17-18. AS0R5 ( Auto sequencer 0-sample 5 result register 0x4015 0070)..........167 Register 17-19. AS0S6 (Auto sequencer 0-sample 6 control 0x4015 0074)............168 Register 17-20. AS0R6 ( Auto sequencer 0-sample 6 result register 0x4015 0078)..........168 Register 17-21.
- Page 20 PAC5223 User Guide Power Application Controller Register 20-7. SOCBINT_EN (SOC Bus Bridge Interrupt Enable, 0x4020 0020)..........203 Register 21-1. SPICTL (SPI Control, 0x4021 0000)................... 206 Register 21-2. SPICFG (SPI Configuration, 0x4021 0004)................207 Register 21-3. SPICLKDIV (SPI Clock Divider, 0x4021 0008)................208 Register 21-4. SPISTAT (SPI Status, 0x4021 0014)..................208 Register 21-5.
- Page 21 PAC5223 User Guide Power Application Controller LIST OF FIGURES Figure 2-1. Memory Map............................25 Figure 4-1. System Clock Control........................43 Figure 5-1. WDT..............................48 Figure 6-1. GPIO Port A............................58 Figure 7-1. GPIO Port B............................66 Figure 8-1. GPIO Port C............................74 Figure 9-1.
- Page 22 PAC5223 User Guide Power Application Controller Figure 18-2. I2C Master Read Transaction......................188 Figure 18-3. I2C Master Read Waveforms......................189 Figure 19-1. UART............................. 197 Figure 20-1. SOC Bridge............................ 204 Figure 20-2. Single Read from SOC Bridge....................... 205 Figure 20-3. Single Write to SOC Bridge......................205 Figure 21-1.
- Page 23 PAC5223 User Guide Power Application Controller Figure 25-25. SHPR2............................355 Figure 25-26. SHPR3............................355 Figure 25-27. SYST_CSR..........................357 Figure 25-28. SYST_RVR..........................357 Figure 25-29. SYST_CVR..........................358 Figure 25-30. SYST_CALIB..........................358 - 23 - Rev 18‒March 4, 2018...
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Page 24: Styles And Formatting Conventions
PAC5223 User Guide Power Application Controller 1. STYLES AND FORMATTING CONVENTIONS 1.1. Overview This chapter describes formatting and styles used through the document. 1.2. Number Representation Numbers in a base other than decimal have a prefix or postfix as indicator. All numbers use little endian formatting, most significant bit/digit is to the left. -
Page 25: Memory And Register Map
PAC5223 User Guide Power Application Controller 2. MEMORY AND REGISTER MAP 2.1. Memory Map Figure 2-1. Memory Map 0xE000 EFFF Debug Control 0xE000 ED00 0xE000 FFFF 0xFFFF FFFF ROM Table NVIC Reserved Nested Vectored Interrupt 0xE00F F000 Reserved Controller 0xE000 E100... -
Page 26: Register Map
PAC5223 User Guide Power Application Controller 2.2. Register Map Table 2-1. Embedded FLASH Register Map ADDRESS NAME DESCRIPTION Embedded FLASH 0x0000 0000 – 0x0000 03FF EFLASHP0 EFLASH page 0 0x0000 0400 – 0x0000 07FF EFLASHP1 EFLASH page 1 0x0000 0800 – 0x0000 0BFF... -
Page 27: Table 2-2. Rom Register Map
PAC5223 User Guide Power Application Controller Table 2-2. ROM Register Map ADDRESS NAME DESCRIPTION INFO ROM 0x0010 0000 – 0x0010 000F Reserved Reserved 0x0010 0010 ROSC11 ROSC frequency in Hz at 11b setting (8 MHz) 0x0010 0014 Reserved Reserved 0x0010 0018... -
Page 28: Table 2-3. System Clock Control Register Map
PAC5223 User Guide Power Application Controller Table 2-3. System Clock Control Register Map ADDRESS NAME DESCRIPTION System Clock Control 0x4000 0000 SCCTL System clock control 0x4000 0004 PLLCTL PLL control 0x4000 0008 ROSCCTL Ring oscillator control 0x4000 000C XTALCTL Crystal driver control - 28 - Rev 18‒March 4, 2018... -
Page 29: Table 2-4. Flash Memory Controller Register Map
PAC5223 User Guide Power Application Controller Table 2-4. FLASH Memory Controller Register Map ADDRESS NAME DESCRIPTION FLASH Memory Controller 0x4002 0000 FLASHLOCK FLASH lock 0x4002 0004 FLASHCTL FLASH Control 0x4002 0008 FLASHPAGE FLASH page selection 0x4002 000C Reserved Reserved 0x4002 0010... -
Page 30: Table 2-8. Gpio Port B Register Map
PAC5223 User Guide Power Application Controller ADDRESS NAME DESCRIPTION GPIO Port A 0x4007 0000 GPIOAOUT GPIO Port A output 0x4007 0004 GPIOAOUTEN GPIO Port A output enable 0x4007 0008 GPIOADS GPIO Port A output drive strength 0x4007 000C GPIOAPU GPIO Port A output weak pull up... -
Page 31: Table 2-9. Gpio Port Ab Register Map
PAC5223 User Guide Power Application Controller Table 2-9. GPIO Port AB Register Map ADDRESS NAME DESCRIPTION GPIO Port AB 0x4007 0080 GPIOABOUT GPIO Port AB output 0x4007 0084 GPIOABOUTEN GPIO Port AB output enable 0x4007 0088 GPIOABODS GPIO Port AB output drive strength... -
Page 32: Table 2-12. Gpio Port Cd Register Map
PAC5223 User Guide Power Application Controller ADDRESS NAME DESCRIPTION 0x4008 0050 GPIODPD GPIO Port D output weak pull down 0x4008 0054 GPIODIN GPIO Port D input 0x4008 0058 Reserved Reserved 0x4008 005C GPIODPSEL GPIO Port D peripheral select 0x4008 0060... -
Page 33: Table 2-14. Timer A Register Map
PAC5223 User Guide Power Application Controller ADDRESS NAME DESCRIPTION 0x4009 002C GPIOEINTM GPIO Port E interrupt mask Table 2-14. Timer A Register Map ADDRESS NAME DESCRIPTION Timer A 0x400D 0000 TACTL Timer A control 0x400D 0004 TAPRD Timer A period... -
Page 34: Table 2-15. Timer B Register Map
PAC5223 User Guide Power Application Controller Table 2-15. Timer B Register Map ADDRESS NAME DESCRIPTION Timer B 0x400E 0000 TBCTL Timer B control 0x400E 0004 TBPRD Timer B period 0x400E 0008 TBCTR Timer B counter Timer B PWMB Capture and Compare... -
Page 35: Table 2-17. Timer D Register Map
PAC5223 User Guide Power Application Controller Table 2-17. Timer D Register Map ADDRESS NAME DESCRIPTION Timer D 0x4010 0000 TDCTL Timer D control 0x4010 0004 TDPRD Timer D period 0x4010 0008 TDCTR Timer D counter Timer D PWMD Capture and Compare... -
Page 36: Table 2-21. Adc Auto-Sampling Sequencer 1 Register Map
PAC5223 User Guide Power Application Controller ADDRESS NAME DESCRIPTION 0x4015 005C AS0S3 Auto-sampling sequencer 0 sample 3 control 0x4015 0060 AS0R3 Auto-sampling sequencer 0 sample 3 result 0x4015 0064 AS0S4 Auto-sampling sequencer 0 sample 4 control 0x4015 0068 AS0R4 Auto-sampling sequencer 0 sample 4 result... -
Page 37: Table 2-23. Uart Register Map
PAC5223 User Guide Power Application Controller ADDRESS NAME DESCRIPTION 0x40B0 0034 I2CMRXDATA C master receive data 0x40B0 0038 I2CMTXDATA C master transmit data 0x40B0 0040 I2CBAUD C master baud rate 0x40B0 0070 I2CSRXDATA C slave receive data 0x40B0 0074 I2CSTXDATA... -
Page 38: Table 2-25. Spi Register Map
PAC5223 User Guide Power Application Controller Table 2-25. SPI Register Map ADDRESS NAME DESCRIPTION 0x4021 0000 SPICTL SPI control 0x4021 0004 SPICFG SPI configuration 0x4021 0008 SPICLKDIV SPI clock divider 0x4021 000C Reserved Reserved 0x4021 0010 Reserved Reserved 0x4021 0014... -
Page 39: Information Block
PAC5223 User Guide Power Application Controller 3. INFORMATION BLOCK 3.1. Register 3.1.1. Register Map Table 3-1. Information Block Register Map BYTE OFFSET ADDRESS 0x0010 0000 Reserved 0x0010 0010 ROSC11 Reserved 0x0010 0020 ADCGAIN ADCOFF FTTEMP TEMPS CLKREF 0x0010 0030 Reserved... -
Page 40: Fttemp
PAC5223 User Guide Power Application Controller 3.1.5. FTTEMP Register 3-4. FTTEMP (FT Temp value, 0x0010 0028) NAME ACCESS DESCRIPTION 15:0 FTTEMP Test temperature for internal temp sensor in °C 3.1.6. TEMPS Register 3-5. TEMPS (Temperature Sensor reading, 0x0010 002A) NAME... -
Page 41: System Clock Control
PAC5223 User Guide Power Application Controller 4. SYSTEM CLOCK CONTROL 4.1. Register 4.1.1. Register Map Table 4-1. System Clock Control Register Map ADDRESS NAME DESCRIPTION RESET VALUE System Clock Control 0x4000 0000 CCSCTL System clock control 0x0000 0000 0x4000 0004... -
Page 42: Pllctl
PAC5223 User Guide Power Application Controller 4.1.3. PLLCTL Register 4-2. PLLCTL (PLL Control, 0x4000 0004) NAME ACCESS RESET DESCRIPTION 31:24 Reserved Reserved 23:20 Reserved Reserved, must be set to 0x0 PLL output divider 1111b: / 15 19:16 PLLOUTDIV 0001b: / 1... -
Page 43: Details Of Operation
PAC5223 User Guide Power Application Controller 4.2. Details of Operation 4.2.1. Block Diagram Figure 4-1. System Clock Control FRCLK CLOCK ADC/ASC GATING FCLK CLOCKSOURCES SYSTICK XTAL HCLK XTALCTL.XTALEN XOUT GPIOD.PD1 FRCLK CLKREF SRAM DIVIDER CLOCK GATING SCCTL.HCLKDIV ROSC FLASH DIVIDER ROSCCTL.ROSCP... -
Page 44: Rosc
PAC5223 User Guide Power Application Controller • UART • Timer A, B, C, D • 4.2.3. ROSC The internal ring oscillator has four frequency settings controllable with OSCCTL.ROSCP from 8.3MHz to 28.7MHz in four steps. The ROSC can also be disabled using OSCCTL.ROSCEN. -
Page 45: Frclk
PAC5223 User Guide Power Application Controller Table 4-5. PLL output frequency settings using 4MHz ROSC as input PLL output PLLOUTDIV PLLFBDIV PLLINDIV 0x01 (/[1*2]) 0x008 (*10) 0x0 (/2) 10MHz 0x05 (/[5*2]) 0x052 (*84) 0x0 (/2) 16.8MHz 0x01 (/[1*2]) 0x012 (*20) -
Page 46: Watchdog Timer
PAC5223 User Guide Power Application Controller 5. WATCHDOG TIMER 5.1. Register 5.1.1. Register Map Table 5-1. Watchdog Timer Register Map ADDRESS NAME DESCRIPTION RESET VALUE Watchdog Timer 0x4003 0000 WDTCTL Watchdog timer control 0x6300 0000 0x4003 0004 WDTCDV Watchdog timer count-down value... -
Page 47: Wdtcdv
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Watchdog interrupt enable WDTINTEN 1b = enable WDT interrupt 0b = disable WDT interrupt WDTCTR counter reset WDTCTRRST 101b = write of 101b reset WDTCTR to WDTCDV value 5.1.3. WDTCDV Register 5-2. -
Page 48: Details Of Operation
PAC5223 User Guide Power Application Controller 5.2. Details of Operation 5.2.1. Block Diagram Figure 5-1. WDT Watchdog Timer WDTCTL.CLKSEL WDTCTL.WDTCLKDIV FRCLK WDTCTL FCLK WDTCTR WDCTL.KEY WDTCDV INTERRUPT WDCTL.RESETEN WDCTL.CTRRST NVIC WDTCTL.WDINT WDTCTL.WDINTEN RESET 5.2.2. Configuration Following blocks need to be configured for correct use of the WDT: Clock Control System (CCS) •... -
Page 49: Watchdog Timer Mode
PAC5223 User Guide Power Application Controller automatic reloads WDTCTR.CTR with WDTCDV.RSTVALUE and continues countdown. The WDT is stopped when WDTCTL.INTEN is cleared. 5.2.7. Watchdog Timer Mode Set WDTCTL.WDTRESETEN to 1b to use the WDT as 24-bit watchdog timer with device reset capability. Set WDTCTL.WDTINTEN to 1b to enable interrupt when WDT counts to 0x0. -
Page 50: Gpio Port A
PAC5223 User Guide Power Application Controller 6. GPIO PORT A 6.1. Register 6.1.1. Register Map Table 6-1. GPIO Port A Register Map ADDRESS NAME DESCRIPTION RESET VALUE GPIO Port A 0x4007 0000 GPIOAOUT GPIO Port A output 0x0000 0000 0x4007 0004... -
Page 51: Gpioaouten
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port A output 1 1b: set output high if GPIOAOE.P1 = 1b 0b: set output low if GPIOAOE.P1 = 1b Port A output 0 1b: set output high if GPIOAOE.P0 = 1b 0b: set output low if GPIOAOE.P0 = 1b... -
Page 52: Gpioapu
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port A output 5 drive strength select 1b: high 0b: low Port A output 4 drive strength select 1b: high 0b: low Port A output 3 drive strength select 1b: high... -
Page 53: Gpioapd
PAC5223 User Guide Power Application Controller 6.1.6. GPIOAPD Register 6-5. GPIOAPD (GPIO Port A Weak Pull Down, 0x4007 0010) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Port A 7 weak pull down select 1b: enable weak pull-down to VSS 0b: disable weak pull-down to VSS... -
Page 54: Gpioapsel
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port A 2 input state 1b: input high 0b: input low Port A 1 input state 1b: input high 0b: input low Port A 0 input state 1b: input high 0b: input low 6.1.8. -
Page 55: Gpioaintp
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port A 1 peripheral select 11b: reserved 10b: reserved 01b: PWMA1 / DTGA1LS output or CA1 capture and compare input / IBCTL1 00b: I/O mode PA1 Port A 0 peripheral select... -
Page 56: Gpioaintf
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port A 6 interrupt enable 1b: enabled interrupt 0b: disable interrupt Port A 5 interrupt enable 1b: enabled interrupt 0b: disable interrupt Port A 4 interrupt enable 1b: enabled interrupt... -
Page 57: Gpioaintm
PAC5223 User Guide Power Application Controller 6.1.12. GPIOAINTM Register 6-11. GPIOAINTM (GPIO Port A Interrupt Mask, 0x4007 002C) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Port A 7 interrupt mask 1b: enable interrupt mask 0b: disable interrupt mask Port A 6 interrupt mask... -
Page 58: Details Of Operation
PAC5223 User Guide Power Application Controller 6.2. Details of Operation 6.2.1. Block Diagram Figure 6-1. GPIO Port A PA 0..7, x = 0..7 INTERRUPT GPIOAINT.PAxINT GPIOAINTEN.PAxINTEN INPUT GPIOAINTP.PAxINTP GPIOAORUP.PAxRUP NVIC GPIOAI.PAxI GPIOAINTM.PAxINTM CCIO D-PERAx1 D-PERAx2 D-PERAx3 GPIOAPSEL.PAxSEL PORTA I/O GPIOADS.PAxDS GPIOAOE.PAxOE... -
Page 59: Output Drive Strength
PAC5223 User Guide Power Application Controller 6.2.6. Output Drive Strength The output drive strength can be adjusted using GPIOADS to meet application needs. Set GPIOADS.Px to enable high current drive strength, reset to enable low current drive strength. 6.2.7. Weak Pull Up and Pull Down Independent from the output settings, weak pull up can be enabled with GPIOAPU and weak pull down can be enabled with GPIOAPD. -
Page 60: Gpio Port B
PAC5223 User Guide Power Application Controller 7. GPIO PORT B 7.1. Register 7.1.1. Register Map Table 7-1. GPIO Port B Register Map ADDRESS NAME DESCRIPTION RESET VALUE GPIO Port B 0x4007 0040 GPIOBOUT GPIO Port B output 0x0000 0000 0x4007 0044... -
Page 61: Gpiobds
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Reserved, must be written to 0b Reserved, must be written to 0b Reserved, must be written to 0b Reserved, must be written to 0b Reserved, must be written to 0b... -
Page 62: Gpiobpd
PAC5223 User Guide Power Application Controller 7.1.6. GPIOBPD Register 7-5. GPIOBPD (GPIO Port B Weak Pull Down, 0x4007 0050) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Reserved, must be written to 0b Reserved, must be written to 0b Reserved, must be written to 0b... -
Page 63: Gpiobintp
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port B 6 peripheral select 11b: reserved 13:12 10b: reserved 01b: EMUXDATA 00b: reserved Port B 5 peripheral select 11b: reserved 11:10 10b: reserved 01b: EMUXCLK 00b: reserved Port B 4 peripheral select... -
Page 64: Gpiobinte
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port B 0 interrupt polarity select 1b: Rising edge, low to high transition 0b: Falling edge, high to low transition 7.1.10. GPIOBINTE Register 7-9. GPIOBINTE (GPIO Port B Interrupt Enable, 0x4007 0064) -
Page 65: Gpiobintm
PAC5223 User Guide Power Application Controller 7.1.12. GPIOBINTM Register 7-11. GPIOBINTM (GPIO Port B Interrupt Mask, 0x4007 006C) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Port B 7 interrupt mask 1b: enable interrupt mask 0b: disable interrupt mask Reserved, must be written to 0b... -
Page 66: Details Of Operation
PAC5223 User Guide Power Application Controller 7.2. Details of Operation 7.2.1. Block Diagram Figure 7-1. GPIO Port B PB 0..7, x = 0..7 INTERRUPT GPIOBINT.PBxINT GPIOBINTEN.PBxINTEN INPUT GPIOBINTP.PBxINTP GPIOBORUP.PBxRUP NVIC GPIOBI.PBxI GPIOBINTM.PBxINTM CCIO D-PERBx1 D-PERBx2 D-PERBx3 GPIOBPSEL.PBxSEL PORTB I/O GPIOBDS.PBxDS GPIOBOE.PBxOE... -
Page 67: Weak Pull Up And Pull Down
PAC5223 User Guide Power Application Controller 7.2.7. Weak Pull Up and Pull Down Independent from the output settings, weak pull up can be enabled with GPIOBPU and weak pull down can be enabled with GPIOBPD. NOTE: GPIOBPU.Pxor GPIOBPD.Px should never be enabled at the same time for a single GPIO. If switching from weak pull-up to weak pull-down is required, disable weak pull-up first before enablle weak pull-down and vice versa. -
Page 68: Gpio Port C
PAC5223 User Guide Power Application Controller 8. GPIO PORT C 8.1. Register 8.1.1. Register Map Table 8-1. GPIO Port C Register Map ADDRESS NAME DESCRIPTION RESET VALUE GPIO Port C 0x4008 0000 GPIOCOUT GPIO Port C output 0x0000 0000 0x4008 0004... -
Page 69: Gpiocouten
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port C output 1 1b: set output high if GPIOCOUTEN. Px = 1b 0b: set output low if GPIOCOUTEN. Px = 1b Port C output 0 1b: set output high if GPIOCOUTEN. Px = 1b 0b: set output low if GPIOCOUTEN. -
Page 70: Gpiocine
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port C 5 input state 1b: input high 0b: input low Port C 4 input state 1b: input high 0b: input low Port C 3 input state 1b: input high... -
Page 71: Gpiocintp
PAC5223 User Guide Power Application Controller 8.1.6. GPIOCINTP Register 8-5. GPIOCINTP (GPIO Port C Interrupt Polarity, 0x4008 0020) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Port C 7 interrupt polarity select 1b: Rising edge, low to high transition 0b: Falling edge, high to low transition... -
Page 72: Gpiocintf
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port C 1 interrupt enable 1b: enabled interrupt 0b: disable interrupt Port C 0 interrupt enable 1b: enabled interrupt 0b: disable interrupt 8.1.8. GPIOCINTF Register 8-7. GPIOCINTF (GPIO Port C Interrupt, 0x4008 0028) - Page 73 PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port C 5 interrupt mask 1b: enable interrupt mask 0b: disable interrupt mask Port C 4 interrupt mask 1b: enable interrupt mask 0b: disable interrupt mask Port C 3 interrupt mask...
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Page 74: Details Of Operation
PAC5223 User Guide Power Application Controller 8.2. Details of Operation 8.2.1. Block Diagram Figure 8-1. GPIO Port C PC 0..7, x = 0..7 INTERRUPT GPIOCINT.PCxINT GPIOCINTEN.PCxINTEN INPUT GPIOCINTP.PCxINTP NVIC GPIOCI.PCxI GPIOCINTM.PCxINTM GPIOCDS.PCxIE PORTC I/O GPIOCOE.PCxOE OUTPUT GPIOCO.PCxO 8.2.2. Configuration Following blocks need to be configured for correct use of the GPIO C: Nested Vectored Interrupt Controller (NVIC) •... - Page 75 PAC5223 User Guide Power Application Controller When the GPIO interrupts are enabled for the first time after device start-up, it may be in an uncertain state and generate an interrupt. To avoid this the GPIOCINTM mask bit need to be set before enabled interrupt bits.
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Page 76: Gpio Port D
PAC5223 User Guide Power Application Controller 9. GPIO PORT D 9.1. Register 9.1.1. Register Map Table 9-1. GPIO Port D Register Map ADDRESS NAME DESCRIPTION RESET VALUE GPIO Port D 0x4008 0040 GPIODOUT GPIO Port D output 0x0000 0000 0x4008 0044... -
Page 77: Gpiodouten
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port D output 1 1b: set output high if GPIODOUTEN.Px = 1b 0b: set output low if GPIODOUTEN.Px = 1b Port D output 0 1b: set output high if GPIODOUTEN.Px = 1b 0b: set output low if GPIODOUTEN.Px = 1b... -
Page 78: Gpiodpu
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port D output 5 drive strength select 1b: high 0b: low Port D output 4 drive strength select 1b: high 0b: low Port D output 3 drive strength select 1b: high... -
Page 79: Gpiodpd
PAC5223 User Guide Power Application Controller 9.1.6. GPIODPD Register 9-5. GPIODPD (GPIO Port D Weak Pull Down, 0x4008 0050) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Port D 7 weak pull down select 1b: enable weak pull-down to VSS 0b: disable weak pull-down to VSS... -
Page 80: Gpiodpsel
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port D 1 input state 1b: input high 0b: input low Port D 0 input state 1b: input high 0b: input low 9.1.8. GPIODPSEL Register 9-7. GPIODPSEL (GPIO Port D Peripheral Select, 0x4008 005C) -
Page 81: Gpiodintp
PAC5223 User Guide Power Application Controller 9.1.9. GPIODINTP Register 9-8. GPIODINTP (GPIO Port D Interrupt Polarity, 0x4008 0060) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Port D 7 interrupt polarity select 1b: Rising edge, low to high transition 0b: Falling edge, high to low transition... -
Page 82: Gpiodintf
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port D 1 interrupt enable 1b: enabled interrupt 0b: disable interrupt Port D 0 interrupt enable 1b: enabled interrupt 0b: disable interrupt 9.1.11. GPIODINTF Register 9-10. GPIODINTF (GPIO Port D Interrupt, 0x4008 0068) - Page 83 PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port D 5 interrupt mask 1b: enable interrupt mask 0b: disable interrupt mask Port D 4 interrupt mask 1b: enable interrupt mask 0b: disable interrupt mask Port D 3 interrupt mask...
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Page 84: Details Of Operation
PAC5223 User Guide Power Application Controller 9.2. Details of Operation 9.2.1. Block Diagram Figure 9-1. GPIO Port D PD 0..7, x = 0..7 INTERRUPT GPIODINT.PDxINT GPIODINTEN.PDxINTEN INPUT GPIODINTP.PDxINTP GPIODORUP.PDxRUP NVIC GPIODI.PDxI GPIODINTM.PDxINTM CCIO D-PERDx1 D-PERDx2 D-PERDx3 GPIODPSEL.PDxSEL PORTD I/O GPIODDS.PDxDS GPIODOE.PDxOE... -
Page 85: Output Drive Strength
PAC5223 User Guide Power Application Controller When GPIODOE.PDxOE is disabled, the output is in High-Z state. 9.2.6. Output Drive Strength The output drive strength can be adjusted using GPIODDS to meet application needs. Set GPIODDS.Px to enable high current drive strength, reset to enable low current drive strength. -
Page 86: Gpio Port E
PAC5223 User Guide Power Application Controller 10. GPIO PORT E 10.1. Register 10.1.1. Register Map Table 10-1. GPIO Port E Register Map ADDRESS NAME DESCRIPTION RESET VALUE GPIO Port E 0x4009 0000 GPIOEOUT GPIO Port E output 0x0000 0000 0x4009 0004... -
Page 87: Gpioeouten
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port E output 1 1b: set output high if GPIOEOUTEN.Px = 1b 0b: set output low if GPIOEOUTEN.Px = 1b Port E output 0 1b: set output high if GPIOEOUTEN.Px = 1b 0b: set output low if GPIOEOUTEN.Px = 1b... -
Page 88: Gpioepu
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port E output 5 drive strength select 1b: high 0b: low Port E output 4 drive strength select 1b: high 0b: low Port E output 3 drive strength select 1b: high... -
Page 89: Gpioepd
PAC5223 User Guide Power Application Controller 10.1.6. GPIOEPD Register 10-5. GPIOEPD (GPIO Port E Weak Pull Down, 0x4009 0010) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Port E 7 weak pull down select 1b: enable weak pull-down to VSS 0b: disable weak pull-down to VSS... -
Page 90: Gpioepsel
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port E 1 input state 1b: input high 0b: input low Port E 0 input state 1b: input high 0b: input low 10.1.8. GPIOEPSEL Register 10-7. GPIOEPSEL (GPIO Port E Peripheral Select, 0x4009 001C) -
Page 91: Gpioeintp
PAC5223 User Guide Power Application Controller 10.1.9. GPIOEINTP Register 10-8. GPIOEINTP (GPIO Port E Interrupt Polarity, 0x4009 0020) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Port E 7 interrupt polarity select 1b: Rising edge, low to high transition 0b: Falling edge, high to low transition... -
Page 92: Gpioeintf
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port E 1 interrupt enable 1b: enabled interrupt 0b: disable interrupt Port E 0 interrupt enable 1b: enabled interrupt 0b: disable interrupt 10.1.11. GPIOEINTF Register 10-10. GPIOEINTF (GPIO Port E Interrupt Flag, 0x4009 0028) - Page 93 PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Port E 5 interrupt mask 1b: enable interrupt mask 0b: disable interrupt mask Port E 4 interrupt mask 1b: enable interrupt mask 0b: disable interrupt mask Port E 3 interrupt mask...
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Page 94: Details Of Operation
PAC5223 User Guide Power Application Controller 10.2. Details of Operation 10.2.1. Block Diagram Figure 10-1. GPIO Port E PE 0..7, x = 0..7 INTERRUPT GPIOEINT.PExINT GPIOEINTEN.PExINTEN INPUT GPIOEINTP.PExINTP GPIOEORUP.PExRUP NVIC GPIOEI.PExI GPIOEINTM.PExINTM CCIO D-PEREx1 D-PEREx2 D-PEREx3 GPIOEPSEL.PExSEL A-PEREx3 GPIOEDS.PExDS GPIOEOE.PExOE... -
Page 95: Weak Pull Up And Pull Down
PAC5223 User Guide Power Application Controller 10.2.7. Weak Pull Up and Pull Down Independent from the output settings, weak pull up can be enabled with GPIOEPU and weak pull down can be enabled with GPIOPD. NOTE: GPIOEPU.Pxor GPIOEPD.Px should never be enabled at the same time for a single GPIO. If switching from weak pull-up to weak pull-down is required, disable weak pull-up first before enablle weak pull-down and vice versa. -
Page 96: General Purpose Timer
PAC5223 User Guide Power Application Controller 11. GENERAL PURPOSE TIMER 11.1. Register 11.1.1. Register Map Table 11-1. General Purpose Timer Register Map ADDRESS NAME DESCRIPTION RESET VALUE Real Time Clock 0x4004 0000 RTCCTL Real-time clock timer control 0x6300 0000 0x4004 0004... -
Page 97: Rtccdv
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION GPTCTR counter reset GPTCTRRST 101b = write of 101b reset GPTCTR to GPTCDV value 11.1.3. RTCCDV Register 11-2. RTCCDV (Real Time Clock Count-Down Value, 0x4004 0004) NAME ACCESS RESET DESCRIPTION... -
Page 98: Details Of Operation
PAC5223 User Guide Power Application Controller 11.2. Details of Operation 11.2.1. Block Diagram Figure 11-1. GPT General Purpose Timer GPTCTL.CLKSEL GPTCTL.GPTCLKDIV FRCLK GPTCTL GPTCTR WDCTL.KEY GPTCDV INTERRUPT WDCTL.RESETEN WDCTL.CTRRST NVIC GPTCTL.WDINT GPTCTL.WDINTEN 11.2.2. Configuration Following blocks need to be configured for correct use of the GPT: Clock Control System (CCS) •... -
Page 99: Timer A
PAC5223 User Guide Power Application Controller 12. TIMER A 12.1. Register 12.1.1. Register Map Table 12-1. Timer A Register Map ADDRESS NAME DESCRIPTION RESET VALUE Timer A 0x400D 0000 TACTL Timer A control 0x0000 0000 0x400D 0004 TAPRD Timer A period... -
Page 100: Tactl
PAC5223 User Guide Power Application Controller ADDRESS NAME DESCRIPTION RESET VALUE 0x400D 00D8 DTGA3TED Timer A dead time generator 3 trailing edge delay 0x0000 0000 12.1.2. TACTL Register 12-1. TACTL (Timer A Control, 0x400D 0000) NAME ACCESS RESET DESCRIPTION 31:14... -
Page 101: Taprd
PAC5223 User Guide Power Application Controller 12.1.3. TAPRD Register 12-2. TAPRD (Timer A Period, 0x400D 0004) NAME ACCESS RESET DESCRIPTION 31:16 Reserved Reserved 15:0 PERIOD Timer A period value 12.1.4. TACTR Register 12-3. TACTR (Timer A Counter, 0x400D 0008) NAME... -
Page 102: Tacc1Ctrl
PAC5223 User Guide Power Application Controller 12.1.7. TACC1CTRL Register 12-6. TACC1CTRL (Timer A PWMA1 Capture and Compare Control, 0x400D 0048) NAME ACCESS RESET DESCRIPTION 31:5 Reserved Reserved Capture and compare mode CCMODE 1b: Capture mode PWMA1 input 0b: Compare mode PWMA1 output... -
Page 103: Tacc2Ctr
PAC5223 User Guide Power Application Controller 12.1.10. TACC2CTR Register 12-9. TACC2CTR (Timer A PWMA2 Capture and Compare Counter, 0x400D 0054) NAME ACCESS RESET DESCRIPTION 31:16 Reserved Reserved Counter value for PWMA2 compare mode or counter value for PWMA2 15:0 CCCTR capture mode 12.1.11. -
Page 104: Tacc4Ctr
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Capture and compare interrupt CCINT 1b: interrupt, clear by write 1b 0b: no interrupt detected Capture mode edge detect PWMA4 11b: reserved CCEDG 10b: high to low transition and low to high transition... -
Page 105: Tacc6Ctrl
PAC5223 User Guide Power Application Controller 12.1.17. TACC6CTRL Register 12-16. TACC6CTRL (Timer A PWMA6 Capture and Compare Control, 0x400D 0070) NAME ACCESS RESET DESCRIPTION 31:5 Reserved Reserved Capture and compare mode CCMODE 1b: Capture mode PWMA6 input 0b: Compare mode PWMA6 output... -
Page 106: Tacc7Ctr
PAC5223 User Guide Power Application Controller 12.1.20. TACC7CTR Register 12-19. TACC7CTR (Timer A PWMA7 Capture and Compare Counter, 0x400D 007C) NAME ACCESS RESET DESCRIPTION 31:16 Reserved Reserved Counter value for PWMA7 compare mode or counter value for PWMA7 15:0 CCCTR capture mode 12.1.21. -
Page 107: Dtga1Ctl
PAC5223 User Guide Power Application Controller 12.1.24. DTGA1CTL Register 12-23. DTGA1CTL (Timer A Dead Time Generator 1 Control, 0x400D 00B0) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Bypass dead time generator 1b: DTGA1 bypass active, DTGA1LS = PWMA1, DTGA1HS = PWMA5... -
Page 108: Dtga2Led
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION One Time Preservation 1b: DTGA2HS high time is same as PWMA6 hightime and is shifted by DTGA2LED 0b: DTGA2HS high time is reduced by DTGA2LED Invert DTGA2HS output signal INVHS... -
Page 109: Dtga3Led
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Reserved Reserved 12.1.31. DTGA3LED Register 12-30. DTGA3LED (Timer A Dead Time Generator 3 Leading Edge Delay, 0x400D 00D4) NAME ACCESS RESET DESCRIPTION 31:12 Reserved Reserved Counter value DTGA3 leading edge dead time in clock cycles defined by 11:0 TACTL.DTGCLK... -
Page 110: Details Of Operation
PAC5223 User Guide Power Application Controller 12.2. Details of Operation 12.2.1. Block Diagram Figure 12-1. Timer A TIMER A Dead time Generator A 0..3, x=0..3 TACTL.DTGCLK PWMA[x+4] DTGAxHS I/O Controller DTGACLK TACTL.CLKDIV EDGE DELAY HCLK DTGAxLED DTGAxCTL.INVHS TIMERA TACTR DTGAxLS... -
Page 111: Register Update
PAC5223 User Guide Power Application Controller while the timer is running, the new TAPRD value will be latched when the counter reaches old TAPRD value in up mode. In up/down mode there is the option to latch the new TAPRD value when counter counts back to zero. -
Page 112: Pwm/Compare Units
PAC5223 User Guide Power Application Controller timer counter is also cleared anytime the TxCTL.CLR bit is set to a 1. When the TxCTL.SYNC bit is set and the SYNC_IN signal is de-asserted and the timer mode is either up or up/down, then the timer will start counting. -
Page 113: Timer And Pwm/Capture Interrupt
PAC5223 User Guide Power Application Controller Figure 12-2. PWMA[x] and PWMA[x+4] Example Using Timer A Up Mode and Up/Down Mode TAPRD TAPRD TAPRD TACTR PWMA[x] TACC[x]CTR TACC[x]CTR TACC[x]CTR PWMA[x+4] TACC[x+4]CTR TACC[x+4]CTR TACC[x+4]CTR TAPRD TAPRD TAPRD TACTR PWMA[x] TACC[x]CTR TACC[x]CTR TACC[x]CTR... -
Page 114: Dead-Time Generator
PAC5223 User Guide Power Application Controller 12.2.12. Dead-Time Generator The dead-time generator can be configured to introduce dead-time for a complementary PWM output. The Timer A block supports up to 4 dead time generators. 12.2.12.1. Dead Time Input Clock Selection The clock source for the DTGAx can be selected using TACTL.DTGCLK. -
Page 115: Figure 12-5. Dtgax Bypass And Inverting Ls Example
PAC5223 User Guide Power Application Controller Figure 12-5. DTGAx Bypass and Inverting LS Example PWMA[x+4] onPWMA[x+4] PWMAx onPWMAx DTGAxHS onPWMA[x+4] DTGAxLS onPWMAx 12.2.12.5. Dead Time Insertion Set DTGAxCTL.BYPASS to 0 to enable dead time insertion. In dead time insertion mode only PWM[x+4] signal is used to generate DTGAxHS and DTGAxLS. -
Page 116: Pwm Output And Capture Input Pin Selection
PAC5223 User Guide Power Application Controller Figure 12-7. DTGAx LED and TED with On Time Preservation Example DTGAxLED DTGAxLED DTGAxTED PWMA[x+4] onPWMA[x+4] PWMAx DTGAxHS onPWMA[x+4] DTGAxLS 12.2.13. PWM Output and Capture Input Pin Selection Each of the DTGAxHS, DTGAxLS outputs, and CAx inputs can be routed to different I/Os, allowing great flexibility in pin assignments. -
Page 117: Timer B
PAC5223 User Guide Power Application Controller 13. TIMER B 13.1. Register 13.1.1. Register Map Table 13-1. Timer B Register Map ADDRESS NAME DESCRIPTION RESET VALUE Timer B 0x400E 0000 TBCTL Timer B control 0x0000 0000 0x400E 0004 TBPRD Timer B period... -
Page 118: Tbprd
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Timer B input clock divider 111b: / 128 110b: / 64 101b: /32 CLKDIV 100b: /16 011b: /8 010b: /4 001b: /2 000b: /1 Timer B interrupt enable INTEN 1b: enable Timer B interrupt... -
Page 119: Tbcc0Ctr
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Capture and compare mode CCMODE 1b: Capture mode PWMB0 input 0b: Compare mode PWMB0 output Capture and compare interrupt enable CCINTEN 1b: enable interrupt 0b: disable interrupt Capture and compare interrupt... -
Page 120: Tbcc2Ctrl
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Counter value for PWMB1 compare mode or counter value for PWMB1 15:0 CCCTR capture mode 13.1.9. TBCC2CTRL Register 13-8. TBCC2CTRL (Timer B PWMB2 Capture and Compare Control, 0x400E 0050) NAME... -
Page 121: Tbcc3Ctr
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Capture mode edge detect PWMB3 11b: reserved CCEDG 10b: high to low transition and low to high transition 01b: low to high transition only 00b: high to low transition only 13.1.12. -
Page 122: Dtgb0Ted
PAC5223 User Guide Power Application Controller 13.1.15. DTGB0TED Register 13-14. DTGB0TED (Timer B Dead Time Generator 0 Trailing Edge Delay, 0x400E 00A8) NAME ACCESS RESET DESCRIPTION 31:12 Reserved Reserved Counter value DTGB0 trailing edge dead time in clock cycles defined by 11:0 TBCTL.DTGCLK... -
Page 123: Details Of Operation
PAC5223 User Guide Power Application Controller 13.2. Details of Operation 13.2.1. Block Diagram Figure 13-1. Timer B TIMER B Dead time Generator B 0 TBCTL.DTGCLK PWMB1 DTGB0HS DTGBCLK I/O Controller TBCTL.CLKDIV EDGE DELAY HCLK DTGB0LED DTGB0CTL.INVHS TIMERB TBCTR DTGB0LS DTGB0TED... -
Page 124: Register Update
PAC5223 User Guide Power Application Controller TBCTL.PRDL configures when the timer will be updated with the new TBPRD value in up/down mode. The current timer value is accessible with the timer B counter value register TBCTR. 13.2.5. Register update The TBPRD, TBCCxCTR register can be written to while the timer is running, the new TBPRD, TBCCxCTR value will be latched when the counter reaches old TBPRD value in up mode. -
Page 125: Pwm/Compare Units
PAC5223 User Guide Power Application Controller Each timer C, or D that need to be synchronized as slave with master timer B need to set the TxCTL.SYNC bit. If this is bit is not set, then the sync_in signal is ignored and the timer operates independently. -
Page 126: Timer And Pwm/Capture Interrupt
PAC5223 User Guide Power Application Controller Figure 13-2. PWMB0 and PWMB1 Example Using Timer B Up Mode and Up/Down Mode TBPRD TBPRD TBPRD TBCTR PWMB0 TBCC0CTR TBCC0CTR TBCC0CTR PWMB1 TBCC1CTR TBCC1CTR TBCC1CTR TBPRD TBPRD TBPRD TBCTR PWMB0 TBCC0CTR TBCC0CTR TBCC0CTR... -
Page 127: Dead-Time Generator
PAC5223 User Guide Power Application Controller 13.2.12. Dead-Time Generator The dead-time generator can be configured to introduce dead-time for a complementary PWM output. The Timer B block supports up to 1 dead time generator. 13.2.12.1. Dead Time Input Clock Selection The clock source for the DTGB0 can be selected using TBCTL.DTGCLK. -
Page 128: Figure 13-5. Dtgb0 Bypass And Inverting Ls Example
PAC5223 User Guide Power Application Controller Figure 13-5. DTGB0 Bypass and Inverting LS Example PWMB1 onPWMB1 PWMB0 onPWMB0 DTGB0HS onPWMB1 DTGB0LS onPWMB0 13.2.12.5. Dead Time Insertion Set DTGB0CTL.BYPASS to 0 to enable dead time insertion. In dead time insertion mode only PWMB1 signal is used to generate DTGB0HS and DTGB0LS. -
Page 129: Pwm Output And Capture Input Pin Selection
PAC5223 User Guide Power Application Controller Figure 13-7. DTGB0 LED and TED with On Time Preservation Example DTGB0LED DTGB0LED DTGB0TED PWMB1 onPWMB1 PWMB0 DTGB0HS onPWMB1 DTGB0LS 13.2.13. PWM Output and Capture Input Pin Selection Each of the DTGB0HS, DTGB0LS outputs, and CBx inputs can be routed to different I/Os, allowing great flexibility in pin assignments. -
Page 130: Timer C
PAC5223 User Guide Power Application Controller 14. TIMER C 14.1. Register 14.1.1. Register Map Table 14-1. Timer C Register Map ADDRESS NAME DESCRIPTION RESET VALUE Timer C 0x400F 0000 TCCTL Timer C control 0x0000 0000 0x400F 0004 TCPRD Timer C period... -
Page 131: Tcprd
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Timer C input clock divider 111b: /128 110b: /64 101b: /32 CLKDIV 100b: /16 011b: /8 010b: /4 001b: /2 000b: /1 Timer C interrupt enable INTEN 1b: enable Timer C interrupt... -
Page 132: Tccc0Ctr
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Capture and compare mode CCMODE 1b: Capture mode PWMC0 input 0b: Compare mode PWMC0 output Capture and compare interrupt enable CCINTEN 1b: enable interrupt 0b: disable interrupt Capture and compare interrupt... -
Page 133: Dtgc0Ctl
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Counter value for PWMC1 compare mode or counter value for PWMC1 15:0 CCCTR capture mode 14.1.9. DTGC0CTL Register 14-8. DTGC0CTL (Timer C Dead Time Generator 0 Control, 0x400F 00A0) NAME... -
Page 134: Figure 14-1. Timer C
PAC5223 User Guide Power Application Controller 14.2. Details of Operation 14.2.1. Block Diagram Figure 14-1. Timer C TIMER C Dead time Generator C 0 TCCTL.DTGCLK PWMC1 DTGC0HS DTGCCLK I/O Controller TCCTL.CLKDIV EDGE DELAY HCLK DTGC0LED DTGC0CTL.INVHS TIMERC TCCTR DTGC0LS DTGC0TED... -
Page 135: Register Update
PAC5223 User Guide Power Application Controller TCCTL.PRDL configures when the timer will be updated with the new TCPRD value in up/down mode. The current timer value is accessible with the timer C counter value register TCCTR. 14.2.5. Register update The TCPRD, TCCCxCTR register can be written to while the timer is running, the new TCPRD, TCCCxCTR value will be latched when the counter reaches old TCPRD value in up mode. -
Page 136: Pwm/Compare Units
PAC5223 User Guide Power Application Controller If timer D that need to be synchronized as slave with master timer C need to set the TxCTL.SYNC bit. If this is bit is not set, then the sync_in signal is ignored and the timer operates independently. -
Page 137: Figure 14-2. Pwmc0 And Pwmc1 Example Using Timer C Up Mode And Up/Down Mode
PAC5223 User Guide Power Application Controller Figure 14-2. PWMC0 and PWMC1 Example Using Timer C Up Mode and Up/Down Mode TCPRD TCPRD TCPRD TCCTR PWMC0 TCCC0CTR TCCC0CTR TCCC0CTR PWMC1 TCCC1CTR TCCC1CTR TCCC1CTR TCPRD TCPRD TCPRD TCCTR PWMC0 TCCC0CTR TCCC0CTR TCCC0CTR... -
Page 138: Figure 14-4. Dtgc0 Bypass Example
PAC5223 User Guide Power Application Controller 14.2.12. Dead-Time Generator The dead-time generator can be configured to introduce dead-time for a complementary PWM output. The Timer C block supports up to 1 dead time generator. 14.2.12.1. Dead Time Input Clock Selection The clock source for the DTGC0 can be selected using TCCTL.DTGCLK. -
Page 139: Figure 14-5. Dtgc0 Bypass And Inverting Ls Example
PAC5223 User Guide Power Application Controller Figure 14-5. DTGC0 Bypass and Inverting LS Example PWMC1 onPWMC1 PWMC0 onPWMC0 DTGC0HS onPWMC1 DTGC0LS onPWMC0 14.2.12.5. Dead Time Insertion Set DTGC0CTL.BYPASS to 0 to enable dead time insertion. In dead time insertion mode only PWMC1 signal is used to generate DTGC0HS and DTGC0LS. -
Page 140: Table 14-2. Timer C Signal To Pin Mapping
PAC5223 User Guide Power Application Controller Figure 14-7. DTGC0 LED and TED with On Time Preservation Example DTGC0LED DTGC0LED DTGC0TED PWMC1 onPWMC1 PWMC0 DTGC0HS onPWMC1 DTGC0LS 14.2.13. PWM Output and Capture Input Pin Selection Each of the DTGC0HS, DTGC0LS outputs, and CCx inputs can be routed to different I/Os, allowing great flexibility in pin assignments. -
Page 141: Table 15-1. Timer D Register Map
PAC5223 User Guide Power Application Controller 15. TIMER D 15.1. Register 15.1.1. Register Map Table 15-1. Timer D Register Map ADDRESS NAME DESCRIPTION RESET VALUE Timer D 0x4010 0000 TDCTL Timer D control 0x0000 0000 0x4010 0004 TDPRD Timer D period... -
Page 142: Tdprd
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Timer D input clock divider 111b: / 128 110b: / 64 101b: /32 CLKDIV 100b: /16 011b: /8 010b: /4 001b: /2 000b: /1 Timer D interrupt enable INTEN 1b: enable Timer D interrupt... -
Page 143: Tdcc0Ctr
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Capture and compare mode CCMODE 1b: Capture mode PWMD0 input 0b: Compare mode PWMD0 output Capture and compare interrupt enable CCINTEN 1b: enable interrupt 0b: disable interrupt Capture and compare interrupt... -
Page 144: Dtgd0Ctl
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Counter value for PWMD1 compare mode or counter value for PWMD1 15:0 CCCTR capture mode 15.1.9. DTGD0CTL Register 15-8. DTGD0CTL (Timer D Dead Time Generator 0 Control, 0x4010 00A0) NAME... -
Page 145: Figure 15-1. Timer D
PAC5223 User Guide Power Application Controller 15.2. Details of Operation 15.2.1. Block Diagram Figure 15-1. Timer D TIMER D Dead time Generator D 0 TDCTL.DTGDLK PWMD1 DTGD0HS DTGDCLK I/O Controller TDCTL.CLKDIV EDGE DELAY HCLK DTGD0LED DTGD0CTL.INVHS TIMERD TDCTR DTGD0LS DTGD0TED... -
Page 146: Register Update
PAC5223 User Guide Power Application Controller 15.2.5. Register Update The TDPRD, TDCCxCTR register can be written to while the timer is running, the new TDPRD, TDCCxCTR value will be latched when the counter reaches old TDPRD value in up mode. In up/down mode there is the option to latch the new TDPRD, TDCCxCTR values when counter counts back to zero. -
Page 147: Figure 15-2. Pwmd0 And Pwmd1 Example Using Timer D Up Mode And Up/Down Mode
PAC5223 User Guide Power Application Controller To enable synchronized timers, the following steps should be followed: 1. The slave timer B, C, D is configured with the selected timer input clock, timer pre-scaler, timer period and set the TxCTL.SYNC bit. The timer should still be set to disabled at this point. -
Page 148: Figure 15-3. Cd0 And Cd1 Capture Example
PAC5223 User Guide Power Application Controller 15.2.10.2. Capture Mode The Capture mode is enabled with setting TDCCxCTRL.CCMODE to 1. The trip condition for capture mode can be configured using TDCCxCTRL.CCEDGE, high-to-low signal edge transition, low-to-high signal edge transition or both. -
Page 149: Figure 15-4. Dtgd0 Bypass Example
PAC5223 User Guide Power Application Controller 15.2.12.3. Bypass Mode Set DTGD0CTL.BYPASS to 0 to enable dead time insertion. Set DTGD0CTL.BYPASS to 1 to enable bypass mode, no dead time is inserted, PWMD1 is routed to DTGD0HS and PWMD0 is routed to DTGD0LS. -
Page 150: Table 15-2. Timer D Signal To Pin Mapping
PAC5223 User Guide Power Application Controller Figure 15-6. DTGD0 LED and TED Example DTGD0LED DTGD0TED PWMD1 onPWMD1 PWMD0 DTGD0HS - LED onPWMD1 DTGD0LS 15.2.12.6. Dead Time Insertion with On Time Preservation Set DTGD0CTL.OTP to 1 to enable on time preservation. In this mode the DTGD0HS is same as PWMD1 on time. -
Page 151: Table 16-1. Flash Memory Controller Register Map
PAC5223 User Guide Power Application Controller 16. FLASH MEMORY CONTROLLER 16.1. Register 16.1.1. Register Map Table 16-1. FLASH Memory Controller Register Map ADDRESS NAME DESCRIPTION RESET VALUE FLASH Memory Controller 0x4002 0000 FLASHLOCK FLASH lock 0x0000 0000 0x4002 0004 FLASHCTL... -
Page 152: Flashctl
PAC5223 User Guide Power Application Controller 16.1.3. FLASHCTL Register 16-2. FLASHCTL (FLASH Control and Status, 0x4002 0004) NAME ACCESS RESET DESCRIPTION 31:5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Page erase active PERASE 1b: page erase in progress 0b: page erase finished or no page erase in progress... -
Page 153: Flashperase
PAC5223 User Guide Power Application Controller 16.1.5. FLASHPERASE Register 16-4. FLASHPERASE (FLASH Page Erase, 0x4002 0014) NAME ACCESS RESET DESCRIPTION Write of correct key value to this register starts FLASH page erase selected in 31:0 PERASE FLASHPAGE.PAGE 0xA5A5 5A5A: start FLASH page erase selected by FLASHPAGE.PAGE 16.1.6. -
Page 154: Flashbwdata
PAC5223 User Guide Power Application Controller 16.1.9. FLASHBWDATA Register 16-8. FLASHBWDATA (Buffered FLASH Write Data, 0x4002 0030) NAME ACCESS RESET DESCRIPTION Reserved Reserved, must be set to 0x0 Reserved Reserved, must be set to 0x0 FLASH page selector to write to... -
Page 155: Figure 16-1. Flash Memory Controller
PAC5223 User Guide Power Application Controller 16.2. Details of Operation 16.2.1. Block Diagram Figure 16-1. FLASH Memory Controller FLASH Memory Controller WaitState Memory FLASHWSTATE Buffered Write FLASH FLASHBWRITE Memory FLASHBWDATA FLASH ERASE FLASHPERASE FLASHPAGE STATUS SWDACCESS FLASHSTATUS 16.2.2. Configuration Following blocks need to be configured for correct use of the FLASH: Clock Control System (CCS) •... -
Page 156: Flash Page Erase
PAC5223 User Guide Power Application Controller 16.2.6. FLASH Page Erase To erase a page of FLASH memory, set FLASHLOCK to 0xAAAA AAAA first, then set FLASHBWDATA.PAGE to the page to be erased and then set FLASHPERASE to 0xA5A5 5A5A. The FLASH page operation will start, FLASHCTL.PERASE is set to 1b and any access to FLASH memory address space is stalled until erase... -
Page 157: Swd Debug Access Disable
PAC5223 User Guide Power Application Controller Memoryaddress: Word memory address pagesize: FLASH page size: 0x400 Example: memoryaddress: 0x0000 0438 PAGE = 0x0000 0438 / 0x400 = 0x01 ADDRESS = (0x0000 0438 – 0x01*0x400)/0x2 = 0x38/0x2 = 0x1C It is not recommended to write to FLASH while executing from FLASH as any access to FLASH is stalled until the erase operation is finished. -
Page 158: Table 17-1. Register Map - Emux
PAC5223 User Guide Power Application Controller 17. ADC AND AUTO SEQUENCER 17.1. Register 17.1.1. Register Map Table 17-1. Register Map – EMUX ADRESS NAME DESCRIPTON RESET VALUE EMUX 0x4015 0000 EMUXCTL ADC external MUX control register 0x0000 0000 0x4015 0004... -
Page 159: Table 17-4. Register Map - Adc Auto Sequencer 1
PAC5223 User Guide Power Application Controller Table 17-4. Register Map – ADC Auto Sequencer 1 ADRESS NAME DESCRIPTON RESET VALUE ADC Auto Sequencer -1 0x4015 0100 AS1CTL Automated ADC sampling 1 control register 0x0000 0000 0x4015 0104 AS1S0 Automated Sampling 1 Sequence 0 register... -
Page 160: Emuxdata
PAC5223 User Guide Power Application Controller 17.1.3. EMUXDATA Register 17-2. EMUXDATA (EMUX data register 0x4015 0004) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved DATA EMUX data, writing this register will start transmission over EMUX - 160 - Rev 18‒March 4, 2018... -
Page 161: Adcctl
PAC5223 User Guide Power Application Controller 17.1.4. ADCCTL Register 17-3. ADCCTL (ADC control register 0x4015 0008) NAME ACCESS RESET DESCRIPTION 31:16 Reserved Reserved ADC module enable ADCEN 1b: enable ADC module 0b: turn off ADC module Start ADC conversion. A write of 1b will start ADC conversion if ADCCTL.ADCBUSY = 0b and ADCCTL.ADCMODE = 00b. -
Page 162: Adcint
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION ADCRESULT ADC conversion result 17.1.6. ADCINT Register 17-5. ADCINT (ADC Interrupt register 0x4015 0010) NAME ACCESS RESET DESCRIPTION 31:13 Reserved Reserved Last Auto sequencer to run 11b: reserved 19:18 ASCINTTR... -
Page 163: As0Ctl
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION ADC conversion finished interrupt 1b: interrupt, clear by writing 1b to it ADCINT 0b: no interrupt NOTE: This bit is cleared by writing a 1b to it. 17.1.7. AS0CTL Register 17-6. AS0CTL (Auto Sequencer 0 control register 0x4015 0040) -
Page 164: As0S0
PAC5223 User Guide Power Application Controller 17.1.8. AS0S0 Register 17-7. AS0S0 (Auto sequencer 0-sample 0 control 0x4015 0044) NAME ACCESS RESET DESCRIPTION 31:15 Reserved Reserved ADC MUX input select 111b: VSSA 110b: reserved 101b: AD5 14:12 ADCMUX 100b: AD4 011b: AD3... -
Page 165: As0R1
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION EMUX transmission start 11b: reserved EMUXS 10b: send AS0S1.EMUXD data after S/H of ADC 01b: send AS0S1.EMUXD data at beginning of this sample sequence 00b: do not send AS0S1.EMUXD data... -
Page 166: As0S3
PAC5223 User Guide Power Application Controller 17.1.14. AS0S3 Register 17-13. AS0S3 (Auto sequencer 0-sample 3 control 0x4015 005C) NAME ACCESS RESET DESCRIPTION 31:15 Reserved Reserved ADC MUX input select 111b: VSSA 110b: reserved 101b: AD5 14:12 ADCMUX 100b: AD4 011b: AD3... -
Page 167: As0R4
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION EMUX transmission start 11b: reserved EMUXS 10b: send AS0S4.EMUXD data after S/H of ADC 01b: send AS0S4.EMUXD data at beginning of this sample sequence 00b: do not send AS0S4.EMUXD data... -
Page 168: As0S6
PAC5223 User Guide Power Application Controller 17.1.20. AS0S6 Register 17-19. AS0S6 (Auto sequencer 0-sample 6 control 0x4015 0074) NAME ACCESS RESET DESCRIPTION 31:15 Reserved Reserved ADC MUX input select 111b: VSSA 110b: reserved 101b: AD5 14:12 ADCMUX 100b: AD4 011b: AD3... -
Page 169: As0R7
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION EMUX transmission start 11b: reserved EMUXS 10b: send AS0S7.EMUXD data after S/H of ADC 01b: send AS0S7.EMUXD data at beginning of this sample sequence 00b: do not send AS0S7.EMUXD data... -
Page 170: As1S0
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Auto sequencer 1 PWM trigger source 1111b: reserved 1110b: reserved 1101b: PWMD1 1100b: PWMD0 1011b: PWMC1 1010b: PWMC0 1001b: PWMB1 AS1TRPWM 1000b: PWMB0 0111b: PWMA7 0110b: PWMA6 0101b: PWMA5 0100b: PWMA4... -
Page 171: As1S1
PAC5223 User Guide Power Application Controller 17.1.27. AS1S1 Register 17-26. AS1S1 (Auto sequencer 1-sample 1 control 0x4015 010C) NAME ACCESS RESET DESCRIPTION 31:15 Reserved Reserved ADC MUX input select 111b: VSSA 110b: reserved 101b: AD5 14:12 ADCMUX 100b: AD4 011b: AD3... -
Page 172: As1R2
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION EMUX transmission start 11b: reserved EMUXS 10b: send AS1S2.EMUXD data after S/H of ADC 01b: send AS1S2.EMUXD data at beginning of this sample sequence 00b: do not send AS1S2.EMUXD data... -
Page 173: As1S4
PAC5223 User Guide Power Application Controller 17.1.33. AS1S4 Register 17-32. AS1S4 (Auto sequencer 1-sample 4 control 0x4015 0124) NAME ACCESS RESET DESCRIPTION 31:15 Reserved Reserved ADC MUX input select 111b: VSSA 110b: reserved 101b: AD5 14:12 ADCMUX 100b: AD4 011b: AD3... -
Page 174: As1R5
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION EMUX transmission start 11b: reserved EMUXS 10b: send AS1S5.EMUXD data after S/H of ADC 01b: send AS1S5.EMUXD data at beginning of this sample sequence 00b: do not send AS1S5.EMUXD data... -
Page 175: As1S7
PAC5223 User Guide Power Application Controller 17.1.39. AS1S7 Register 17-38. AS1S7 (Auto sequencer 1-sample 7 control 0x4015 013C) NAME ACCESS RESET DESCRIPTION 31:15 Reserved Reserved ADC MUX input select 111b: VSSA 110b: reserved 101b: AD5 14:12 ADCMUX 100b: AD4 011b: AD3... -
Page 176: Figure 17-1. Adc, Emux, Asc0, Asc1
PAC5223 User Guide Power Application Controller Figure 17-1. ADC, EMUX, ASC0, ASC1 GPIOC ADC Result 10-BIT ADCCR.ADCRESULT ADC CTL INTERRUPT ADCCTL.ADCMUX ADCCTL.ADCCDIV ADCCTL.ADCSTART ADCINT.ASCINTTR ADCINT.ASCINTSEQ ADCLK FCLK ADCCTL.ADCREPEAT ADCINT.ASCINTEN ADCINT.ASCINT NVIC ADCCTL.ADCMODE ADCINT.AS0INTEN ADCINT.AS0INT ADCCTL.ADCBUSY ADCINT.AS1INTEN ADCINT.AS1INT EMUX ADCCTL.ADCDONE ADCINT.EMUXINTEN ADCINT.EMUXINT... -
Page 177: Figure 17-2. Adc Conversion (Single Shot)
PAC5223 User Guide Power Application Controller 17.3.4. ADC The ADC, ASC0, ASC1 and EMXUX block is enabled with ADCCTL.ADCEN. In manual conversion mode set ADCCTL.ADCMODE to 0b. Set the ADx channel with ADCCTL.ADCMUX. For single conversion, set ADCCTL.REPEAT to 0b, for repeated conversion set ADCCTL.REPEAT to 1b. To start a conversion set ADCCTL.ADCSTART to 1b. -
Page 178: Figure 17-4. Ascx, Adcctl.adcmode = 001B, 010B, 100B, 101B
PAC5223 User Guide Power Application Controller offload the CPU from high speed, low latency sampling. Each sequencer can be programmed to take up to 8 consecutive ADC samples from different analog inputs. 17.3.6.1. Auto Sequencer Modes The AC0, ASC1 support 8 different modes, configurable with ADCCTL.ADCMODE. -
Page 179: Figure 17-6. Ascx, Adcctl.adcmode = 111B
PAC5223 User Guide Power Application Controller Figure 17-6. ASCx, ADCCTL.ADCMODE = 111b ASC0 Trigger ASC0 AS0S1 AS0S2 AS0S3 AS0S4 AS0S5 AS0S6 AS0S7 AS0S0 ASC1 Trigger ASC1 AS1S1 AS1S2 AS1S3 AS1S4 AS1S5 AS1S6 AS1S7 AS1S0 17.3.6.2. Sequencer trigger Each sequencer ASC0 and ASC1 can use 2 different trigger modes, manual mode or automated mode. -
Page 180: Figure 17-8. Asxsy Sample With Asxsy.emuxs = 01B And Asxsy.delay = 11B
PAC5223 User Guide Power Application Controller Figure 17-8. ASxSy Sample with ASxSy.EMUXS = 01b and ASxSy.DELAY = 11b 15 16 ADCCLK ADC S/H EMUX DELAY ASxRy ADCCTL.ADCBUSY ADCINT.ADCINT EMUXCLOCK EMUXDATA ADCCTL.ADCMUX Figure 17-9. ASxSy Sample with ASxSy.EMUXS = 10b and ASxSy.DELAY = 11b... -
Page 181: Figure 17-11. Ascx 8 Samples, Collision
PAC5223 User Guide Power Application Controller Figure 17-11. ASCx 8 samples, Collision ASCx Trigger ASCx ADCINT.ASCINT ADCINT.ASCINTR ADCINT.ASCINTSEQ In ADCCTL.ADCMODE = 111b, the ASC0 and ASC1 sequencer are triggered independently but are accessing the same ADC. In case of both ASC0 and ASC1 are triggered at the same time, ASC0 has always higher priority and will be executed while ASC1 is skipped and ignored. -
Page 182: Table 18-1 . I2C Register Map
PAC5223 User Guide Power Application Controller 18. I 18.1. Register 18.1.1. Register Map Table 18-1. I C Register Map ADDRESS NAME DESCRIPTION RESET VALUE 0x401B 0000 I2CCFG C configuration 0x0000 0000 0x401B 0004 I2CSTATUS C interrupt and status 0x0000 0000... - Page 183 PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Slave Transfer SLXFERDONEIN 1b = Slave transfer complete, clears on read 0b = Slave transfer not done 23:19 Reserved Reserved Slave receive data register SLRXDATA full SLRXFINT 1b: SLRXDATA received data from I2C bus, clears on read...
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Page 184: I2Cie
PAC5223 User Guide Power Application Controller 18.1.4. I2CIE Register 18-3. I2CIE (I C Interrupt Enable, 0x401B 0008) NAME ACCESS RESET DESCRIPTION 31:25 Reserved Reserved SLXFERDONE Interrupt enable SLXFERDONEIN 1b: interrupt enable 0b: interrupt disabled 23:19 Reserved Reserved SLRXF Interrupt enable... -
Page 185: I2Cmrxdata
PAC5223 User Guide Power Application Controller 18.1.6. I2CMRXDATA Register 18-5. I2CMRXDATA (I C Master Receive Data, 0x401B 0034) NAME ACCESS RESET DESCRIPTION 31:9 Reserved Reserved I2CMARXDATA full I2CMARXDATAF 1b: I2CMARXDATA register full, clear by read 0b: I2CMARXDATA register empty MARXDATA Master Data Byte received 18.1.7. -
Page 186: I2Csltxdata
PAC5223 User Guide Power Application Controller 18.1.10. I2CSLTXDATA Register 18-9. I2CSLTXDATA (I C Slave Transmit Data, 0x401B 0074) NAME ACCESS RESET DESCRIPTION 31:9 Reserved Reserved I2CSLTXDATA full I2CSLTXDATAF 1b: I2CSLTXDATA register full, data not transmitted 0b: I2CSLTXDATA register empty Slave ACK or NACK... -
Page 187: Figure 18-1. I2C
PAC5223 User Guide Power Application Controller 18.2. Details of Operation 18.2.1. Block Diagram Figure 18-1. I2C I2C Master I2CMATXDATA I2CMARXDATA I2C Clock I2CMACTL HCLK I/O Controller I2CBAUD.SCLH I2CBAUD.SCLL I2C Slave I2CSLTXDATA I2CSLRXDATA I2CSLADDR INTERRUPT NVIC I2C STATUS I2C Control I2CINT... -
Page 188: Figure 18-2. I2C Master Read Transaction
PAC5223 User Guide Power Application Controller I2C Mode SCLK Frequency HLCK I2CBAUD.SCLH I2CBAUD.SCLL Normal 100kHz 50MHz 0xFA 0xFA Normal 100kHz 4MHz 0x14 0x14 Normal 100kHz 2.8MHz 0x0E 0x0E Fast 400kHz 50MHz 0x3E 0x3E Fast 400kHz 4MHz 0x3E 0x3E Fast 400kHz 3.2MHz... -
Page 189: Figure 18-3. I2C Master Read Waveforms
PAC5223 User Guide Power Application Controller The Master will send the first byte with the slave address and the Read command. The slave will ACK. Immediately after this first ACK, the master will request the first data byte. When the first data byte is transferred into the Master, the Master will ACK and generate two interrupts: one for Master Transmit Data Register Empty and then one for Master Receive Data Register Full. - Page 190 PAC5223 User Guide Power Application Controller 1. First Data Byte I2CSTATUS.MATXE interrupt, I2CMTXDATA.LBYTE = 0 2. First Data Byte I2CSTATUS.MRXF interrupt, read the I2CMTXDATA register 3. Second Data Byte I2CSTATUS.MATXE interrupt, I2CMTXDATA.LBYTE = 1 (as byte #3 will be NACK’d) 4.
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Page 191: Table 19-1. Uart Register Map
PAC5223 User Guide Power Application Controller 19. UART 19.1. Register 19.1.1. Register Map Table 19-1. UART Register Map ADDRESS NAME DESCRIPTION RESET VALUE UART 0x401D 0000 UARTRXTX UART receive/transmit FIFO 0x0000 0000 0x401D 0004 UARTIER UART interrupt enable 0x0000 0000... -
Page 192: Uartier/Uartdl_H
PAC5223 User Guide Power Application Controller 19.1.3. UARTIER/UARTDL_H Register 19-2. UARTIER (UART Interrupt Enable, 0x401D 0004) NAME ACCESS RESET DESCRIPTION 31:4 Reserved Reserved Modem Status interrupt enable MSINTEN 1b: enable interrupt 0b: disable interrupt Receive interrupt enable RSINTEN 1b: enable interrupt... -
Page 193: Uartlcr
PAC5223 User Guide Power Application Controller 19.1.5. UARTLCR Register 19-4. UARTLCR (UART Line Control, 0x401D 000C) NAME ACCESS RESET DESCRIPTION 31:8 Reserved Reserved Divisor Latch Access DLAB 1b: Allow access to the divistor latch 0b: Allow access to the FIFOs and IER... -
Page 194: Uartsp
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION TX FIFO Empty TCFE 1b:TX FIFO are empty 0b: not empty RX Break RXBE 1b: entry on top of RX FIFO has break error, bit clears on read 0b: error cleared... -
Page 195: Uartier2
PAC5223 User Guide Power Application Controller 19.1.10. UARTIER2 Register 19-9. UARTIER2 (UART Interrupt Enable, 0x401D 0024) NAME ACCESS RESET DESCRIPTION 31:4 Reserved Reserved Modem Status interrupt enable MSINTEN 1b: enable interrupt 0b: disable interrupt Receive interrupt enable RSINTEN 1b: enable interrupt... - Page 196 PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION 31:4 Reserved Reserved RX FIFO full RXFF 1b: RX FIFO full 0b: RX FIFO not full RX FIFO empty RXFE 1b: RX FIFO empty 0b: RX FIFO not empty TX FIFO full...
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Page 197: Figure 19-1. Uart
PAC5223 User Guide Power Application Controller 19.2. Details of Operation 19.2.1. Block Diagram Figure 19-1. UART UART TX FIFO Fractional DIV 16 deep HCLK RX/16 UARTDL_L.DL_L I/O Controller UARTRXTX UARTFD_L.FRAC RX FIFO 16 Deep UART STATUS UART CTL INTERRUPT NVIC UARTCTL.SP... - Page 198 PAC5223 User Guide Power Application Controller BAUDRATE: desired Baud rate The integer portion of UARTDivisor is used to set UARTDL_H, UARTDL_L. To calculate the value of UARTFD_F, use formula below and round to the nearest integer. UARTFD=UARTDivisor ∗256 frac Where:...
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Page 199: Data Settings
PAC5223 User Guide Power Application Controller Baud Desired Absolute BAUD BAUD rate frac UARTDL_H UARTDL_L UARTFD_F Rate Divisor rate error error % 10416.667 10416 0x28 0xB0 0xAB 0.000010 0.0000% 5208.333 5208 0x14 0x58 0x55 -0.000038 0.0000% 3472.222 3472 0x0D 0x90 0x39 -0.000058... -
Page 200: Table 20-1. Soc Bus Bridge Register Map
PAC5223 User Guide Power Application Controller 20. SOC BUS BRIDGE 20.1. Register 20.1.1. Register Map Table 20-1. SOC Bus Bridge Register Map ADDRESS NAME DESCRIPTION RESET VALUE SOC Bus Bridge 0x4020 0000 SOCBCTL SOC Bus Bridge control 0x0000 0000 0x4020 0004... -
Page 201: Socbclkdiv
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Reserved Reserved, be set to 0x0 Reserved Reserved, be set to 0x1 Reserved Reserved, be set to 0x1 Reserved Reserved, be set to 0x0 Reserved Reserved, be set to 0x0... -
Page 202: Socbcsstr
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Write Buffer Underflow: set on the start of a second outgoing transfer if data hasn’t been written to the SOCBD after the previous transfer 1b: Write Underflow detected, clear by writing 1b to it... -
Page 203: Socbd
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION 31:12 Reserved Reserved, must be set to 0x0 CSSETUP Chip Select Setup CSHOLD Chip Select Hold CSWAIT Chip Select Wait CKWAIT SOC Bus Bridge Clock Wait Reserved Reserved, must be set to 0x0 20.1.7. -
Page 204: Figure 20-1. Soc Bridge
PAC5223 User Guide Power Application Controller 20.2. Details of Operation 20.2.1. Block Diagram Figure 20-1. SOC Bridge SOC Bridge HLCK Chip Select SOCBCTL.MTRARM SOCBCS0 SOCBCLK Analog SOCBCLKDIV DATA I/O Controller SPIMISO Peripheral SPIMOSI SPID INTERRUPT NVIC SPISTAT SPIINT_EN SPICTL SPICTL.SIE SPICFG 20.2.2. -
Page 205: Figure 20-2. Single Read From Soc Bridge
PAC5223 User Guide Power Application Controller 20.2.5. Enable and Setup of SOC Bridge 20.2.6. SOC Interrupt The SOC bridge engine interrupt is enabled with SOCBCTL.SIE. Then any sub interrupts are enabled in SINT_EN. 20.2.7. SOC Bridge Protocol The SOC bridge protocol is a 2 byte protocol, the first byte is the address packet including a 7-bit address [7:1] and a write bit [0], the second packet is an 8bit data packet. -
Page 206: Table 21-1. Spi Register Map
PAC5223 User Guide Power Application Controller 21. SPI 21.1. Register 21.1.1. Register Map Table 21-1. SPI Register Map ADDRESS NAME DESCRIPTION RESET VALUE 0x4021 0000 SPICTL SPI control 0x0000 0000 0x4021 0004 SPICFG SPI configuration 0x0000 0200 0x4021 0008 SPICLKDIV... -
Page 207: Spicfg
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Internal loop back Mode 1b: Tie the serial out source to the serial in line (internal signaling, does not LPBK traverse the chip IO bi-di buffers). 0b = Normal operation. -
Page 208: Spiclkdiv
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Module reset. 1b: Force soft reset of module. The internal state machines are reset; MRST Status register is cleared; However, the soft reset doesn’t affect control register values. 0b: do not hold the module in reset. - Page 209 PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Write Buffer Underflow Set on the start of a second outgoing transfer if data hasn’t been written to the SD register after the previous transfer 1b: Write Underflow detected, clear by writing 1b to it...
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Page 210: Spicsstr
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION SPI Interrupt Logical OR of each raw status bit WRUFL, RDOFL, and CYC_DONE, qualified with its corresponding INT_EN enable. 1b: interrupt 0b: no interrupt SPI_INT NOTE: that if the corresponding INT_EN of those status bits is reset to ‘0’, those status bits themselves will still assert upon meeting the condition, but will not contribute to the assertion of SPI_INT. -
Page 211: Spid
PAC5223 User Guide Power Application Controller 21.1.7. SPID Register 21-6. SPID (SPI Data, 0x4021 001C) NAME ACCESS RESET DESCRIPTION SOC bus bridge data 31:0 DATA On READ: retrieve received data word from the incoming holding buffer. On WRITE: write a data word to the outgoing holding buffer. -
Page 212: Details Of Operation
PAC5223 User Guide Power Application Controller 21.2. Details of Operation 21.2.1. Block Diagram Figure 21-1. SPI SPICLKDIV Chip Select HLCK SCLK SPICSSTR SPICS2 SPICTL.MTRANS SPICS1 SPICTL.MTRARM SPICS0 I/O Controller CLK /PHASE SPIMISO Loopback SPCFG.TXDATPH SPIMOSI SPCFG.RCVCPH SPICTL.LPBK SPCFG.RCVCP SPCFG.CPH SPCFG.CP SPICTL.MTURBO... -
Page 213: Figure 21-2. Spi Clock Polarity And Phase
PAC5223 User Guide Power Application Controller Where: SCLK: SCLK in Hz HCLK: HLCK in Hz SPICLKDIV: SPICLKDIV setting 21.2.5. Master Slave Mode The master mode is selected with SPICTL.SE= 0b. In master mode a write to SPID will initiate SPI data transfer. -
Page 214: Figure 21-3. Spimosi Early Transmit In Master Mode
PAC5223 User Guide Power Application Controller Figure 21-3. SPIMOSI early transmit in master mode SPICFG.(RCV)CP = 0b SPICLK SPICFG.(RCP)CP = 1b SPICLK SPICSSTR.CSL = 0b SPICSx SPICSSTR.CSL = 1b SPICSx SPIMOSI SPICFG.(RCV)CPH = 1b SPIMISO Cycle SPIMOSI SPICFG.(RCV)CPH = 0b... -
Page 215: Figure 21-5. Spicsx
PAC5223 User Guide Power Application Controller 21.2.9. Chip Select Settings The SPI engine supports up to 3 chip select signals SPICS0, SPICS1 and SPICS2, selectable with SPICSSTR.CSNUM. The CS polarity can be set with SPICSSTR.CSL, 0b for active low, 1b for active high. -
Page 216: Spi Interrupt
PAC5223 User Guide Power Application Controller and SPICLK, SPIMOSI, SPCSx can be still observed on pins. 21.2.12. SPI Interrupt The SPI engine interrupt is enabled with SPICTL.SIE. Then any sub interrupts are enabled in SPIINT_EN. 21.2.13. SPI Enable The SPI engine is enabled with SPICTL.SSEN. To soft reset the state machine and clear all status bits use SPICFG.MRST. -
Page 217: Table 22-1. Multi-Mode Power Manager Register Map
PAC5223 User Guide Power Application Controller 22. MULTI-MODE POWER MANAGER 22.1. Register 22.1.1. Register Map Table 22-1. Multi-Mode Power Manager Register Map ADDRESS NAME DESCRIPTION RESET VALUE Multi-Mode Power Manager 0x00 SYSSTAT System status 0x00 0x08 DEVID Device identification 0x09... -
Page 218: Devid
PAC5223 User Guide Power Application Controller 22.1.3. DEVID Register 22-2. DEVID (Device Identification, 0x08) NAME ACCESS RESET DESCRIPTION DEVID Device identification 22.1.4. VERID Register 22-3. VERID (Version Identification, 0x09) NAME ACCESS RESET DESCRIPTION VERID Version identification 22.1.5. PWRCTL Register 22-4. PWRCTL (Power Manager Control, 0x10) -
Page 219: Pwrstat
PAC5223 User Guide Power Application Controller 22.1.6. PWRSTAT Register 22-5. PWRSTAT (Power Manager Status, 0x11h, Persistent In Hibernate Mode) NAME ACCESS RESET DESCRIPTION Hardware reset status. When not masked, bit is set on Hardware Reset and HWRSTAT cleared when written to 1b. -
Page 220: Imod
PAC5223 User Guide Power Application Controller 22.1.8. IMOD Register 22-7. IMOD (Current Modulation, 0x13) NAME ACCESS RESET DESCRIPTION Current modulation. 0xFF (default) = 100%. Inductor current is clamped to ILMAX • (IMOD<7:0> - 0x20) / FFh. Power factor control can be achieved by... - Page 221 PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION VP voltage setting when DC/DC is enabled 00b: 5V/13.8V Varies 01b: 9V 10b: 12V 11b: 15V DC/DC enable configuration SMPSOFF 0b: DC/DC enabled 1b: DC/DC disabled Reserved Reserved, write as 0...
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Page 222: Table 23-1. Configurable Analog Front End Register Map
PAC5223 User Guide Power Application Controller 23. CONFIGURABLE ANALOG FRONT END 23.1. Register 23.1.1. Register Map Table 23-1. Configurable Analog Front End Register Map SOC ADDRESS NAME DESCRIPTION RESET VALUE Configurable Analog Front End 0x20 SOC.CFGAIO0 AIO0 Configuration 0x00 0x21 SOC.CFGAIO1... -
Page 223: Soc.cfgaio0
PAC5223 User Guide Power Application Controller 23.1.2. SOC.CFGAIO0 Register 23-1. SOC.SOC.CFGAIO0 (AIO0 Configuration, SOC 0x20) NAME ACCESS RESET IO MODE DIFFAMP MODE MODE AIO0 Option: Differential amplifier gain setting: 11b: Reserved 111b: 48x OPT0 10b: Open-drain output 110b: 32x 01b: Reserved... - Page 224 PAC5223 User Guide Power Application Controller NAME ACCESS RESET IO MODE DIFFAMP MODE If CFGAIO1.OPT1 = 00b, AIO1 Input Differential Amplifier Offset: polarity setting. If CFGAIO1.OPT1 = 10b, AIO1 Output polarity setting: 1b: Offset enabled, input signal shifted by POL1...
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Page 225: Soc.cfgaio2
PAC5223 User Guide Power Application Controller 23.1.4. SOC.CFGAIO2 Register 23-3. SOC.SOC.CFGAIO2 (AIO2 Configuration, SOC 0x22) NAME ACCESS RESET IO MODE DIFFAMP MODE MODE2 AIO2 IO Option: Differential amplifier gain setting: OPT2 11b: Reserved 111b: 48x 10b: Open-drain output 110b: 32x... - Page 226 PAC5223 User Guide Power Application Controller NAME ACCESS RESET IO MODE DIFFAMP MODE If CFGAIO3.OPT3 = 00b, Reserved Differential Amplifier Offset Calibration: If CFGAIO3.OPT3 = 10b, Output 1b: enabled polarity, set AIO3 state according to 0b: disabled MUX3: HP32 comparator setting:...
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Page 227: Soc.cfgaio4
PAC5223 User Guide Power Application Controller 23.1.6. SOC.CFGAIO4 Register 23-5. SOC.SOC.CFGAIO4 (AIO4 Configuration, SOC 0x24) NAME ACCESS RESET IO MODE DIFFAMP MODE MODE4 OPT4 AIO4 IO Option: Differential amplifier gain setting: 11b: Reserved 111b: 48x 10b: Open-drain output 110b: 32x... - Page 228 PAC5223 User Guide Power Application Controller NAME ACCESS RESET IO MODE DIFFAMP MODE If CFGAIO5.OPT5 = 00b, AIO5 Input Differential Amplifier Offset: polarity setting. If CFGAIO5.OPT5 = 10b, AIO5 Output polarity setting: 1b: Offset enabled, input signal shifted by POL5...
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Page 229: Soc.cfgaio6
PAC5223 User Guide Power Application Controller 23.1.8. SOC.CFGAIO6 Register 23-7. SOC.CFGAIO6 (AIO6 Configuration, SOC 0x26) IO MODE GAIN MODE COMPARATOR MODE SPECIAL MODE MODE6 MODE6 MODE6 MODE6 OPT6 GAIN6 OPT6 ADMUX AIO6 IO Option setting: AIO6 Comparator Reference select: ADMUX ADC output MUX:... -
Page 230: Soc.cfgaio7
PAC5223 User Guide Power Application Controller 23.1.9. SOC.CFGAIO7 Register 23-8. SOC.CFGAIO7 (AIO7 Configuration, SOC 0x27) IO MODE GAIN MODE COMPARATOR MODE SPECIAL MODE MODE7 MODE7 MODE7 MODE7 OPT7 GAIN7 OPT7 OPT7 AIO7 IO Setting: Amplifier gain setting: Select reference for AIO7, AIO8, AIO9:... -
Page 231: Soc.cfgaio8
PAC5223 User Guide Power Application Controller 23.1.10. SOC.CFGAIO8 Register 23-9. SOC.CFGAIO8 (AIO8 Configuration, SOC 0x28) IO MODE GAIN MODE COMPARATOR MODE SPECIAL MODE MODE8 MODE8 MODE8 MODE8 OPT8 GAIN8 OPT8 OPT8[1] S/H Bypass for POS: AIO8 IO Setting: Amplifier gain setting:... -
Page 232: Soc.cfgaio9
PAC5223 User Guide Power Application Controller 23.1.11. SOC.CFGAIO9 Register 23-10. SOC.CFGAIO9 (AIO9 Configuration, SOC 0x29) IO MODE GAIN MODE COMPARATOR MODE SPECIAL MODE MODE9 MODE9 MODE9 MODE9 OPT9 GAIN9 OPT9 OPT9 Amplifier gain setting: AIO9 Comparator Reference select: AIO789 comparator output to POS:... -
Page 233: Soc.sigset
PAC5223 User Guide Power Application Controller 23.1.12. SOC.SIGSET Register 23-11. SOC.SIGSET (Signal Manager Configuration, SOC 0x2A) NAME ACCESS RESET DESCRIPTION AIO9 Comparator Hysteresis AIO9HYS 1b: Comparator Hysteresis enabled 0b: Comparator Hysteresis disabled AIO8 Comparator Hysteresis AIO8HYS 1b: Comparator Hysteresis enabled... -
Page 234: Soc.adcscan
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION LPDAC[1:0] LPDAC Setting bit 1 to bit 0 23.1.16. SOC.ADCSCAN Register 23-15. SOC.ADCSCAN (ADCSCAN Configuration, SOC 0x2E) NAME ACCESS RESET DESCRIPTION Reserved Reserved, write to 0x0 ADC Scan Control Enable... -
Page 235: Soc.protstat
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Reserved Reserved, write to 0x0 HPROT54 Interrupt enable HP54INTEN 1b: enable 0b: disabled HPROT32 Interrupt enable HP32INTEN 1b: enable 0b: disabled HPROT10 Interrupt enable HP10INTEN 1b: enable 0b: disabled Reserved... -
Page 236: Soc.doutsig1
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION AIO5 digital out AIO5DOUT 1b: Output High Z 0b: Output VSSA AIO4 digital out AIO4DOUT 1b: Output High Z 0b: Output VSSA AIO3 digital out AIO3DOUT 1b: Output High Z... -
Page 237: Soc.dinsig1
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION AIO3 digital input AIO3DIN 1b: Input high 0b: Input low AIO2 digital input AIO2DIN 1b: Input high 0b: Input low AIO1 digital input AIO1DIN 1b: Input high 0b: Input low... -
Page 238: Soc.sigintf
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION AIO8 digital input falling edge interrupt enable AIO8FEINTEN 1b: enabled 0b: disabled AIO7 digital input falling edge interrupt enable AIO7FEINTEN 1b: enabled 0b: disabled AIO6 digital input falling edge interrupt enable... -
Page 239: Figure 23-1. Configurable Analog Front End
PAC5223 User Guide Power Application Controller 23.2. Details of Operation 23.2.1. Block Diagram Figure 23-1. Configurable Analog Front End Configurable Analog Front End nIRQ2 GPIOB nIRQ1 Comparator S. E. AIOx Amplifier GPIOC Diff. Amplifier EMUX Application Specific Protection Power Driver 23.2.2. -
Page 240: Figure 23-2. Aio1, Aio0
PAC5223 User Guide Power Application Controller 23.3. AIO1, AIO0 23.3.1. Block Diagram Figure 23-2. AIO1, AIO0 AIO1 AIO0 Digital I/O SOC.AIOIN0.AIO0DIN I/O Logic Polarity SOC.AIOOUT0.AIO0DOUT SOC.AIO0CFG.POL0 SOC.AIO0CFG.OPT0 SOC.AIO0CFG.MUX0 SOC.AIO0CFG.MODE10 SOC.AIO1CFG.OPT1 SOC.AIO1CFG.MUX1 SOC.AIO0CFG.MODE10 SOC.AIO0OUT0.AIO1DIN I/O Logic Polarity SOC.AIO0OUT0.AIO1DOUT SOC.AIO1CFG.POL1 DBUS AIO1 AIO0 Differential Amplifier VREF/2 SOC.AIO1CFG.OS10EN... -
Page 241: Aio1, Aio0 Differential Amplifier Mode
PAC5223 User Guide Power Application Controller 23.3.3.1. AIO0 IO Set SOC.CFGAIO0.OPT0 = 00b to use AIO0 as input. The input state can be read at SOC.DINSIG0.AIO0DIN. Set SOC.CFGAIO0.OPT0 = 10b to use AIO0 as open drain output. Set SOC.CFGAIO0.MUX0 = 00b to mux the output state from SOC.DOUTSIG0.AIO0DOUT. - Page 242 PAC5223 User Guide Power Application Controller in the application specific power driver section. 23.3.5.1. HP10 Comparator The HP10 comparator takes the AIO1 voltage referenced to VSSA and compares it against the HP-DAC voltage. The 8-bit HP-DAC is programmable with SOC.HPDAC.
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Page 243: Figure 23-3. Aio3, Aio2
PAC5223 User Guide Power Application Controller 23.4. AIO3, AIO2 23.4.1. Block Diagram Figure 23-3. AIO3, AIO2 AIO3 AIO2 Digital I/O SOC.AIOIN0.AIO2DIN I/O Logic Polarity SOC.AIOOUT0.AIO2DOUT SOC.AIO2CFG.POL2 SOC.AIO2CFG.OPT2 SOC.AIO2CFG.MUX2 SOC.AIO2CFG.MODE32 SOC.AIO3CFG.OPT3 SOC.AIO3CFG.MUX3 SOC.AIO2CFG.MODE32 SOC.AIOOUT0.AIO3DIN I/O Logic Polarity SOC.AIOOUT0.AIO3DOUT SOC.AIO3CFG.POL3 DBUS AIO3 AIO2 Differential Amplifier VREF/2 SOC.AIO3CFG.OS32EN... -
Page 244: Aio3, Aio2 Differential Amplifier Mode Dao32
PAC5223 User Guide Power Application Controller 23.4.3.1. AIO2 IO Set SOC.CFGAIO2.OPT2 = 00b to use AIO2 as input. The input state can be read at SOC.DINSIG0.AIO2DIN. Set SOC.CFGAIO2.OPT2 = 10b to use AIO2 as open drain output. Set SOC.CFGAIO2.MUX2 = 00b to MUX the output state from SOC.DOUTSIG0.AIO2DOUT. - Page 245 PAC5223 User Guide Power Application Controller side comparator protector LP10 are also active that can be configured to disabled high-side or low-side drivers in the application specific power driver section. 23.4.5.1. HP32 Comparator The HP32 comparator takes the AIO3 voltage referenced to VSSA and compares it against the HP-DAC voltage.
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Page 246: Figure 23-4. Aio5, Aio4
PAC5223 User Guide Power Application Controller 23.5. AIO5, AIO4 23.5.1. Block Diagram Figure 23-4. AIO5, AIO4 AIO5 AIO4 Digital I/O SOC.AIOIN0.AIO4DIN I/O Logic Polarity SOC.AIOOUT0.AIO4DOUT SOC.AIO4CFG.POL4 SOC.AIO4CFG.OPT4 SOC.AIO4CFG.MUX4 SOC.AIO4CFG.MODE54 SOC.AIO5CFG.OPT5 SOC.AIO5CFG.MUX5 SOC.AIO4CFG.MODE54 SOC.AIOOUT0.AIO5DIN I/O Logic Polarity SOC.AIOOUT0.AIO5DOUT SOC.AIO5CFG.POL5 DBUS AIO5 AIO4 Differential Amplifier VREF/2 SOC.AIO5CFG.OS54EN... -
Page 247: Aio5, Aio4 Differential Amplifier Mode Dao54
PAC5223 User Guide Power Application Controller 23.5.3.1. AIO4 IO Set SOC.CFGAIO4.OPT4 = 00b to use AIO4 as input. The input state can be read at SOC.DINSIG0.AIO4DIN. Set SOC.CFGAIO4.OPT4 = 10b to use AIO4 as open drain output. Set SOC.CFGAIO4.MUX4 = 00b to MUX the output state from SOC.DOUTSIG0.AIO4DOUT. - Page 248 PAC5223 User Guide Power Application Controller side comparator protector LP54 are also active that can be configured to disabled high-side or low-side drivers in the application specific power driver section. 23.5.5.1. HP54 Comparator The HP54 comparator takes the AIO5 voltage referenced to VSSA and compares it against the HP-DAC voltage.
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Page 249: Figure 23-5. Aio6
PAC5223 User Guide Power Application Controller 23.6. AIO6 23.6.1. Block Diagram Figure 23-5. AIO6 AIO6 Digital I/O SOC.CFGAIO6.OPT6 SOC.AIOIN1.DIN6 SOC.CFGAIO6.MODE6 SOC.CFGAIO6.MUX6 SOC.AIOOUT1.DOUT6 nIRQ2 GPIOB SOC.AIOINTEN.AIO6REINTEN SOC.AIOINTEN.AIO6FEINTEN I/O Logic Polarity SOC.AIOINT.AIO6INT SOC.CFGAIO6.POL6 DBUS AIO6 Amplifier AIO6 ABUS SOC.CFGAIO6.MODE6 SOC.CFGAIO6.MUX6 SOC.AIOIN1.DIN6 SOC.AIOOUT1.DOUT6 SOC.CFGAIO6.GAIN6... -
Page 250: Aio6 Digital I/O Mode
PAC5223 User Guide Power Application Controller 23.6.3. AIO6 digital I/O Mode Set SOC.PWRSTAT.PBEN = 0b and SOC.CFGAIO6.MODE6 = 00b to use AIO6 as digital IO. 23.6.3.1. AIO6 IO Set SOC.CFGAIO6.OPT6 = 00b to use AIO6 as input. The input state can be read at SOC.DINSIG1.AIO6DIN. -
Page 251: Aio6 Special Mode
PAC5223 User Guide Power Application Controller 23.6.5.1. AIO6 Comparator Hysteresis Use SOC.SIGSET.AIO6HYS to enable AIO6 comparator hysteresis. 23.6.5.2. AIO6 Comparator setting Use SOC.CFGAIO6.OPT6 to set the compare value of the comparator to AB1, AB2, AB3 or VTHREF, setable with SOC.SYSSTAT.VTHREF. - Page 252 PAC5223 User Guide Power Application Controller 23.6.7.1. AIO6 Push Button Wake Up In Hibernate Wake Mode and enabled push button mode, if AIO6 is pulled low for the de-bouncing time period, the SOC.PWRCTL.HIB is cleared and the device powers up.
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Page 253: Figure 23-6. Aio7
PAC5223 User Guide Power Application Controller 23.7. AIO7 23.7.1. Block Diagram Figure 23-6. AIO7 AIO7 Digital I/O SOC.CFGAIO7.OPT7 SOC.AIOIN1.DIN7 SOC.CFGAIO7.MODE7 SOC.CFGAIO7.MUX7 SOC.AIOOUT1.DOUT7 nIRQ2 GPIOB SOC.AIOINTEN.AIO7REINTEN SOC.AIOINTEN.AIO7FEINTEN I/O Logic Polarity SOC.AIOINT.AIO7INT SOC.CFGAIO7.POL7 DBUS AIO7 Amplifier AIO7 ABUS SOC.CFGAIO7.MODE7 SOC.CFGAIO7.AMUX7 SOC.CFGAIO7.GAIN7 VSSA AIO7 Comparator SOC.CFGAIO7.MUX7... -
Page 254: Aio7 Single Ended Amplifier Mode
PAC5223 User Guide Power Application Controller 23.7.3.1. AIO7 IO Set SOC.CFGAIO7.OPT7 = 00b to use AIO7 as input. The input state can be read at SOC.DINSIG1.AIO7DIN. Set SOC.CFGAIO7.OPT7 = 10b to use AIO7 as open drain output. Set SOC.CFGAIO7.MUX7 = 00b to MUX the output state from SOC.DOUTSIG1.AIO7DOUT. -
Page 255: Aio7 Special Mode
PAC5223 User Guide Power Application Controller 23.7.5.2. AIO7 Comparator Reference Use SOC.CFGAIO7.OPT7 to set the compare value of the comparator to AB1, AB2, AB3 or VTHREF, setable with SOC.SYSSTAT.VTHREF. 23.7.5.3. AIO7 Comparator Polarity Use SOC.CFGAIO7.POL7 to set the output polarity of the comparator. - Page 256 PAC5223 User Guide Power Application Controller 23.7.6.6. AIO7 POS S/H Bypass Set SOC.CFGAIO8.OPT8[1] =0b bypass the POS S/H. Set SOC.CFGAIO8.OPT8[1] =1b use POS S/H for use with EMUX. 23.7.6.7. AIO7 nIRQ2/POS Selector Use SOC.CFGAIO8.OPT8[0] to select POS or nIRQ2 output.
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Page 257: Figure 23-7. Aio8
PAC5223 User Guide Power Application Controller 23.8. AIO8 23.8.1. Block Diagram Figure 23-7. AIO8 AIO8 Digital I/O SOC.CFGAIO8.OPT8 SOC.AIOIN1.DIN8 SOC.CFGAIO8.MODE8 SOC.CFGAIO8.MUX8 SOC.AIOOUT1.DOUT8 nIRQ2 GPIOB SOC.AIOINTEN.AIO8REINTEN SOC.AIOINTEN.AIO8FEINTEN I/O Logic Polarity SOC.AIOINT.AIO8INT SOC.CFGAIO8.POL8 DBUS AIO8 Amplifier AIO8 ABUS SOC.CFGAIO8.MODE8 SOC.CFGAIO8.AMUX8 SOC.CFGAIO8.GAIN8 VSSA AIO8 Comparator SOC.CFGAIO8.MUX8... -
Page 258: Aio8 Digital I/O Mode
PAC5223 User Guide Power Application Controller 23.8.3. AIO8 digital I/O Mode Set SOC.CFGAIO8.MODE8 = 00b to use AIO8 as digital IO. 23.8.3.1. AIO8 IO Set SOC.CFGAIO8.OPT8 = 00b to use AIO8 as input. The input state can be read at SOC.DINSIG0.AIO8DIN. -
Page 259: Aio8 Special Mode
PAC5223 User Guide Power Application Controller 23.8.5.2. AIO8 Comparator Reference Use SOC.CFGAIO8.OPT8 to set the compare value of the comparator to AB1, AB2, AB3 or VTHREF, setable with SOC.SYSSTAT.VTHREF. 23.8.5.3. AIO8 Comparator Polarity Use SOC.CFGAIO8.POL8 to set the output polarity of the comparator. - Page 260 PAC5223 User Guide Power Application Controller 23.8.6.5. AIO8 Comparator Output Use SOC.CFGAIO9.OPT9 to select AIO7, AIO8 or AIO9 comparator output signal for POS. 23.8.6.6. AIO8 POS S/H Bypass Set SOC.CFGAIO8.OPT8[1] =0b bypass the POS S/H. Set SOC.CFGAIO8.OPT8[1] =1b use POS S/H for use with EMUX.
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Page 261: Figure 23-8. Aio9
PAC5223 User Guide Power Application Controller 23.9. AIO9 23.9.1. Block Diagram Figure 23-8. AIO9 AIO9 Digital I/O SOC.CFGAIO9.OPT9 SOC.AIOIN1.DIN9 SOC.CFGAIO9.MODE9 SOC.CFGAIO9.MUX9 SOC.AIOOUT1.DOUT9 nIRQ2 GPIOB SOC.AIOINTEN.AIO9REINTEN SOC.AIOINTEN.AIO9FEINTEN I/O Logic Polarity SOC.AIOINT.AIO9INT SOC.CFGAIO9.POL9 DBUS AIO9 Amplifier AIO9 ABUS SOC.CFGAIO9.MODE9 SOC.CFGAIO9.AMUX9 SOC.CFGAIO9.GAIN9 VSSA... -
Page 262: Aio9 Digital I/O Mode
PAC5223 User Guide Power Application Controller 23.9.3. AIO9 digital I/O Mode Set SOC.CFGAIO9.MODE9 = 00b to use AIO9 as digital IO. 23.9.3.1. AIO9 IO Set SOC.CFGAIO9.OPT9 = 00b to use AIO9 as input. The input state can be read at SOC.DINSIG1.AIO9DIN. -
Page 263: Aio9 Special Mode
PAC5223 User Guide Power Application Controller 23.9.5.2. AIO9 Comparator Reference Use SOC.CFGAIO9.OPT9 to set the compare value of the comparator to AB1, AB2, AB3 or VTHREF, setable with SOC.SYSSTAT.VTHREF. 23.9.5.3. AIO9 Comparator Polarity Use SOC.CFGAIO9.POL9 to set the output polarity of the comparator. - Page 264 PAC5223 User Guide Power Application Controller 23.9.6.5. AIO9 Comparator Output Use SOC.CFGAIO9.OPT9 to select AIO7, AIO8 or AIO9 comparator output signal for POS. 23.9.6.6. AIO9 POS S/H Bypass Set SOC.CFGAIO8.OPT8[1] =0b bypass the POS S/H. Set SOC.CFGAIO8.OPT8[1] =1b use POS S/H for use with EMUX.
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Page 265: Figure 23-9. Emux
PAC5223 User Guide Power Application Controller 23.10. EMUX and ADMUX 23.10.1. Block Diagram Figure 23-9. EMUX EMUX DAOxy SOC.ADCSCANCFG.ADCBUFEN AIOx ABUS GPIOC VREF/2 ABUS SOC.AIO6CFG.ADMUX SOC.ADMUX DASH AIOx, AIOy EMUX EMUXCLK, EMUXDATA GPIOB AIO7, SOC.ADCSCANCFG.SCANEN AIO8, AIO9 23.10.2. EMUX The EMUX is a dedicated high speed low latency serial interface to control the ADMUX, the AIO7, AIO8, AIO9 POS S/H and the DAOxy S/H using the ASC0, ASC1 sequencer. -
Page 266: Figure 23-10. Emux Timing
PAC5223 User Guide Power Application Controller NAME DESCRIPTION AD MUX Channel Selector 1111b: VREF / 2 1110b: AB12 1101b: AB11 1100b: AB10 1011b: AB9 1010b: AB8 1001b: AB7 1000b: AB6 0111b: AB5 0110b: AB4 0101b: AB3 0100b: AB2 0011b: AB1... - Page 267 PAC5223 User Guide Power Application Controller 23.10.3.2. ADMUX Buffer Use SOC.ADCSCAN.ADCBUFEN to enable the ADMUX buffer. 23.10.3.3. ADMUX Use SOC.AIO6CFG.ADIN1 to route the output of the ADMUX to AB7 for debug purposes. - 267 - Rev 18‒March 4, 2018...
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Page 268: Table 24-1. Application Specific Power Driver Register Map
PAC5223 User Guide Power Application Controller 24. APPLICATION SPECIFIC POWER DRIVER 24.1. Register 24.1.1. Register Map Table 24-1. Application Specific Power Driver Register Map SOC ADDRESS NAME DESCRIPTION RESET VALUE Application Specific Power Driver 0x60 SOC.CFGDRV0 Driver Configuration 0 0x00 0x61 SOC.CFGDRV1... -
Page 269: Soc.cfgdrq6
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION High side PR1 protection enable HSPR1EN 1b: PR1 enabled 0b: PR1 disabled High side PR2 protection enable HSPR2EN 1b: PR2 enabled 0b: PR2 disabled Low side PR1 protection enable LSPR1EN... -
Page 270: Soc.doutdrv
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION Reserved Reserved, write to 0x0 OHI7 IO Setting 11b: Reserved OPT7 10b: Open-drain output 01b: Open-drain strong driver 00b: Input If CFGAIO0.OPT7 = 00b, AIO7 Input polarity setting. If CFGAIO0.OPT7 = 01b or 10b , AIO7 Output polarity setting. -
Page 271: Soc.endrv
PAC5223 User Guide Power Application Controller NAME ACCESS RESET DESCRIPTION OHI7 input OHI7DIN 1b: High 0b: Low OHI6 input OHI6DIN 1b: High 0b: Low Reserved Reserved, write to 0x0 24.1.8. SOC.ENDRV Register 24-7. SOC.ENDRV (Application Specific Power Driver Control, SOC 0x66) -
Page 272: Figure 24-1. Application Specific Power Driver
PAC5223 User Guide Power Application Controller 24.2. Details of Operation 24.2.1. Block Diagram Figure 24-1. Application Specific Power Driver Application Specific Power Drivers DRBx DRHx High Side Gate Driver DRSx DRLx Low Side GPIOA Gate Driver SOC Bus Registers Bridge... -
Page 273: Figure 24-2. Enhs1, Enls1 Protection
PAC5223 User Guide Power Application Controller 24.3. ENHS1, ENLS1 Protection 24.3.1. Block Diagram Figure 24-2. ENHS1, ENLS1 Protection ENLS1, ENLS1 Protection SOC.PROTCTL.PROTSEL Lowside Protection PR1, PR2 CAFE DRL0, ENLS1 DRL1, SOC.CFGDRV1.LSPR1EN DRL2 Highside Protection DRH3, ENHS1 DRH4, SOC.CFGDRV1.HSPR1EN DRH5 PROT... - Page 274 PAC5223 User Guide Power Application Controller select the input signal for this protection function. - 274 - Rev 18‒March 4, 2018...
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Page 275: Figure 24-3. Drl0
PAC5223 User Guide Power Application Controller 24.4. DRL0 Low Side Driver 24.4.1. Block Diagram Figure 24-3. DRL0 DRL0 Low Side Driver SOC.ENDRV.ENDRV DRL0 Propagation Delay GPIOA Enable SOC.DRVCFG0.PROP0 ENLS1 VSSP Protection ENLS1 DRH3 DRH3 SOC.ENBBM.ENBBM 24.4.2. DRL0 DRL0 is a push-pull low side gate driver, controlled by PA0 I/O. The gate driver has configurable propagation... -
Page 276: Figure 24-4. Drl1
PAC5223 User Guide Power Application Controller 24.5. DRL1 Low Side Driver 24.5.1. Block Diagram Figure 24-4. DRL1 DRL1 Low Side Driver SOC.ENDRV.ENDRV DRL1 Propagation Delay GPIOA Enable SOC.DRVCFG0.PROP1 ENLS1 VSSP Protection ENLS1 DRH3 DRH4 SOC.ENBBM.ENBBM 24.5.2. DRL1 DRL1 is a push-pull low side gate driver, controlled by PA1 I/O. The gate driver has configurable propagation... -
Page 277: Figure 24-5. Drl2
PAC5223 User Guide Power Application Controller 24.6. DRL2 Low Side Driver 24.6.1. Block Diagram Figure 24-5. DRL2 DRL2 Low Side Driver SOC.ENDRV.ENDRV DRL2 Propagation Delay GPIOA Enable SOC.DRVCFG0.PROP2 ENLS1 VSSP Protection ENLS1 DRH5 DRH4 SOC.ENBBM.ENBBM 24.6.2. DRL2 DRL2 is a push-pull low side gate driver, controlled by PA2 I/O. The gate driver has configurable propagation... -
Page 278: Figure 24-6. Drh3
PAC5223 User Guide Power Application Controller 24.7. DRH3 High Side Driver 24.7.1. Block Diagram Figure 24-6. DRH3 DRH5 High Side Driver DRB5 SOC.ENDRV.ENDRV DRH5 Propagation Delay GPIOA Enable SOC.DRVCFG1.PROP5 DRS5 ENHS1 Protection ENHS1 DRL2 DRL2 SOC.ENBBM.ENBBM 24.7.2. DRH3 DRH3 is a push-pull high side gate driver, controlled by PA3 I/O. The gate driver has configurable propagation delay, global driver enable, configurable make before break with DRL0 and configurable protection disable with ENHS1 signal from the configurable analog front end. -
Page 279: Figure 24-7. Drh4
PAC5223 User Guide Power Application Controller 24.8. DRH4 High Side Driver 24.8.1. Block Diagram Figure 24-7. DRH4 DRH4 High Side Driver DRB4 SOC.ENDRV.ENDRV DRH4 Propagation Delay GPIOA Enable SOC.DRVCFG1.PROP4 DRS4 ENHS1 Protection ENHS1 DRL1 DRL1 SOC.ENBBM.ENBBM 24.8.2. DRH4 DRH4 is a push-pull high side gate driver, controlled by PA4 I/O. The gate driver has configurable propagation delay, global driver enable, configurable make before break with DRL2 and configurable protection disable with ENHS1 signal from the configurable analog front end. -
Page 280: Figure 24-8. Drh5
PAC5223 User Guide Power Application Controller 24.9. DRH5 High Side Driver 24.9.1. Block Diagram Figure 24-8. DRH5 DRH5 High Side Driver DRB5 SOC.ENDRV.ENDRV DRH5 Propagation Delay GPIOA Enable SOC.DRVCFG1.PROP5 DRS5 ENHS1 Protection ENHS1 DRL2 DRL2 SOC.ENBBM.ENBBM 24.9.2. DRH5 DRH5 is a push-pull high side gate driver, controlled by PA5 I/O. The gate driver has configurable propagation delay, global driver enable, configurable make before break with DRL3 and configurable protection disable with ENHS1 signal from the configurable analog front end. -
Page 281: Figure 25-1. Cortex-M0 Implementation
PAC5223 User Guide Power Application Controller 25. ARM CORTEX-M0 REFERENCE 25.1. Introduction 25.1.1. Overview This chapter is taken from the ARM Cortex-M0 User Guide with minimal modifications made to account for the specific Cortex-M0 implementation. 25.1.2. About the Cortex-M0 processor and core peripherals The Cortex™-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of... - Page 282 PAC5223 User Guide Power Application Controller includes a non-maskable interrupt (NMI) • provides zero jitter interrupt option • provides four interrupt priority levels. • The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency.
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Page 283: Table 25-1. Summary Of Processor Mode And Stack Use Options
PAC5223 User Guide Power Application Controller 25.1.2.4.2. System Control Block The System Control Block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 25.1.2.4.3. System timer The system timer, SysTick, is a 24-bit count-down timer. -
Page 284: Table 25-2. Core Register Set Summary
PAC5223 User Guide Power Application Controller 25.2.1.3. Core Registers Figure 25-2. Core Registers Table 25-2. Core register set summary NAME TYPE* RESET VALUE DESCRIPTION R0 – R12 Unknown General Purpose Register,see chapter 25.2.1.3.1 on page 284 See description Stack pointer, see chapter 25.2.1.3.2 on page 285 Unknown Stack pointer, see chapter 25.2.1.3.2 on page 285... -
Page 285: Figure 25-3. Psr
PAC5223 User Guide Power Application Controller 25.2.1.3.2. Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: 0 = Main Stack Pointer (MSP). This Is the reset value. -
Page 286: Table 25-4. Apsr Bit Assignments
PAC5223 User Guide Power Application Controller write to the APSR using APSR with the MSR instruction. • The PSR combinations and attributes are: Table 25-3. Core register set summary REGISTER TYPE* COMBINATION RW *, ** APSR, EPSR, and IPSR IEPSR... -
Page 287: Table 25-6. Epsr Bit Assignments
PAC5223 User Guide Power Application Controller NAME FUNCTION This is the number of the current exception: 63-48: Reserved 47: IRQ31 16: IRQ0 15: SysTick Exception 14: PendSV Number 13-12: Reserved 11: SVCALL 10-4: Reserved 3: HardFault 2: NMI 1: Reserved 0: Thread mode see Exception types in chapter 25.2.3.2 on page 295... -
Page 288: Table 25-7. Primask Register Bit Assignments
PAC5223 User Guide Power Application Controller 25.2.1.3.10. Exception mask register The exception mask register disables the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks or code sequences requiring atomicity. To disable or re-enable exceptions, use the MSR and MRS instructions, or the CPS instruction, to change the value of PRIMASK. -
Page 289: Table 25-8. Control Register Bit Assignments
PAC5223 User Guide Power Application Controller Table 25-8. CONTROL register bit assignments NAME FUNCTION 31:1 Reserved Reserved Defines the current stack: Active Stack 1: MSP is the current stack pointer Pointer 0: PSP is the current stack pointer In Handler mode this bit reads as zero and ignores writes. -
Page 290: Memory Model
PAC5223 User Guide Power Application Controller 25.2.1.6. The Cortex Microcontroller Software Interface Standard ARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) for programming Cortex-M0 microcontrollers. The CMSIS is an integrated part of the device driver library. For a Cortex-M0 microcontroller... -
Page 291: Figure 25-6. Memory Map
PAC5223 User Guide Power Application Controller Figure 25-6. Memory Map The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers, see About the Cortex-M0 processor and core peripherals in chapter 25.1.2 on page 281 25.2.2.1. -
Page 292: Figure 25-7. Memory Ordering Restrictions
PAC5223 User Guide Power Application Controller 25.2.2.1.2. Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. 25.2.2.1.3. Strongly-ordered The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. -
Page 293: Table 25-9. Memory Access Behavior
PAC5223 User Guide Power Application Controller 25.2.2.3. Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 25-9. Memory Access Behavior ADDRESS MEMORY MEMORY DESCRIPTION RANGE REGION TYPE 0xFFFF FFFF – Device Device... - Page 294 PAC5223 User Guide Power Application Controller before subsequent instructions execute. See DSB in chapter 25.3.7.4 on page 336. 25.2.2.4.3. ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See ISB in chapter 25.3.7.5 on page336.
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Page 295: Figure 25-8. Little Endian Format
PAC5223 User Guide Power Application Controller Figure 25-8. Little Endian Format 25.2.3. Exception model This section describes the exception model. 25.2.3.1. Exception states Each exception is in one of the following states: 25.2.3.1.1. Inactive The exception is not active and not pending. -
Page 296: Table 25-10. Properties Of The Different Exception Types
PAC5223 User Guide Power Application Controller 25.2.3.2.1. Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. - Page 297 PAC5223 User Guide Power Application Controller EXCEPTION EXCEPTION PRIORITY VECTOR ADDRESS** ACTIVATION NUMBER* NUMBER* TYPE 12-13 Reserved PendSV Configurable*** 0x0000 0038 Asynchronous SysTick Configurable*** 0x0000 003C Asynchronous 0 and 16 and above Interrupt (IRQ) Configurable*** 0x0000 0040 and above**** Asynchronous...
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Page 298: Figure 25-9. Vector Table
PAC5223 User Guide Power Application Controller Figure 25-9. Vector Table The vector table is fixed at address 0x0000 0000. 25.2.3.5. Exception priorities As Table 25-10. Properties of the different exception types on page 296 shows, all exceptions have an associated priority, with: a lower priority value indicating a higher priority •... - Page 299 PAC5223 User Guide Power Application Controller Assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
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Page 300: Figure 25-10. Exception Entry Stack Contents
PAC5223 User Guide Power Application Controller 25.2.3.6.5. Exception entry Exception entry occurs when there is a pending exception with sufficient priority and either: the processor is in Thread mode • the new exception is of higher priority than the exception being handled, in which case the new •... -
Page 301: Table 25-11. Execution Return Behavior
PAC5223 User Guide Power Application Controller a POP instruction that loads the PC • a BX instruction using any register. • The processor saves an EXC_RETURN value to the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. Bits[31:4] of an EXC_RETURN value are 0xFFF FFFF. -
Page 302: Power Management
PAC5223 User Guide Power Application Controller processor is in lockup state it does not execute any instructions. The processor remains in lockup state until one of the following occurs: it is reset • a debugger halts it • an NMI occurs and the current lockup is in the HardFault handler. - Page 303 PAC5223 User Guide Power Application Controller If the event register is 1b, this indicates that the processor must not enter sleep mode on execution of a WFE instruction. Typically, this is because of the assertion of an external event, or because another processor in the system has executed a SEV instruction, see SEV in chapter 25.3.7.9 on page 339.
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Page 304: The Cortex-M0 Instruction Set
PAC5223 User Guide Power Application Controller The WIC is not programmable, and does not have any registers or user interface. It operates entirely from hardware signals. When the WIC is enabled and the processor enters deep sleep mode, the power management unit in the system can power down most of the Cortex-M0 processor. -
Page 305: Table 25-12. Cortex-M0 Instructions
PAC5223 User Guide Power Application Controller In Table 25-12. Cortex-M0 instructions: angle brackets, <>, enclose alternative forms of the operand • braces, {}, enclose optional operands and mnemonic parts • the Operands column is not exhaustive. • For more information on the instructions and operands, see the instruction descriptions. -
Page 306: Table 25-13. Cmsis Intrinsic Functions To Generate Some Cortex-M0 Instructions
PAC5223 User Guide Power Application Controller MNEMONIC OPERANDS BRIEF DESCRIPTION FLAGS CHAPTER, PAGE MULS Rd, Rn, Rm Multiply, 32-bit result N, Z Chapter 25.3.5.6, page 327 MVNS Rd, Rm Bitwise NOT N, Z Chapter 25.3.5.5, page 326 No Operation Chapter 25.3.7.8, page 339... -
Page 307: Table 25-14. Cmsis Intrinsic Functions To Access Special Registers
PAC5223 User Guide Power Application Controller INSTRUCTION CMSIS INTRINSIC FUNCTION void __DMB(void) void __NOP(void) uint32_t REV(uint32_t int value) REV16 uint32_t REV16(uint32_t int value) REVSH uint32_t REVSH(uint32_t int value) void __SEV(void) void __WFE(void) void __WFI(void) The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 25-14. -
Page 308: Figure 25-11. Asr #3
PAC5223 User Guide Power Application Controller 25.3.3.2. Restrictions when using PC or SP Many instructions are unable to use, or have restrictions on whether you can use, the Program Counter (PC) or Stack Pointer (SP) for the operands or destination register. See instruction descriptions for more information. -
Page 309: Figure 25-12. Lsr #3
PAC5223 User Guide Power Application Controller 25.3.3.3.2. LSR Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result, and it sets the left-hand n bits of the result to 0. See Figure 25-12. LSR #3 on page 309. -
Page 310: Figure 25-13. Lsl #3
PAC5223 User Guide Power Application Controller Figure 25-13. LSL #3 25.3.3.3.4. ROR Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right- hand 32-n bits of the result, and it moves the right-hand n bits of the register into the left-hand n bits of the result. - Page 311 PAC5223 User Guide Power Application Controller For most instructions, the value of the PC is the address of the current instruction plus 4 bytes. • Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a •...
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Page 312: Table 25-15. Condition Code Suffixes
PAC5223 User Guide Power Application Controller 25.3.3.6.2. Condition code suffixes Conditional branch is shown in syntax descriptions as B{cond}. A branch instruction with a condition code is only taken if the condition code flags in the APSR meet the specified condition, otherwise the branch instruction is ignored. - Page 313 PAC5223 User Guide Power Application Controller MNEMONIC BRIEF DESCIPTION PUSH and POP in chapter 25.3.4.6 on page PUSH Push Registers To Stack LDM and STM in chapter 25.3.4.5 on page Store Multiple Registers STR{type} Store Register Using Immediate Offset LDR and STR in chapter 25.3.4.2 on page 314...
- Page 314 PAC5223 User Guide Power Application Controller ADR R3, [PC,#996] ; Set R3 to value of PC + 996. 25.3.4.2. LDR and STR, immediate offset Load and Store with immediate offset. 25.3.4.2.1. Syntax LDR Rt, [<Rn | SP> {, #imm}] LDR<B|H> Rt, [Rn {, #imm}] STR Rt, [<Rn | SP>, {,#imm}]...
- Page 315 PAC5223 User Guide Power Application Controller 25.3.4.2.4. Condition flags These instructions do not change the flags. 25.3.4.2.5. Examples LDR R4, [R7] ; Loads R4 from the address in R7. STR R2, [R0,#const-struc] ; const-struc is an expression evaluating ; to a constant in the range 0-1020.
- Page 316 PAC5223 User Guide Power Application Controller the computed memory address must be divisible by the number of bytes in the load or store, see • Address alignment in chapter 25.3.3.4 on page 310. 25.3.4.3.4. Condition flags These instructions do not change the flags.
- Page 317 PAC5223 User Guide Power Application Controller 25.3.4.4.5. Examples LDR R0, LookUpTable ; Load R0 with a word of data from an address ; labeled as LookUpTable. LDR R3, [PC, #100] ; Load R3 with memory word at (PC + 100).
- Page 318 PAC5223 User Guide Power Application Controller 25.3.4.5.3. Restrictions In these instructions: •reglist and Rn are limited to R0-R7. • the writeback suffix must always be used unless the instruction is an LDM where reglist also contains • Rn, in which case the writeback suffix must not be used.
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Page 319: Table 25-17. Data Processing Instructions
PAC5223 User Guide Power Application Controller highest numbered register using the highest memory address. POP loads registers from the stack, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. - Page 320 PAC5223 User Guide Power Application Controller MNEMONIC BRIEF DESCIPTION AND, ORR, EOR, and BIC in chapter 25.3.5.2 BICS Bit Clear on page 322 CMP and CMN in chapter 25.3.5.4 on page Compare Negative CMP and CMN in chapter 25.3.5.4 on page Compare AND, ORR, EOR, and BIC in chapter 25.3.5.2...
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Page 321: Table 25-18. Adc, Add, Rsb, Sbc, And Sub Operand Restrictions
PAC5223 User Guide Power Application Controller ADD{S} {Rd,} Rn, <Rm|#imm> RSBS {Rd,} Rn, Rm, #0 SBCS {Rd,} Rn, Rm SUB{S} {Rd,} Rn, <Rm|#imm> Where: causes an ADD or SUB instruction to update flags specifies the result register specifies the first source register specifies the second source register specifies a constant immediate value. - Page 322 PAC5223 User Guide Power Application Controller INSTRUCTION RESTRICTIONS ADCS R0-R7 R0-R7 R0-R7 Rd and Rn must specify the same register Rd and Rn must specify the same register R0-R15 R0-R15 R0-PC Rn and Rm must not both specify PC R0-R7...
- Page 323 PAC5223 User Guide Power Application Controller 25.3.5.2.1. Syntax ANDS {Rd,} Rn, Rm ORRS {Rd,} Rn, Rm EORS {Rd,} Rn, Rm BICS {Rd,} Rn, Rm where: Rd is the destination register. Rn is the register holding the first operand and is the same as the destination register.
- Page 324 PAC5223 User Guide Power Application Controller BICS R0, R0, R1 25.3.5.3. ASR, LSL, LSR, and ROR Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right. 25.3.5.3.1. Syntax ASRS {Rd,} Rm, Rs ASRS {Rd,} Rm, #imm LSLS {Rd,} Rm, Rs...
- Page 325 PAC5223 User Guide Power Application Controller 25.3.5.3.3. Restrictions In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate instructions, Rd and Rm must specify the same register. 25.3.5.3.4. Condition flags These instructions update the N and Z flags according to the result.
- Page 326 PAC5223 User Guide Power Application Controller instruction, except that the result is discarded. 25.3.5.4.3. Restrictions For the: CMN instruction Rn, and Rm must only specify R0-R7. • CMP instruction: • Rn and Rm can specify R0-R14 • immediate must be in the range 0-255.
- Page 327 PAC5223 User Guide Power Application Controller 25.3.5.5.2. Operation The MOV instruction copies the value of Rm into Rd. The MOVS instruction performs the same operation as the MOV instruction, but also updates the N and Z flags. The MVNS instruction takes the value of Rm, performs a bitwise logical negate operation on the value, and places the result into Rd.
- Page 328 PAC5223 User Guide Power Application Controller 25.3.5.6.1. Syntax MULS Rd, Rn, Rm where: Rd is the destination register. Rn, Rm are registers holding the values to be multiplied. 25.3.5.6.2. Operation The MUL instruction multiplies the values in the registers specified by Rn and Rm, and places the least significant 32 bits of the result in Rd.
- Page 329 PAC5223 User Guide Power Application Controller REVSH Rd, Rn where: is the destination register. is the source register. 25.3.5.7.2. Operation Use these instructions to change endianness of data: REV converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into big-endian data.
- Page 330 PAC5223 User Guide Power Application Controller UXTH Rd, Rm where: Rd is the destination register. Rm is the register holding the value to be extended. 25.3.5.8.2. Operation These instructions extract bits from the resulting value: SXTB extracts bits[7:0] and sign extends to 32 bits •...
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Page 331: Table 25-19. Branch And Control Instructions
PAC5223 User Guide Power Application Controller is the register holding the first operand. the register to test against. 25.3.5.9.2. Operation This instruction tests the value in a register against another register. It updates the condition flags based on the result, but does not write the result to a register. -
Page 332: Table 25-20. Branch Ranges
PAC5223 User Guide Power Application Controller 25.3.6.1. B, BL, BX, and BLX Branch instructions. 25.3.6.1.1. Syntax B{cond} label BL label BX Rm BLX Rm where: cond is an optional condition code, see Conditional execution in chapter 25.3.3.6 on page 311. -
Page 333: Table 25-21. Miscellaneous Instructions
PAC5223 User Guide Power Application Controller and is discarded from the target address. • Note BCOND is the only conditional instruction on the Cortex-M0 processor. Condition flags These instructions do not change the flags. Examples B loopA ; Branch to loopA BL funC ;... - Page 334 PAC5223 User Guide Power Application Controller 25.3.7.1. BKPT Breakpoint. 25.3.7.1.1. Syntax BKPT #imm where: is an integer in the range 0-255. 25.3.7.1.2. Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- Page 335 PAC5223 User Guide Power Application Controller 25.3.7.2.2. Operation CPS changes the PRIMASK special register values. CPSID causes interrupts to be disabled by setting PRIMASK. CPSIE cause interrupts to be enabled by clearing PRIMASK. See Exception mask register in chapter 25.2.1.3.10 on page 288 for more information about these registers.
- Page 336 PAC5223 User Guide Power Application Controller 25.3.7.3.4. Condition flags This instruction does not change the flags. 25.3.7.3.5. Examples ; Data Memory Barrier 25.3.7.4. DSB Data Synchronization Barrier. 25.3.7.4.1. Syntax 25.3.7.4.2. Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes.
- Page 337 PAC5223 User Guide Power Application Controller 25.3.7.5.1. Syntax 25.3.7.5.2. Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.
- Page 338 PAC5223 User Guide Power Application Controller 25.3.7.6.3. Restrictions In this instruction, Rd must not be SP or PC. 25.3.7.6.4. Condition flags This instruction does not change the flags. 25.3.7.6.5. Examples MRS R0, PRIMASK ; Read PRIMASK value and write it to R0 25.3.7.7.
- Page 339 PAC5223 User Guide Power Application Controller 25.3.7.7.5. Examples MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register 25.3.7.8. NOP No Operation. 25.3.7.8.1. Syntax 25.3.7.8.2. Operation NOP performs no operation and is not guaranteed to be time consuming. The processor might remove it from the pipeline before it reaches the execution stage.
- Page 340 PAC5223 User Guide Power Application Controller 25.3.7.9.2. Operation SEV causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register, see Power management in chapter 25.2.5 on page 302. See also WFE in in chapter 25.3.7.11 on page 341.
- Page 341 PAC5223 User Guide Power Application Controller 25.3.7.10.4. Condition flags This instruction does not change the flags. 25.3.7.10.5. Examples SVC #0x32 ; Supervisor Call (SVC handler can extract the immediate value ; by locating it via the stacked PC) 25.3.7.11. WFE Wait For Event.
- Page 342 PAC5223 User Guide Power Application Controller 25.3.7.11.4. Condition flags This instruction does not change the flags. 25.3.7.11.5. Examples ; Wait for event 25.3.7.12. WFI Wait for Interrupt. 25.3.7.12.1. Syntax 25.3.7.12.2. Operation WFI suspends execution until one of the following events occurs: an exception •...
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Page 343: Table 25-22. Core Peripheral Register Regions
PAC5223 User Guide Power Application Controller 25.4. Cortex-M0 Peripherals The following sections are the reference material for the ARM Cortex-M0 core peripherals descriptions in a User Guide: About the Cortex-M0 peripherals in chapter 25.4.1 on page 343 • Nested Vectored Interrupt Controller in chapter 25.4.2 on page 343 •... -
Page 344: Table 25-24. Cmsis Access Nvic Functions
PAC5223 User Guide Power Application Controller ADDRESS NAME TYPE RESET VALUE DESCRIPTION 0xE000 E100 ISER 0x0000 0000 Interrupt Set-enable Register in chapter 25.4.2.2 on page 344 0xE000 E180 ICER 0x0000 0000 Interrupt Clear-enable Register in chapter 25.4.2.3 on page 345... -
Page 345: Table 25-26. Icer Bit Assignments
PAC5223 User Guide Power Application Controller NAME FUNCTION Interrupt set-enable bits. Write: 1: enable interrupt 31:0 SETENA 0: no effect Read: 1: interrupt enabled 0: interrupt disabled If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. -
Page 346: Table 25-27. Ispr Bit Assignments
PAC5223 User Guide Power Application Controller Table 25-27. ISPR bit assignments NAME FUNCTION Interrupt set-pending bits. Write: 1: changes interrupt state to pending 31:0 SETPEND 0: no effect Read: 1: changes interrupt state to pending 0: interrupt not pending Note... -
Page 347: Table 25-29. Ipr Bit Assignments
PAC5223 User Guide Power Application Controller Figure 25-19. IPR Table 25-29. IPR bit assignments NAME FUNCTION Priority, byte 31:24 offset 3 Priority, byte 23:16 Each priority field holds a priority value, 0-192. The lower the value, the greater the priority of the offset 2 corresponding interrupt. - Page 348 PAC5223 User Guide Power Application Controller detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt, see Hardware and software control of interrupts in chapter 25.4.2.7.1 on page 348. For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again.
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Page 349: Table 25-30. Cmsis Access Nvic Functions
PAC5223 User Guide Power Application Controller void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: Table 25-30. CMSIS access NVIC functions CMSIS FUNCTION DESCRIPTION void NVIC_EnableIRQ(IRQn_Type IRQn... -
Page 350: Table 25-32. Cpuid Register Bit Assignments
PAC5223 User Guide Power Application Controller 25.4.3.2. CPUID Register The CPUID register contains the processor part number, version, and implementation information. See the register summary in Table 25-32. CPUID register bit assignments on page 350 for its attributes. The bit assignments are: Figure 25-20. -
Page 351: Table 25-33. Icsr Register Bit Assignments
PAC5223 User Guide Power Application Controller Figure 25-21. ICSR Table 25-33. ICSR register bit assignments NAME TYPE FUNCTION NMI set-pending bit Write: 1: changes NMI exception state to pending 0: no effect Read: NMIPENDSET 1: NMI exception is pending 0: NMI exception is not pending Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. -
Page 352: Table 25-34. Aircr Register Bit Assignments
PAC5223 User Guide Power Application Controller NAME TYPE FUNCTION 21:18 Reserved Reserved Indicates the exception number of the highest priority pending enabled exception: 17:12 VECTPENDING RO Nonzero: the exception number of the highest priority pending enabled exception 0: no pending exceptions... -
Page 353: Table 25-35. Scr Register Bit Assignments
PAC5223 User Guide Power Application Controller NAME TYPE FUNCTION 14:3 Reserved Reserved System reset request: Read: This bit reads as 0. SYSRESETREQ WO Write: 1: requests a system level reset. 0: no effect VECTCLRACTIV Reserved for debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. -
Page 354: Table 25-36. Ccr Register Bit Assignments
PAC5223 User Guide Power Application Controller NAME TYPE FUNCTION Indicates sleep-on-exit when returning from Handler mode to Thread mode: 1: enter sleep, or deep sleep, on return from an ISR to Thread mode. SLEEPONEXIT 0: do not sleep when returning to Thread mode. -
Page 355: Table 25-37. System Fault Handler Priority Fields
PAC5223 User Guide Power Application Controller page 296 for more information. The system fault handlers, and the priority field and register for each handler are: Table 25-37. System fault handler priority fields HANDLER FIELD REGISTER DESCRIPTION SVCall PRI_11 System handler Priority Register 2 on page... -
Page 356: Table 25-40. System Timer Register Summary
PAC5223 User Guide Power Application Controller NAME TYPE FUNCTION 23:16 PRI_14 Priority of system Handler 14, PendSV 15:0 Reserved Reserved 25.4.3.8. SCB usage hints and tips Ensure software uses aligned 32-bit word size transactions to access all the SCB registers. -
Page 357: Table 25-41. Syst_Csr Register Bit Assignments
PAC5223 User Guide Power Application Controller Figure 25-27. SYST_CSR Table 25-41. SYST_CSR register bit assignments NAME TYPE FUNCTION 31:17 Reserved Reserved COUNTFLAG Returns 1 if timer counted to 0 since the last read of this register 15:3 Reserved Reserved Selects the SysTick timer clock source... -
Page 358: Table 25-43. Syst_Cvr Register Bit Assignments
PAC5223 User Guide Power Application Controller but this has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. - Page 359 PAC5223 User Guide Power Application Controller NAME TYPE FUNCTION 29:24 Reserved Reserved 23:0 TENMS Reads as zero. Indicates calibration value is not known If calibration information is not known, calculate the calibration value required from the frequency of the processor clock or external clock.
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Page 360: Legal Information
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