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PCIE-5565RC Series
ABACO PCIE-5565RC Series Manuals
Manuals and User Guides for ABACO PCIE-5565RC Series. We have
1
ABACO PCIE-5565RC Series manual available for free PDF download: Hardware Reference Manual
ABACO PCIE-5565RC Series Hardware Reference Manual (72 pages)
Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts
Brand:
ABACO
| Category:
PCI Card
| Size: 4.08 MB
Table of Contents
About this Manual
4
Conventions
4
Further Information
5
Technical Support Contact Information
6
Returns
6
Compliance
6
International Compliance
6
FCC Part 15
7
Canadian Regulations
7
Safety Summary
8
Overview
9
Features
9
PCI Express Compliance
9
Vendor and Device Identification
10
Subsystem Vendor ID and Subsystem ID
10
Comparison of the PCIE-5565RC and the VMIPCI-5565
10
Block Diagram
11
Figure 1 Block Diagram of PCIE-5565RC
11
Figure 2 Typical Reflective Memory Network
12
Table of Contents
13
1 Handling and Installation
18
Unpacking Procedures
18
Handling Precaution
18
Switch S1 and S2 Configuration
19
Before Installation Switch S1 and S2 Configuration
19
Table 1-1 Example Node ID Switch S2 RFM-5565
20
Table 1-2 Switch S1 Configuration RFM-5565
20
Figure 1-1 S1 and S2 Location PCIE-5565RC
21
Physical Installation
22
Figure 1-2 Installing the PCIE-5565RC
22
Front Panel Description
23
Figure 1-3 Front Panel of PCIE-5565RC
23
LED Description
24
Cable Configuration
24
Connector Specification (Singlemode and Multimode)
24
Table 1-3 LED Descriptions
24
Table 1-4 Cable Specifications for Multimode and Singlemode
24
Figure 1-4 LC Type Fiber-Optic Cable Connector
25
Figure 1-5 Example: Six Node Ring Connectivity PCIE-5565RC
26
2 Theory of Operation
27
Basic Operation
27
Front Bezel LED Indicators
27
RFM-5565 Register Sets
28
Reflective Memory RAM
28
Interrupt Circuits
29
Figure 2-1 Interrupt Circuitry Block Diagram
30
Network Interrupts
31
Redundant Transfer Mode of Operation
31
Rogue Packet Removal Operation
32
3 Programming
33
PCI Configuration Registers
34
Table 3-1 PCI Configuration Registers
34
Table 3-2 PCI Configuration ID Registers
34
Table 3-3 PCI Command Register
35
Table 3-4 PCI Status Register
36
Table 3-5 PCI Revision ID Register
37
Table 3-6 PCI Class Code Register
37
Table 3-7 PCI Cache Line Size Register
37
Table 3-8 PCI Latency Timer Register
38
Table 3-9 PCI Header Type Register
38
Table 3-10 PCI Built-In Self Test Register
38
Table 3-11 PCI Base Address Register 0 for Access to Local Configuration Registers
39
Table 3-12 PCI Base Address Register 1 for Access to Local Configuration Registers
40
Table 3-13 PCI Base Address Register 2 for Access to RFM Control and Status Registers
40
Table 3-14 PCI Base Address Register 3 for Access to Reflective Memory
41
Table 3-15 PCI Base Address Register 4
42
Table 3-16 PCI Base Address Register 5
42
Table 3-17 PCI Cardbus CIS Pointer Register
42
Table 3-18 PCI Subsystem Vendor ID Register
42
Table 3-19 PCI Subsystem ID Register
43
Table 3-20 PCI Expansion ROM Base Register
43
Table 3-21 PCI Capability Pointer Register
44
Table 3-22 PCI Interrupt Line
44
Table 3-23 PCI Interrupt Pin
44
Table 3-24 PCI Min_Gnt
44
Local Configuration Registers
45
Table 3-25 PCI Max_Lat
45
Table 3-26 Local Configuration and DMA Control Registers
45
Table 3-27 Mode/Dma Arbitration Register
46
Table 3-28 Big/Little Endian Descriptor Register
46
Table 3-29 Interrupt Control and Status Register
47
Table 3-30 INTCSR Interrupt Enables
48
Table 3-31 INTCSR Interrupt Status
48
Table 3-32 PCI Core/Features Revision ID
48
Table 3-33 DMA Channel 0 Mode Register
48
Table 3-34 DMA Channel 0 PCI Address Register
49
Table 3-35 DMA Channel 0 Local Address Register
49
Table 3-36 DMA Channel 0 Transfer Size (Bytes) Register
49
Table 3-37 DMA Channel 0 Descriptor Pointer Register
50
Table 3-38 DMA Channel 0 Command/Status Register
50
Table 3-39 DMA Channel 0 PCI Dual Address Cycles Upper Address
51
Table 3-40 PCI PIO Direct Slave Local Address Range
51
Table 3-41 PCI PIO Direct Slave Local Base Address (Remap)
51
RFM Control and Status Registers
53
Table 3-42 Memory Map of the Local Control and Status Registers
53
Board ID Register
54
Board Revision Build Register
54
Board Revision Register
54
Local Control and Status Register 1
54
Node ID Register
54
Table 3-43 Local Control and Status Register 1
54
Local Interrupt Control Registers
58
Table 3-44 Local Interrupt Status Register
58
Network Target Data Register
61
Network Target Node Register
61
Table 3-45 Local Interrupt Enable Register
61
Network Interrupt Command Register
62
Interrupt 1 Sender Data FIFO
62
Table 3-46 Network Interrupt Command Register
62
Interrupt 1 Sender ID FIFO
63
Interrupt 2 Sender Data FIFO
63
Interrupt 2 Sender ID FIFO
63
Interrupt 3 Sender Data FIFO
63
Interrupt 3 Sender ID FIFO
63
Interrupt 4 Sender Data FIFO
63
Interrupt 4 Sender ID FIFO
63
Figure 3-1 Block Diagram of the Network Interrupt Reception Circuitry
64
Example of a Block DMA Operation for RFM-5565
65
Example of a Scatter-Gather DMA Operation for RFM-5565
66
Example of a PCI PIO Sliding Window Operation for RFM-5565
68
Example of Network Interrupt Handling
69
Setup
69
Servicing Network Interrupts
70
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