Sony RDR-HX680 Service Manual page 64

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Pin No. Pin Name
B9 DDQM3
B10 Not open to public
B11 Not open to public
B12 Not open to public
B13 Not open to public
B14 Not open to public
B15 Not open to public
B16 Not open to public
B17 Not open to public
B18 SS0CKIN
B19 DA2_VDD3
B20 COMP1
B21 VAC
B22 VREF
B23 VAG
B24 COMP0
C1 DCLK
C2 DWEB
C3 DCS0B
C4 DADD10
C5 DADD02
C6 DDQS1
C7 DQ14
C8 DQ10
TE
L 13942296513
C9 DDQS3
C10 DILM
C11 Not open to public
C12 Not open to public
C13 Not open to public
C14 Not open to public
C15 Not open to public
C16 Not open to public
C17 Not open to public
C18 SDA1
C19 AOBCK
C20 AIOMCK0
C21 DA1_VDD3
C22 DA1_GND
C23 VCOMB
C24 VRTB
D1 DADD06
D2 DADD07
D3 DADD08
D4 DADD11
D5 DCKE
D6 DQ30
D7 DQ28
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D8 DQ26
D9 DQ24
D10 PHY_D7
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D11 PHY_D5
D12 PHY_D3
D13 PHY_D1
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I/O
O Output of data mask [3]
I Input of monitor sense
O Output of data [11]
O Output of data [8]
O Output of data [5]
O Output of data [2]
O Output of data enable
O Output of CTL signal [3]
I/O Input/output of DDC clock
I Input of serial clock signal
— Power supply input (3.0V for DAC)
— Fixed at "L"
O Output of DA converter for video signal chrominance
I Input of reference voltage
O Output of DA converter for analog video signal green/Y
— Fixed at "L"
O Output of positive clock for DDRSDRAM
O Output of command write enable
O Output of DDRSDRAM chip select [0]
O Output of DDRSDRAM address [10]
O Output of DDRSDRAM address [2]
I/O Input/output of data strobe [1]
I/O Input/output of DDRSDRAM data [14]
I/O Input/output of DDRSDRAM data [10]
I/O Input/output of data strobe [3]
— Fixed at "H"
O Output of CTL signal [2]
O Output of data [9]
O Output of data [6]
O Output of data [4]
O Output of data [1]
O Output of horizontal synchronization
I Input of hot plug detect
I/O Input/output of serial data
O Output of audio data clock
I/O Input/output of audio master clock [0]
— Power supply input (3.0V for DAC)
— GND (for DAC)
— Fixed at "L"
— Fixed at "L"
O Output of DDRSDRAM address [6]
O Output of DDRSDRAM address [7]
O Output of DDRSDRAM address [8]
O Output of DDRSDRAM address [11]
O Output of clock enable
I/O Input/output of DDRSDRAM data [30]
I/O Input/output of DDRSDRAM data [28]
I/O Input/output of DDRSDRAM data [26]
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I/O Input/output of DDRSDRAM data [24]
I/O Input/output of PHY-link data [7] for PHY
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I/O Input/output of PHY-link data [5] for PHY
I/O Input/output of PHY-link data [3] for PHY
I/O Input/output of PHY-link data [1] for PHY
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