Sony RDR-HX680 Service Manual page 60

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5-2. AV ENCODER/DECODER IC (IC1001:MC10050F1-505-LU1-A (RD-066 BOARD))
Pin No. Pin Name
A1 DGND
A2 DRASB
A3 DBA1
A4 DADD01
A5 DDQM1
A6 DQ13
A7 DQ11
A8 DQ08
A9 DIHM
A10 Not open to public
A11 Not open to public
A12 Not open to public
A13 Not open to public
A14 Not open to public
A15 Not open to public
A16 Not open to public
A17 Not open to public
A18 SS0DOUT
A19 DA2_GND
A20 VAY
A21 RSET1
A22 VAR
A23 RSET0
A24 VAB
TE
L 13942296513
AA1 MD14
AA2 LDQM
AA3 MD5
AA4 MD1
AA5 MD3
AA6 DVDD15(1.5V)
AA19 GPIO40
AA20 AIOBCK
AA21 RDATA02
AA22 RADD03
AA23 RADD08
AA24 FWEB/GWEB
AB1 MD2
AB2 UDQM
AB3 MD4
AB4 MCLKOUT
AB5 MD13
AB6 DVDD15(1.5V)
AB19 CTS1B
AB20 VIOCLK
AB21 SP1CLK
AB22 AIOBD
AB23 SP1STRT
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AB24 RADD15
AC1 MA9
AC2 MD12
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AC3 MA10
AC4 MCKE
AC5 MA7
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I/O
— Digital GND
O Output of RAS signal
O Output of bank address [1]
O Output of DDRSDRAM address [1]
O Output of data mask [1]
I/O Input/output of DDRSDRAM data [13]
I/O Input/output of DDRSDRAM data [11]
I/O Input/output of DDRSDRAM data [8]
— Fixed at "L"
O Output of power down
O Output of data [10]
O Output of data [7]
O Output of l clock
O Output of data [3]
O Output of data [0]
O Output of vertical synchronization
I/O Input/output of DDC data
O Output of serial data
— GND (for DAC)
O Output of DA converter for analog video signal Y
— Fixed at "L"
O Output of DA converter for analog video signal red
— Fixed at "L"
O Output of DA converter for analog video signal blue
I/O Input/output of buffer memory interface data bus [14]
O Output of lower byte data I/O mask control
I/O Input/output of buffer memory interface data bus [5]
I/O Input/output of buffer memory interface data bus [1]
I/O Input/output of buffer memory interface data bus [3]
— Power supply input
— Fixed at "L"
I/O Input/output of audio data clock
I/O Input/output of ROM/GIO data [2]
O Output of ROM/GIO address [3]
O Output of ROM/GIO address [8]
O Output of ROM/GIO write enable
I/O Input/output of buffer memory interface data bus [2]
O Output of upper byte data I/O mask control
I/O Input/output of buffer memory interface data bus [4]
O Output of clock for SDRAM
I/O Input/output of buffer memory interface data bus [13]
— Power supply input
I Input of clear to send
O Output of video pixel clock
— Fixed at GND
I/O Input/output of audio bitstream data
— Fixed at GND
O Output of ROM/GIO address [15]
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O Output of buffer memory interface address bus [9]
I/O Input/output of buffer memory interface data bus [12]
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O Output of buffer memory interface address bus [10]
O Output of SDRAM clock enable control
O Output of buffer memory interface address bus [7]
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8
Function
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5-3
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