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MAIN(OP DRV) SCHEMATIC DIAGRAM
REG_4.9V
REG_3.1V
GND
TO MAIN IF(CN103,112)
M_REG4.9
GND
R4987
TO P.PRCS
F/Z_RST
TO MAIN IF(CN105),
R4988
CAM_CLK
P.PRCS
R4989
TO P.PRCS
OP_CS
TO MAIN IF(CN105),
R4990
CAM_OUT
P.PRCS
TO P.PRCS
CLK27_AT
R4991 OPEN
VDIRS
TO GA,P.PRCS
R4992
CAM_VD
CAM_IN
TO P.PRCS
R4994
IRIS_PS
R4981
TO GA,P.PRCS
HDIRS
R4998
TO MAIN IF(CN112)
GATE_PLS
TO MAIN IF
IR_OUT
TL4901
TL4902
TL4903
TO V I/O
ASPECT
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-23(No.YF146)
5
4
C4924
1µ
C4923
1µ
IC4902
1
2
3
MM1614GN-X
C4927
0.01u
L4902
10µ
REG_4.9V_IC4901
NQL38DK-100X
C4903
10/10
T
L4901
NQR0129-002X
REG_3.1V_IC4901
C4902
10/6.3
T
L4904
NQL38DK-100X
C4935
10/10
T
L4903
10µ
NQL38DK-100X
C4932
10/10
T
0R0
0R0
0R0
0R0
0R0
0R0
0R0
0R0
IC4903
R1100D311C-X
1
2
3
C4925
C4926
1µ
1µ
C4936
0.01
C4905
0.1
R4993
470
R4925
100K
TL4915
R4944
0Ω
C4906
0.1
C4934
OPEN
N.C.
N.C.
N.C.
Dch
Cch
N.C.
N.C.
DVSS
DVDD(3V)
RETB
SCK
TEST0
TEST1
MONI0
TEST2
CS
SIN
CLK
VD
SOUT
PDWNB
HD
PLS1
PLS2
MODESEL
AVSS1
0
IC4901
JCY0223-X
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