Sanyo VPC-S122EXBL Service Manual page 4

3. IC901 (V Driver)
A V driver (IC901) is necessary in order to generate the clocks
(vertical transfer clock and electronic shutter clock) which
driver the CCD.
The signals (SCLK, SAV 0-2 and SDV 0-5) which are output
from IC101 are source of the vertical transfer clock, and are
decorded and superimposed at V driver.
The SUBCLK signal which is output from IC101 is used as
the sweep pulse for the electronic shutter.
XSG0
SAV2
XV0
XSG1
SAV1
XV2
SAV0
HlDrv0
SDV5
SDV4
SDV3
SDV2
XSG4
SDV1
DECODER
XV6
SDV0
XSG5
XV7
HlDrv2
SCLK
RESET
XSG8
CCDVH
XV10
XSG9
CCDVM1
XV11
CCDVM2
HlDrv4
CCDVM3
CCDVL
XSG12
XV15
SUBH
XSG13
XV16
SUBM
XV17
HlDrv6
DVDD
EP
NOTE: 3 DENOTES THREE-LEVEL DRIVERS
Fig. 1-3. IC901 Block Diagram
OV0
3
OV1
3
OV2
2
XSG2
OV3
3
XV3
XSG3
OV4
3
XV5
OV5
2
HlDrv1
OV6
3
OV7
3
OV8
2
XSG6
OV9
3
XV8
XSG7
OV10
3
XV9
OV11
2
HlDrv3
OV12
3
OV13
3
OV14
2
XSG10
OV15
XV12 3
XSG11
XV13 OV16
3
XV14
OV17
2
HlDrv5
OV18
3
OV19
3
OV20
2
XSG14
OV21
XV18 3
XV19
OV22
2H
HlDrv7
XV20
OV23
2H
HlDrv8
XV21
OV24
2H
HlDrv9
XSUBCLK
SUBCLK
XSUBMID 3
2 DENOTES TWO-LEVEL DRIVERS
2H DENOTES 2-LEVEL HIGH LOAD DRIVERS
4. IC902 (H Driver, CDS, AGC and A/D converter)
IC902 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver and reset pulse for CCD
image sensor are generated inside H1, H2, H3, H4 and RG
and output to CCD.
The video signal which is output from the CCD is input to pin
(25) of IC902. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the VGA (VGA: Variable Gain Amplifier). It is con-
verted internally into a small-amplitude actuating signal
(LVDS), and is then input to IC101. The gain of the VGA am-
plifier is controlled by pins (32), (33) and (34) using serial
signals which is output from IC101.
-3, 0, +3, +6dB
CDS
CCDIN
3V INPUT
LDO
REG
1.8V OUTPUT
RG
HORIZONTAL
HL
DRIVERS
4
H1 TO H4
GP01 GP02
Fig. 1-4. IC902 Block Diagram
– 4 –
REFT REFB
AD9971
VREF
6~42 dB
12-BIT
REDUCED
VGA
ADC
RANGE
LVDS
OUTPUT
CLAMP
INTERNAL
CLOCKS
PRECISION
INTERNAL
TIMING
REGISTERS
GENERATOR
SYNC
GENERATOR
HD VD
CLI
TCLKP
TCLKN
DOUT0P
DOUT0N
DOUT1P
DOUT1N
SL
SCK
SDATA