1.8V & 3.3V
lvdsrx_lock_on
R1A1~E1 +/‐
R1A2~E2 +/‐
R2A1~E1 +/‐
R2A2~E2 +/‐
R1CLK1 +/‐
LVDS‐RX
R1CLK2 +/‐
R2CLK1 +/‐
R2CLK2 +/‐
'0'
0
SCLKO
1
rxclkout_en
SSPLL
SSIC
SCLKI
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Only for training and service purposes
Local dimming Block
Local dimming Block
lvdsrx_pm
([6:0]*5)*4
clk_rx
clk_disp
rst_disp_n
clk_xtal
clk_iss
rst_xtal_n
0
clk_ss
1
clk25_sel
1
0
clk_vco
25MHz
VCO
+/- 10%
Local Dimming
(ld_core)
clk_xtal : I2C & BLC operation
clk_disp : Local Dimming Core operation
Modified 8/12
T1A1~E1 +/‐
lvdstx_pm
T1A2~E2 +/‐
T2A1~E1 +/‐
T2A2~E2 +/‐
([6:0]*5)*4
LVDS‐TX
T1CLK1 +/‐
T1CLK2 +/‐
T2CLK1 +/‐
T2CLK2 +/‐
M_VS
M_SCLK
M_MOSI
S_VS
S_SCLK
S_MOSI
LGE Internal Use Only