1. Manuals
  2. Brands
  3. Mips Technologies Manuals
  4. Motherboard
  5. Malta
  6. User manual

Mips Technologies Malta User Manual

Development board
Hide thumbs
Table of Contents

Advertisement

Quick Links

MIPS® Malta™ User's Manual
Document Number: MD00048
Revision 01.07
August 28, 2009
MIPS Technologies, Inc.
955 East Arques Avenue
Sunnyvale, CA 94085-4521
Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Malta and is the answer not in the manual?

Questions and answers

Summary of Contents for Mips Technologies Malta

  • Page 1 MIPS® Malta™ User’s Manual Document Number: MD00048 Revision 01.07 August 28, 2009 MIPS Technologies, Inc. 955 East Arques Avenue Sunnyvale, CA 94085-4521 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 2 This document contains information that is proprietary to MIPS Technologies, Inc. ("MIPS Technologies"). Any copying, reproducing, modifying or use of this information (in whole or in part) that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyright laws.

  • Page 3: Table Of Contents

    5.13: Flash Memory............................39 5.14: EEPROM ..............................39 5.15: AMR (Audio Modem Riser)........................40 5.16: Front Panel Connector ..........................40 5.17: Debug Access ............................40 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 4 7.1.8: CBUS ............................... 50 7.1.9: EJTAG.............................. 51 7.1.10: Misc..............................51 7.2: Signals............................... 52 7.2.1: J3 Connector............................ 53 7.2.2: J4 Connector............................ 55 7.3: Physical Design ............................56 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 5 Figure 7.1: CBUS Read Cycle ..........................50 Figure 7.2: CBUS Write Cycle..........................51 Figure 7.3: J3 and J4 Alignment ..........................57 Figure 7.4: Core Card Template Layout........................58 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 6 List of Tables Table 3.1: Malta Physical Memory Map ........................13 Table 3.2: I2C Slave Address Map ......................... 14 Table 3.3: REVISION Register ..........................14 Table 3.4: NMISTATUS Register ..........................15 Table 3.5: NMIACK Register........................... 16 Table 3.6: SWITCH Register........................... 16 Table 3.7: STATUS Register ..........................

  • Page 7: Chapter 1: Introduction

    The Malta Board provides a standard platform for software development with MIPS32® and MIPS64® processors. The platform is composed of two parts: the Malta Motherboard, which holds the CPU-independent parts of the cir- cuitry, and one or more CoreLV or CoreFPGA Core boards, which hold the MIPS CPU plus its System Controller and fast SDRAM memory.

  • Page 8: Figure 1.1: Malta Tm Development Platform Block Diagram

    4 Mbyte (x32) Interrupt Controller PROM Ethernet Am79C973 Ethernet Cypress Controller CY2278A PROM Clock/Synthesizer Driver AMR slot Crystal CS4281 Audio Reset Controller On/NMI PCI slot 1-4 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 9 The PCI bus is 32-bit, 33 MHz PCI standard version 2.2 compliant (Reference [1]), and allows devices on the bus DMA access to the DRAM on the Core Board. Four 5V PCI slots are provided on Malta to allow insertion of optional peripherals (for example, a video controller), and also to provide a way of monitoring traffic on this bus.
  • Page 10 Introduction MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 11: Chapter 2: Getting Started

    Chapter 2 Getting Started 2.1 Required Hardware In addition to the basic Malta motherboard, you will typically need: • a suitable standard ATX cabinet with power supply. For a power supply with stand-by capabilities, a minimum current of 720 mA is required (1A/1.5A peak recommended) for the 5V stand-by voltage.

  • Page 12: Wiring It Up

    2.3 Wiring It Up Begin by connecting the Core Board to the Malta motherboard. Notice that the connectors J3 and J4 have the same numbers on both boards, and one of the corner mounting pillars is offset to prevent incorrect insertion. When remov- ing the Core Board at some later date, be careful not to bend it.

  • Page 13: Chapter 3: Memory Map

    Chapter 3 Memory Map This chapter describes the Malta Board’s memory map and its control/status registers as seen by the CPU. The mem- ory map showing the starting addresses of the major devices on the board is shown in Table 3.1.

  • Page 14: Revision Information

    RAM is typically mapped at the bottom of memory, so that exception vectors are located in fast memory. Malta does not specify a mapping for addresses above 0x2000.0000. These addresses are accessed via kuseg, using mapping defined by TLB entries.

  • Page 15: Nmi Interrupts

    NMI interrupt controller. The NMI interrupt can be cleared by writing a “1” to the NMIACK register. Note that South Bridge NMI is acknowledged in the South Bridge. Name: NMIACK Address: 0x1F00.0104 Access: Reset Value: MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 16: Switches / Status

    The SWITCH, STATUS, and JPMRS registers allow software to monitor the state of various switches and jumpers on the Malta Board. All DIP switches have a value of “1” for a switch in the “ON” position. A switch is considered ON if any of the following are true: •...

  • Page 17: Displays

    1 = ON ASCIIWORD 0x0000.0010 Writing a 32-bit word to this register will cause it to be displayed in hex on the ASCII character display. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 18: Table 3.10 Ledbar Register

    Field Name Function Initial Value 31:8 Reserved Reserved 8 bits each corresponding to 1 LED (1 = ON) 0x00 Name: ASCIIWORD Address: 0x1F00.0410 Access: Reset Value: MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 19: Reset Control

    Initial Value 31:8 Reserved Reserved RESET Writing the magic value GORESET (==0x42) 0x00 to this field will initiate a board reset Name: BRKRES Address: 0x1F00.0508 Access: MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 20: Cbus Uart, Tty2

    (Divisor Latch Access Bit) of the Line Control Register is set. 3.8 General Purpose I/O The Malta Board has eight GP inputs and eight GP outputs connected to the Core Board. For usage details, refer to the documentation on the specific Core Board.

  • Page 21: I2C

    C controller: • I2CSEL: Selects between the FPGA I C controller and the South Bridge I C controller (the two I C controllers cannot co-exist). MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 22: Table 3.18 I2Cinp Register

    Reserved I2CSCL The value of this bit will be driven to the I2C SCL pin when the I2CSCL bit of the I2COE register is “1”. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 23: Table 3.21 I2Csel Register

    “0” means that the I2C controller in the FPGA is disabled and the I2C controller in the South Bridge is connected to the I2C bus. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 24 Memory Map MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 25: Chapter 4: Board Layout

    Chapter 4 Board Layout The basic layout of the Malta Board is shown in Figure 4.1. Figure 4.1 Malta Board Layout SPD100 STBY ON/NMI RESET ATX ON FPGA MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 26: Connectors & Jumpers

    The connector layout on the rear panel (namely, the shield design as described in Design Guide for Intel ATX Moth- erboard I/O Implementations Version 1.1 [13] is a subset of Intel Core design #1. This enables the Malta Board to be installed in an ordinary ATX chassis. Figure 4.2 shows the rear panel connector layout.

  • Page 27: Table 4.2 Jumpers

    Monitor Flash itself, regardless of the state of the Lock bits. When not Disables writing to the Monitor Flash lock fitted bits from software. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 28: Switches

    “CLOSED” (not in the “OPEN” position) will give a “1” in the appropriate register. Table 4.3 Switches Type Default Description 8-way All OFF This switch provides a value which can be read from the SWITCH register. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 29: Displays / Leds

    Jumper JP1. S5-2 When ON, set operation mode to big endian. If the endianess is changed, Malta must be reset again in order for the new endian mode to take effect. If the board is not reset unpredictable operation can occur.

  • Page 30: Table 4.5 Ethernet Connector Led Functionality

    Ethernet LED0: Link up (Programmable) Yellow Ethernet LED1: Activity (Programmable) All four ethernet LEDs are programmed/controlled by the ethernet controller. LED0-LED3 are linked to the four LEDs. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 31: Chapter 5: Hardware Description

    Chapter 5 Hardware Description This chapter describes the Malta Board’s hardware components. For more detailed information on these components, refer to the Malta Schematics [16]. 5.1 PCI Bus The PCI bus is implemented as a 5V, 32-bit and 33 MHz PCI standard version 2.2 compliant bus that connects the main components on the Malta Board.

  • Page 32: 1: Pci Arbiter

    Power On/Off is controlled by the South Bridge and its function is similar to a PC. The board also supports Power Management Events, for eample, Wake On LAN events, used for powering up in stand-by mode. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 33: Reset

    South Bridge internal devices (timer, real time clock, USB) • Super I/O devices (keyboard, 2 UARTs, floppy disk, parallel port, mouse) • Ethernet controller • Audio controller MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 34 PCI A..D interrupts including the South Bridge USB controller (using PCI D) are mapped on IRQ 0..15, which are further multiplexed to South Bridge INTR. Based on the interrupt sources, the South Bridge generates 3 interrupts : INTR, SMI, and NMI. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 35: Figure 5.2 Interrupt Wiring

    PCI bus has been configured. Please use the macros in the header file to access all registers and fields of the interrupt controller, as described in [3]. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 36: Table 5.2 Irq 0..15 Mapping

    South Bridge SMI South Bridge CBUS UART (tty2) Discrete 16550 COREHI Core Card CORELO Core Card Not used, driven inactive Typically used for CPU internal timer interrupt MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 37: Serial Ports

    5.7 Serial Ports There are 2 serial ports (tty0 and tty1) on Malta which are available on the rear edge via standard, male DB9 connec- tors (J6). These ports are provided by the Super I/O. A third serial port (tty2) is available via a 10-pin header (J22).

  • Page 38: 2: Serial Port Reset

    5.7.2 Serial Port Reset The tty0 port (J6) can be used to reset the Malta Board. By default, a “Break” condition on the tty0 port for more than 10 ms will reset the board, exactly as if the reset button had been pressed. This functionality can be disabled, or the time can be changed to a different value by programming the BRKRES register in the CBUS FPGA (see Section 3.6,...

  • Page 39: Real Time Clock (Rtc)

    For additional information about Compact Flash modules, see [15]. 5.13 Flash Memory Malta is fitted with 4 Mbytes of Flash memory (refered to as Monitor Flash), which is used to boot the system. See Chapter 3, “Memory Map” on page 13 for details of the Malta memory map.

  • Page 40: Amr (Audio Modem Riser)

    CPU core. See for details. 5.17.2 Hardware Debug You have access to most, if not all, interesting signals on the Malta Board via testpoints (Table 5.5) and HP Logic Analyser high-density connectors (Table 5.6).

  • Page 41: Table 5.6 Logic Analyser Connectors

    IIC + ASCII Clock PCI_CLK 33.33 MHz (default) Display 15:14 IIC_SCL, IIC_SDA IIC signals Not Used 12:8 ADA[4:0] ASCII display address ADD[7:0] ASCII display data MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 42 40 MHz Even 15:10 EJTRSTN, EJTDO, EJTDI, JTAG signals EJTMS, EJTCK, EJDINT PCI_INTAN, PCI_INTBN, PCI Interrupts PCI_INTCN, PCI_INTDN PCI_FRAMEN, PCI_IRDYN, PCI signals PCI_TRDY, PCI_DEVSELN, PCI_STOPN, PCI_LOCKN MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 43 ARBITER Clock PCI_CLK 33.33 MHz (default) 15:8 PCI_REQN_CORE, Requests PCI_REQN_SOUTHBRIDGE, PCI_REQN_ETHERNET, PCI_REQN_AUDIO, PCI_REQN_CON1, PCI_REQN_CON2, PCI_REQN_CON3, PCI_REQN_CON4 PCI_GNTN_CORE, Grants PCI_GNTN_SOUTHBRIDGE, PCI_GNTN_ETHERNET, PCI_GNTN_AUDIO, PCI_GNTN_CON1, PCI_GNTN_CON2, PCI_GNTN_CON3, PCI_GNTN_CON4 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 44 Hardware Description MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 45: Chapter 6: 1284 Flash Download Format

    Chapter 3, “Memory Map” on page The Malta Board’s Flash devices are organised in sectors of 64 Kbyte. “Erase” and “Set Lock Bit” commands operate on exactly one sector, this being the sector currently addressed. After the last block of 16 words in a sector are written into flash, the address counter has advanced to the next sector.

  • Page 46: Table 6.1 Download Codes

    Hex expected (always data blocks of 16 words), for example, a com- ment (#) is received in the middle of a block of 16 words Era susp Block erase suspended MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 47 Err prog Error in programming or set block lock-bits Low volt Low programming voltage detected Lock det Master lock-bit, Block lock-bit or RP# lock detected MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 48 1284 Flash Download Format MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 49: Chapter 7: Core Card Design

    Core cards must route all of these interrupts to the CPU—if the CPU chip has fewer external interrupt pins, they should be ORed together. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 50: 7: Endian

    All CBUS signals must use 3.3 volt signalling levels. Read and write cycles are schown in Figure 7.1and Figure 7.2. AC timing parameters are shown in Table 7.1. Figure 7.1 CBUS Read Cycle CA[25:2] ADDR CD[31:0] RD DATA CCSN CRDN MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 51: 9: Ejtag

    The EJTAG signals from the “basic” EJTAG connector are taken to the interface from the front panel connector. 7.1.10 Misc. Various debug, reserved, and presence-detect functions, as described in the following subsections. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 52: Signals

    Wired to zero, to indicate presence of Core down card. APRESN Input strong Wired to zero on the motherboard, to indicate down attachment. D12V Input Twelve volt power for possible fan MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 53: 1: J3 Connector

    Table 7.3 J3 Pin List Number Name Number Name Number Name Number Name CPWR_OK D3V3 JTGCPU CGPI4 CINTHIN CORE_OK CINTLON CGPO7 CGPI7 D3V3 CGPO6 CD31 CGPO5 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 54 CA24 CGPO0 CGPI1 CA25 EJTCK D3V3 CREV0 EJTMS CREV1 EJTDI D3V3 CREV2 CA23 EJTDO CWRN CREV3 CRDN EJTRSTN CCSN D3V3 CREV4 CGPI6 EJDINT CGPI5 CREV5 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 55: 2: J4 Connector

    PCI_AD31 PCI_AD30 D3V3 PCI_AD29 D3V3 PCI_AD28 PCI_CLK D3V3 D3V3 PCI_PAR PCI_FRAME PCI_IRDYN D3V3 PCI_AD27 D3V3 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD4 PCI_CBEN3 D3V3 PCI_CBEN2 D3V3 PCI_CBEN1 PCI_CBEN0 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 56: Physical Design

    The core card is 170mm x 100mm, and is mounted by pillars at each corner, plus 2 x 200-way (4 row x 25 pin) 1.27mm pitch connectors of type Samtec MOLC-150-31-x-Q. See Figure 7.4. Pin numbering on these connectors is shown in Figure 7.3. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 57: Figure 7.3 J3 And J4 Alignment

    The Core card is mounted at a height of 11mm over the motherboard when using the connectors given above. How- ever, the existing placement of high components on the Atlas and Malta motherboards results in the height restric- tions when placing components on the Core board, as shown in Table 7.5.

  • Page 58: Figure 7.4 Core Card Template Layout

    Figure 7.4 Core Card Template Layout connector center. “Zone 3” “Zone 1” TOP VIEW “Zone 2” 3.2 dia. Shaded zone: no tracks on outer layers. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
  • Page 59 Appendix A References This appendix lists other documents available from MIPS Technologies, Inc. that are referenced elsewhere in this document. These documents may be included in the $MIPS_HOME/$MIPS_CORE/doc area of a typical Core- Name soft or hard core release, or in some cases may be available on the MIPS web site, http://www.mips.com.
  • Page 60 References 15. CF+ and CompactFlash Specification. Revision 1.4 http://www.compactflash.org 16. MIPS Malta™ Schematics MIPS Document: MD00049 MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

  • Page 61: Revision History

    2002/06/10 Fixed Figure 3 with reference to keyboard and mouse connectors swapped. 01.06 2007/07/08 Updated document with Template nB1.03. 01.07 2009/08/28 Updated with new functionality of S5-3 switch.. MIPS® Malta™ User’s Manual, Revision 01.07 Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.

Table of Contents

Save PDF