Sanyo FISHER DVD-1500 Service Manual page 56

IC BLOCK DIAGRAM & DESCRIPTION
IC110 KM416S1120DT(1Mx16BIT CMOS DRAM)
Pin
System Clock
CLK
CS Chip Select
CKE Clock Enable
A0~A10/AP Address
Bank Select Address
BA
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ0~15 Data Input/Output
V /V Power Supply/Ground
DD SS
V /V Data Output Power/Ground
DDQ SSQ
No Connection/
N.C/RFU
Reserved for Future Use
IC480 SI-3050C(DC REGULATER)
1 3 5
2 4
IC710 TC7SHU04FU(INVERTER)
NC
1
IN A 2
GND
3
Name
Active on the positive going edge to sample all inputs.
Disables or enable device operation by masking or enabling all inputs except
CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least ono cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
Selects bank to be actiaeted during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses no the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in standing from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM ctive.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to probide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
IC490 STR-G6651(SWITCH REGULATER)
1. GND
2. V (on/off)
C
3. Vo
4. Vosense
5. V
IN
V
5
CC
OUT Y
4
Input Function
after the clock and masks the output.
SHZ
V
IN
4
START O.V.P LATCH
REG.
O.S.C
T.S.D
Pin No. Sym. Description
1 D Drain terminal
2
S Source terminal
3
GND Ground terminal
V Power Supply terminal
4
IN
Overcurrent/Feedback
5 O.C.P/F.B
terminal
Overvoltage protection
- O.V.P
circuit
Thermal shutdown
-
T.S.D.
circuit
- 71 -
DRIVE
-
Vth(1)
+
Comp.1
-
Vth(2)
+
Comp.2
Function
MOS FET drain
MOS FET source
Ground
Input of power supply for control
circuit
Input of overcurrent detection signal
and constant voltage control signal
Overvoltage protection circuit
Terminal shutdown circuit
1
D
2 S
O.C.P/F
5
GND
3