Onboard Bdtack Generation - Tandy 6000 Service Manual

Service Manual
If RIP* is asserted, an interrupt acknowledge cycle is in
progress and the interrupt vector data is valid from the
interrupt controller chip U 1 5 .
IODTACK* and RIP* are ORed together at U8 pins 9 and 10 and
the resultant output at U8 pin 8 clocks a low into the D
flip-flop (1/2 of U4 9 ) .
U49 pin 6, which is inverted by l/6th of U33 and used to
drive BDTACK* line low.
Address Strobe (AS) sets the flip-flop and negates BDTACK*
for the next bus cycle.
relationships for onboard BDTACK* generation.
Figure 7-6.
Generation of BDTACK* from offboard devices is only from the
MC68000 memory boards.
MC68000 memory board indicates that the data transfer has
been completed.
During a write cycle, BDTACK* indicates that the data from
the data bus has been written into memory and has completed
the transfer. During a read cycle, BDTACK* indicates that
the data requested is present on the data bus.
details on memory BDTACK* generation, refer to Paragraph 7.2
Memory Board Theory of Operation.
BDTACK* is also generated when an External time-out (TMERRE)
occurs. This allows the WAIT* signal from U36 to the Z80A to
be negated and release the Z80A CPU. During an internal
time-out (TMERRI), BDTACK* is not required because BERR* is
asserted which will terminate to the MC68000 cycle.
TANDY COMPUTER PRODUCTS
This results in a high output at
Figure 7-6 shows the timing

Onboard BDTACK Generation

BDTACK* being asserted from an
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TANDY 6000/6000-HD
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