Related Manuals for M-Systems Flash Disk Pioneers Flash Memory
Summary of Contents for M-Systems Flash Disk Pioneers Flash Memory
- Page 1 White Paper Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory Written by: Raz Dan and Rochelle Singer JANUARY 2003 91-SR-014-02-8L, REV 1.0...
- Page 2 In an attempt to gain grounds in these highly competitive markets, vendors of flash memory are trying to squeeze more and more capacity into constantly shrinking silicon dies, thereby optimizing both size and cost benefits.
- Page 3 Comparing Binary and MLC Flash Technologies Basic Flash Technology Figure 1 shows the basic structure of a flash memory cell, which is similar to a standard MOS transistor. However, unlike a standard transistor, a flash cell must be able to retain charge after power removal in order to permanently store data.
- Page 4 Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory Select Gate Oxide Floating Gate Program Erase (Inject electrons) (Remove electrons) Source Drain Substrate Figure 1: A Basic Flash Cell Binary and MLC Technologies In flash devices that implement Binary flash technology, there are two possible ranges for V .
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Page 5: Data Reliability
MLC flash errors is two orders of magnitude worse. Long-Term Data Errors Flash memory cells must provide long-term data retention capabilities to function reliably as a non- volatile memory device. In order to do this, the long-term stability of voltage levels is critical. - Page 6 Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory Read Disturb Errors The read disturb effect causes a page read operation to induce a permanent, bit value change in one of the read bits. In Binary flash technology based on a 0.16µ manufacturing process, the typical read disturb error rate is on the order of 1 bit error per 10 repetitive reads of the page containing the bit.
- Page 7 Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory Sustained Read When comparing sustained read performance values in real-world scenarios for Binary Flash with MLC, the gap lessens considerably: MLC performance is 98 percent of Binary flash performance. Operations that both Binary flash and MLC require to support a sustained read operation – such as running the driver code and the file system code, and accumulating bus cycles to support address, command, error correction code and control information –...
- Page 8 Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory Overcoming MLC Limitations Because MLC technology can potentially bring the industry breakthrough cost and size benefits for local data and code storage, M-Systems chose to take on the challenge of perfecting it by providing solutions to overcome MLC reliability, performance and flash management limitations.
- Page 9 Table 1 maps the various features of x2 technology against the three major areas of MLC limitations that they overcome. The remainder of this section explains how each feature achieves these enhancements in Mobile DiskOnChip G3. Table 1: Overcoming MLC Limitations with x2-based Mobile DiskOnChip G3 x2 Technology Feature Robust flash management Enhanced EDC...
- Page 10 Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory Enhanced EDC and ECC The Error Detection Code (EDC) and Error Correction Code (ECC) developed for x2 technology is based on M-Systems’ highly effective combination used in previous generation DiskOnChip products. This system contains hardware-embedded EDC mechanism to detect errors on-the-fly and software-embedded ECC mechanism to reduce silicon size and cost.
- Page 11 Efficient Bad Block Handling x2 technology handles bad blocks, which can be randomly present in flash media, by enabling unaligned block access to two planes. Bad blocks are mapped individually on each plane, as shown in Figure 4. Good units can therefore be aligned or unaligned, minimizing the effects of bad blocks on the media.
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Page 12: Dma Support
MultiBurst To improve MLC read performance rates, x2 technology incorporates a feature called MultiBurst. MultiBurst enables parallel read access from two 16-bit planes to the flash controller, thereby achieving the desired output data rate for the host. The host accesses the first word of a page with a relatively slow access time, but each subsequent word with a very fast access time. -
Page 13: Power Consumption
Parallel Multiplane Access As discussed earlier, the MLC flash media is built of two planes that can operate in parallel. This architecture is one of the most powerful, x2 technology innovations, doubling read, write and erase performance. Two pages on different planes can be concurrently read or written if they have the same offset within their respective blocks, even if the blocks are unaligned. -
Page 14: How To Contact Us
© 2003 M-Systems Flash Disk Pioneers, Ltd. All rights reserved. This document is for information use only and is subject to change without prior notice. M-Systems Flash Disk Pioneers Ltd. assumes no responsibility for any errors that may appear in this document. No part of this document may be reproduced, transmitted, transcribed, stored in a retrievable manner or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without prior written consent of M-Systems.