Harmony Gsm_Rx (U100) - Motorola V975 Service Manual

Service Manual(Level 3)
mixer amplifier. Large integrated capacitors are used to
provide a low-frequency, low-pass corner at the out-
put of the mixer. The signal then passes through baseband
amplification and anti-aliasing filtering. The output of
ALGAE MB will be balanced RXI and RXQ signal. It
will have a 100kHz Very Low Intermediate Frequency
(VLIF) signal that will be sent to the Harmony for Ana-
log to digital conversion.
The LO signal is provided by a fully integrated VCO
that drives either a divide-by-two or divide-by-four
quadrature generator. In addition, a divide-by-3or5 cir-
cuit is used to feed back the LO signal to the synthe-
sizer. The divide-by-3or5 circuit drives a differential
output stage that provides the appropriate power level
to the synthesizer. This output stage is shared with the
TX path and provides the synthesizer feedback signal
in both transmit and receive.

HARMONY GSM_RX (U100)

The RXI and RXQ VLIF signal entering the Harmony
is sent to the Sigma-Delta modulator which transforms
the slow moving analog signal into a high speed digital
output. The Sigma-Delta modulator is set as an Ana-
log-to-Digital Converter (ADC). The output of the
Sigma-Delta modulator is then fed into the Receive
Coprocessor (RxCPROC).
Figure 3-6. Harmony (GSM RX)
MB_RX_I
MB_RX_IX
MB_RX_Q
MB_RX_QX
HARMONY
(U100)
Draft 1.0 Motorola Confidential Proprietary
The RxCPROC includes the digital signal processing
hardware required for the receive transceiver (Rx) af-
ter the initial conversion done by the sigma-delta modu-
lator. It's configured to be used in the very low interme-
diate frequency mode (VLIF). The RxCPROC sup-
ports the GSM and EDGE standards.
The RxCPROC is represented by blocks listed as "deci-
mation filters", "digital IF mixer", "digital LO" and "se-
rial interface". The RxCPROC decimates and filters the
I and Q quadrature input signals and converts them to
baseband. Processed signals are sent serially to the Base
Band Port (BBP) to be further handled by the DSP and
VIAC.
A serial bus consisting of SDFS and SDRX will trans-
mit the RXI and RXQ data to the BBP module in the
POG. SDFS is a framing signal which marks the begin-
ning of an I,Q transfer. SDRX is the serial data. The
clock used for the serial transfer is SCLK.
The RxCPROC is controlled via the SEQUENCE
MANGER or SPI. Each control line of the Seq. Man-
ager can be overridden by a corresponding line from
the SPI (MB_SPI_CLK, MB_SPI_MOSI). Layer One
timer signals (MB_RX_ON, MBRX_ACQ,
MBRX_SLOT) from POG control the start of major
sequences of events.
Theory of Operation
RF GSM Receiver
3-5