Sanyo VPC-HD700 Service Manual page 5

1-2. CP1 and VF1 CIRCUIT DESCRIPTION
1. Circuit Description
1-1. Digital clamp
The optical black section of the CCD extracts averaged values
from the subsequent data to make the black level of the CCD
output data uniform for each line. The optical black section of
the CCD averaged value for each line is taken as the sum of
the value for the previous line multiplied by the coefficient k
and the value for the current line multiplied by the coefficient
1-k.
1-2. Signal processor
1. γ correction circuit
This circuit performs (gamma) correction in order to maintain
a linear relationship between the light input to the camera and
the light output from the picture screen.
2. Color generation circuit
This circuit converts the CCD data into RGB signals.
3. Matrix circuit
This circuit generates the Y signals, R-Y signals and B-Y sig-
nals from the RGB signals.
4. Horizontal and vertical aperture circuit
This circuit is used gemerate the aperture signal.
1-3. AE/AWB and AF computing circuit
The AE/AWB carries out computation based on a 64-segment
screen, and the AF carries out computations based on a 6-
segment screen.
1-4. SDRAM controller
This circuit outputs address, RAS, CAS and CLOCK data for
controlling the SDRAM. It also refreshes the SDRAM.
1-5. Communication control
1. SIO
This is the interface for the 8-bit microprocessor.
2. PIO/PWM/SIO for LCD
8-bit parallel input and output makes it possible to switch be-
tween individual input/output and PWM input/output.
1-6. TG/SG
Timing generated for 7 million pixel horizontal addtion CCD
control.
1-7. Digital encorder
It generates chroma signal from color difference signal.
2. Outline of Operation
When the shutter opens, the reset signals (ASIC and CPU)
and the serial signals ("take a picture" commands) from the 8-
bit microprocessor are input and operation starts. When the
TG/SG drives the CCD, picture data passes through the A/D
and CDS, and is converted internally into a small-amplitude
actuating signal, and is then input to ASIC. The data that is
input to the ASIC is input to the SDRAM through digital clamp.
The AF, AE, AWB, shutter, and AGC value are computed from
this data to obtain the optimum picture. The data which has
already been stored in the SDRAM is read by the CPU and
color generation is carried out. Each pixel is interpolated from
the surrounding data as being either R, G, and B primary color
data to produce R, G and B data. At this time, correction of the
lens distortion which is a characteristic of wide-angle lenses is
carried out. After AWB and γ processing are carried out, a matrix
is generated and aperture correction is carried out for the Y
signal, and the data is then compressed by JPEG and is then
written to card memory (SD card).
When played back on the LCD and monitor, data is transferred
from memery to the SDRAM, and the image is then elongated
so that it is displayed over the SDRAM display area.
3. LCD Block
The LCD display circuit is located on the CP1 board, and
consists of components such as a power circuit.
The signals from the ASIC are 8-bit digital signals, that is
input to the LCD directly. The 8-bit digital signals are con-
verted to RGB signals inside the LCD driver circuit . This LCD
has a 3-wire serial, and functions such as the brightness and
image quality are controlled.
Because the LCD closes more as the difference in potential
between the VCOM (common polar voltage: AC) and the R,
G and B signals becomes greater, the display becomes darker;
if the difference in potential is smaller, the element opens and
the LCD become brighter.
In addition, the timing pulses for signals other than the video
signals are also input from the ASIC directory to the LCD.
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